About the Execution of LoLA for Echo-PT-d03r05
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
6058.756 | 1563350.00 | 1563832.00 | 3643.40 | ?F????TF?F??TT?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851200090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Echo-PT-d03r05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851200090
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.6K Feb 25 14:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 14:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 14:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 14:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 716K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d03r05-CTLFireability-00
FORMULA_NAME Echo-PT-d03r05-CTLFireability-01
FORMULA_NAME Echo-PT-d03r05-CTLFireability-02
FORMULA_NAME Echo-PT-d03r05-CTLFireability-03
FORMULA_NAME Echo-PT-d03r05-CTLFireability-04
FORMULA_NAME Echo-PT-d03r05-CTLFireability-05
FORMULA_NAME Echo-PT-d03r05-CTLFireability-06
FORMULA_NAME Echo-PT-d03r05-CTLFireability-07
FORMULA_NAME Echo-PT-d03r05-CTLFireability-08
FORMULA_NAME Echo-PT-d03r05-CTLFireability-09
FORMULA_NAME Echo-PT-d03r05-CTLFireability-10
FORMULA_NAME Echo-PT-d03r05-CTLFireability-11
FORMULA_NAME Echo-PT-d03r05-CTLFireability-12
FORMULA_NAME Echo-PT-d03r05-CTLFireability-13
FORMULA_NAME Echo-PT-d03r05-CTLFireability-14
FORMULA_NAME Echo-PT-d03r05-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678414695779
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d03r05
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT Echo-PT-d03r05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA Echo-PT-d03r05-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Echo-PT-d03r05-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Echo-PT-d03r05-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Echo-PT-d03r05-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Echo-PT-d03r05-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Echo-PT-d03r05-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678416259129
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 28 (type EXCL) for 21 Echo-PT-d03r05-CTLFireability-07
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 3/199 1/32 Echo-PT-d03r05-CTLFireability-07 182254 m, 36450 m/sec, 1366853 t fired, .
Time elapsed: 7 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 8/199 2/32 Echo-PT-d03r05-CTLFireability-07 427494 m, 49048 m/sec, 3442032 t fired, .
Time elapsed: 12 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 13/199 3/32 Echo-PT-d03r05-CTLFireability-07 666067 m, 47714 m/sec, 5531077 t fired, .
Time elapsed: 17 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 18/199 4/32 Echo-PT-d03r05-CTLFireability-07 900498 m, 46886 m/sec, 7617541 t fired, .
Time elapsed: 22 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 23/199 6/32 Echo-PT-d03r05-CTLFireability-07 1133155 m, 46531 m/sec, 9707353 t fired, .
Time elapsed: 27 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 28/199 7/32 Echo-PT-d03r05-CTLFireability-07 1367727 m, 46914 m/sec, 11779536 t fired, .
Time elapsed: 32 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 33/199 7/32 Echo-PT-d03r05-CTLFireability-07 1583659 m, 43186 m/sec, 13861806 t fired, .
Time elapsed: 37 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 38/199 8/32 Echo-PT-d03r05-CTLFireability-07 1795728 m, 42413 m/sec, 15940547 t fired, .
Time elapsed: 42 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 43/199 9/32 Echo-PT-d03r05-CTLFireability-07 2005654 m, 41985 m/sec, 18014811 t fired, .
Time elapsed: 47 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 48/199 10/32 Echo-PT-d03r05-CTLFireability-07 2213097 m, 41488 m/sec, 20096254 t fired, .
Time elapsed: 52 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 53/199 11/32 Echo-PT-d03r05-CTLFireability-07 2446745 m, 46729 m/sec, 22174574 t fired, .
Time elapsed: 57 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 58/199 12/32 Echo-PT-d03r05-CTLFireability-07 2666318 m, 43914 m/sec, 24252660 t fired, .
Time elapsed: 62 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 63/199 13/32 Echo-PT-d03r05-CTLFireability-07 2878604 m, 42457 m/sec, 26330160 t fired, .
Time elapsed: 67 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 68/199 14/32 Echo-PT-d03r05-CTLFireability-07 3085777 m, 41434 m/sec, 28405592 t fired, .
Time elapsed: 72 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 73/199 15/32 Echo-PT-d03r05-CTLFireability-07 3297243 m, 42293 m/sec, 30495329 t fired, .
Time elapsed: 77 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 78/199 16/32 Echo-PT-d03r05-CTLFireability-07 3525042 m, 45559 m/sec, 32545210 t fired, .
Time elapsed: 82 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 83/199 17/32 Echo-PT-d03r05-CTLFireability-07 3736918 m, 42375 m/sec, 34588413 t fired, .
Time elapsed: 87 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 88/199 18/32 Echo-PT-d03r05-CTLFireability-07 3948400 m, 42296 m/sec, 36658197 t fired, .
Time elapsed: 92 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 93/199 19/32 Echo-PT-d03r05-CTLFireability-07 4160878 m, 42495 m/sec, 38739211 t fired, .
Time elapsed: 97 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 98/199 20/32 Echo-PT-d03r05-CTLFireability-07 4372020 m, 42228 m/sec, 40799327 t fired, .
Time elapsed: 102 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 103/199 21/32 Echo-PT-d03r05-CTLFireability-07 4566215 m, 38839 m/sec, 42874754 t fired, .
Time elapsed: 107 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 108/199 22/32 Echo-PT-d03r05-CTLFireability-07 4757488 m, 38254 m/sec, 44938294 t fired, .
Time elapsed: 112 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 113/199 22/32 Echo-PT-d03r05-CTLFireability-07 4950393 m, 38581 m/sec, 47015662 t fired, .
Time elapsed: 117 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 118/199 23/32 Echo-PT-d03r05-CTLFireability-07 5157101 m, 41341 m/sec, 49089004 t fired, .
Time elapsed: 122 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 123/199 24/32 Echo-PT-d03r05-CTLFireability-07 5355579 m, 39695 m/sec, 51157292 t fired, .
Time elapsed: 127 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 128/199 25/32 Echo-PT-d03r05-CTLFireability-07 5547662 m, 38416 m/sec, 53227733 t fired, .
Time elapsed: 132 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 133/199 26/32 Echo-PT-d03r05-CTLFireability-07 5739443 m, 38356 m/sec, 55302649 t fired, .
Time elapsed: 137 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 138/199 27/32 Echo-PT-d03r05-CTLFireability-07 5953182 m, 42747 m/sec, 57381436 t fired, .
Time elapsed: 142 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 143/199 28/32 Echo-PT-d03r05-CTLFireability-07 6176346 m, 44632 m/sec, 59456002 t fired, .
Time elapsed: 147 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 148/199 29/32 Echo-PT-d03r05-CTLFireability-07 6388289 m, 42388 m/sec, 61529859 t fired, .
Time elapsed: 152 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 153/199 30/32 Echo-PT-d03r05-CTLFireability-07 6600982 m, 42538 m/sec, 63611130 t fired, .
Time elapsed: 157 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 158/199 31/32 Echo-PT-d03r05-CTLFireability-07 6813345 m, 42472 m/sec, 65683309 t fired, .
Time elapsed: 162 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 163/199 32/32 Echo-PT-d03r05-CTLFireability-07 7012182 m, 39767 m/sec, 67749702 t fired, .
Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 1 0 3 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 168/199 32/32 Echo-PT-d03r05-CTLFireability-07 7203617 m, 38287 m/sec, 69818516 t fired, .
Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for Echo-PT-d03r05-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 50 Echo-PT-d03r05-CTLFireability-14
lola: time limit : 201 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 5/201 2/32 Echo-PT-d03r05-CTLFireability-14 248389 m, 49677 m/sec, 1654749 t fired, .
Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 10/201 3/32 Echo-PT-d03r05-CTLFireability-14 470487 m, 44419 m/sec, 3344596 t fired, .
Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 15/201 4/32 Echo-PT-d03r05-CTLFireability-14 686040 m, 43110 m/sec, 5029590 t fired, .
Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 20/201 4/32 Echo-PT-d03r05-CTLFireability-14 901574 m, 43106 m/sec, 6725666 t fired, .
Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 25/201 5/32 Echo-PT-d03r05-CTLFireability-14 1113799 m, 42445 m/sec, 8442589 t fired, .
Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 30/201 6/32 Echo-PT-d03r05-CTLFireability-14 1334330 m, 44106 m/sec, 10154728 t fired, .
Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 35/201 7/32 Echo-PT-d03r05-CTLFireability-14 1537748 m, 40683 m/sec, 11877628 t fired, .
Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 40/201 8/32 Echo-PT-d03r05-CTLFireability-14 1734205 m, 39291 m/sec, 13602717 t fired, .
Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 45/201 9/32 Echo-PT-d03r05-CTLFireability-14 1926105 m, 38380 m/sec, 15330928 t fired, .
Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 50/201 10/32 Echo-PT-d03r05-CTLFireability-14 2123358 m, 39450 m/sec, 17062152 t fired, .
Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 55/201 11/32 Echo-PT-d03r05-CTLFireability-14 2330934 m, 41515 m/sec, 18780217 t fired, .
Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 60/201 12/32 Echo-PT-d03r05-CTLFireability-14 2542705 m, 42354 m/sec, 20495313 t fired, .
Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 65/201 13/32 Echo-PT-d03r05-CTLFireability-14 2736016 m, 38662 m/sec, 22221741 t fired, .
Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 70/201 13/32 Echo-PT-d03r05-CTLFireability-14 2931247 m, 39046 m/sec, 23940587 t fired, .
Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 75/201 14/32 Echo-PT-d03r05-CTLFireability-14 3126055 m, 38961 m/sec, 25654652 t fired, .
Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 80/201 15/32 Echo-PT-d03r05-CTLFireability-14 3318293 m, 38447 m/sec, 27387050 t fired, .
Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 85/201 16/32 Echo-PT-d03r05-CTLFireability-14 3533833 m, 43108 m/sec, 29088973 t fired, .
Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 90/201 17/32 Echo-PT-d03r05-CTLFireability-14 3731000 m, 39433 m/sec, 30800071 t fired, .
Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 95/201 18/32 Echo-PT-d03r05-CTLFireability-14 3925247 m, 38849 m/sec, 32505568 t fired, .
Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 100/201 19/32 Echo-PT-d03r05-CTLFireability-14 4120252 m, 39001 m/sec, 34221281 t fired, .
Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 106/201 20/32 Echo-PT-d03r05-CTLFireability-14 4318129 m, 39575 m/sec, 35940748 t fired, .
Time elapsed: 283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 111/201 20/32 Echo-PT-d03r05-CTLFireability-14 4502309 m, 36836 m/sec, 37669510 t fired, .
Time elapsed: 288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 116/201 21/32 Echo-PT-d03r05-CTLFireability-14 4680232 m, 35584 m/sec, 39399152 t fired, .
Time elapsed: 293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 121/201 22/32 Echo-PT-d03r05-CTLFireability-14 4856509 m, 35255 m/sec, 41126985 t fired, .
Time elapsed: 298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 126/201 23/32 Echo-PT-d03r05-CTLFireability-14 5035188 m, 35735 m/sec, 42859029 t fired, .
Time elapsed: 303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 131/201 24/32 Echo-PT-d03r05-CTLFireability-14 5228067 m, 38575 m/sec, 44574887 t fired, .
Time elapsed: 308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 136/201 24/32 Echo-PT-d03r05-CTLFireability-14 5405617 m, 35510 m/sec, 46303804 t fired, .
Time elapsed: 313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 141/201 25/32 Echo-PT-d03r05-CTLFireability-14 5580760 m, 35028 m/sec, 48020126 t fired, .
Time elapsed: 318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 146/201 26/32 Echo-PT-d03r05-CTLFireability-14 5759402 m, 35728 m/sec, 49751993 t fired, .
Time elapsed: 323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 151/201 27/32 Echo-PT-d03r05-CTLFireability-14 5959190 m, 39957 m/sec, 51470600 t fired, .
Time elapsed: 328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 156/201 28/32 Echo-PT-d03r05-CTLFireability-14 6164616 m, 41085 m/sec, 53178951 t fired, .
Time elapsed: 333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 161/201 29/32 Echo-PT-d03r05-CTLFireability-14 6359914 m, 39059 m/sec, 54890512 t fired, .
Time elapsed: 338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 166/201 30/32 Echo-PT-d03r05-CTLFireability-14 6555998 m, 39216 m/sec, 56602410 t fired, .
Time elapsed: 343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 171/201 30/32 Echo-PT-d03r05-CTLFireability-14 6752043 m, 39209 m/sec, 58319609 t fired, .
Time elapsed: 348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 176/201 31/32 Echo-PT-d03r05-CTLFireability-14 6941365 m, 37864 m/sec, 60039316 t fired, .
Time elapsed: 353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 181/201 32/32 Echo-PT-d03r05-CTLFireability-14 7116411 m, 35009 m/sec, 61764561 t fired, .
Time elapsed: 358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 51 (type EXCL) for Echo-PT-d03r05-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-13: EXEF 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 47 Echo-PT-d03r05-CTLFireability-13
lola: time limit : 202 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for Echo-PT-d03r05-CTLFireability-13
lola: result : true
lola: markings : 13
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 Echo-PT-d03r05-CTLFireability-11
lola: time limit : 215 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/215 2/32 Echo-PT-d03r05-CTLFireability-11 318979 m, 63795 m/sec, 2156100 t fired, .
Time elapsed: 368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/215 3/32 Echo-PT-d03r05-CTLFireability-11 597286 m, 55661 m/sec, 4344021 t fired, .
Time elapsed: 373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/215 4/32 Echo-PT-d03r05-CTLFireability-11 875535 m, 55649 m/sec, 6531743 t fired, .
Time elapsed: 378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/215 6/32 Echo-PT-d03r05-CTLFireability-11 1153503 m, 55593 m/sec, 8715570 t fired, .
Time elapsed: 383 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/215 7/32 Echo-PT-d03r05-CTLFireability-11 1426458 m, 54591 m/sec, 10891370 t fired, .
Time elapsed: 388 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 30/215 8/32 Echo-PT-d03r05-CTLFireability-11 1670758 m, 48860 m/sec, 13086067 t fired, .
Time elapsed: 393 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 35/215 9/32 Echo-PT-d03r05-CTLFireability-11 1919838 m, 49816 m/sec, 15274844 t fired, .
Time elapsed: 398 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 40/215 10/32 Echo-PT-d03r05-CTLFireability-11 2167096 m, 49451 m/sec, 17469830 t fired, .
Time elapsed: 403 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 45/215 11/32 Echo-PT-d03r05-CTLFireability-11 2437467 m, 54074 m/sec, 19654891 t fired, .
Time elapsed: 408 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 50/215 12/32 Echo-PT-d03r05-CTLFireability-11 2695276 m, 51561 m/sec, 21845477 t fired, .
Time elapsed: 413 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 55/215 13/32 Echo-PT-d03r05-CTLFireability-11 2942615 m, 49467 m/sec, 24036077 t fired, .
Time elapsed: 418 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 60/215 15/32 Echo-PT-d03r05-CTLFireability-11 3190766 m, 49630 m/sec, 26232731 t fired, .
Time elapsed: 423 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 65/215 16/32 Echo-PT-d03r05-CTLFireability-11 3449445 m, 51735 m/sec, 28426252 t fired, .
Time elapsed: 428 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 70/215 17/32 Echo-PT-d03r05-CTLFireability-11 3708709 m, 51852 m/sec, 30609736 t fired, .
Time elapsed: 433 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 75/215 18/32 Echo-PT-d03r05-CTLFireability-11 3957820 m, 49822 m/sec, 32799470 t fired, .
Time elapsed: 438 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 80/215 19/32 Echo-PT-d03r05-CTLFireability-11 4210846 m, 50605 m/sec, 34992699 t fired, .
Time elapsed: 443 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 85/215 20/32 Echo-PT-d03r05-CTLFireability-11 4453654 m, 48561 m/sec, 37180713 t fired, .
Time elapsed: 448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 90/215 21/32 Echo-PT-d03r05-CTLFireability-11 4677921 m, 44853 m/sec, 39375840 t fired, .
Time elapsed: 453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 95/215 22/32 Echo-PT-d03r05-CTLFireability-11 4901480 m, 44711 m/sec, 41577389 t fired, .
Time elapsed: 458 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 100/215 23/32 Echo-PT-d03r05-CTLFireability-11 5139182 m, 47540 m/sec, 43767905 t fired, .
Time elapsed: 463 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 105/215 24/32 Echo-PT-d03r05-CTLFireability-11 5371019 m, 46367 m/sec, 45965406 t fired, .
Time elapsed: 468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 110/215 25/32 Echo-PT-d03r05-CTLFireability-11 5595596 m, 44915 m/sec, 48161728 t fired, .
Time elapsed: 473 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 115/215 26/32 Echo-PT-d03r05-CTLFireability-11 5821303 m, 45141 m/sec, 50370805 t fired, .
Time elapsed: 478 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 120/215 27/32 Echo-PT-d03r05-CTLFireability-11 6093916 m, 54522 m/sec, 52548558 t fired, .
Time elapsed: 483 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 125/215 29/32 Echo-PT-d03r05-CTLFireability-11 6343851 m, 49987 m/sec, 54737806 t fired, .
Time elapsed: 488 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 130/215 30/32 Echo-PT-d03r05-CTLFireability-11 6591933 m, 49616 m/sec, 56930114 t fired, .
Time elapsed: 493 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 135/215 31/32 Echo-PT-d03r05-CTLFireability-11 6839020 m, 49417 m/sec, 59113407 t fired, .
Time elapsed: 498 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 140/215 32/32 Echo-PT-d03r05-CTLFireability-11 7065960 m, 45388 m/sec, 61277136 t fired, .
Time elapsed: 503 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for Echo-PT-d03r05-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 508 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 38 Echo-PT-d03r05-CTLFireability-10
lola: time limit : 220 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/220 2/32 Echo-PT-d03r05-CTLFireability-10 321886 m, 64377 m/sec, 2176905 t fired, .
Time elapsed: 513 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/220 3/32 Echo-PT-d03r05-CTLFireability-10 601653 m, 55953 m/sec, 4373507 t fired, .
Time elapsed: 518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/220 4/32 Echo-PT-d03r05-CTLFireability-10 881570 m, 55983 m/sec, 6572488 t fired, .
Time elapsed: 523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/220 6/32 Echo-PT-d03r05-CTLFireability-10 1161917 m, 56069 m/sec, 8772640 t fired, .
Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 25/220 7/32 Echo-PT-d03r05-CTLFireability-10 1435963 m, 54809 m/sec, 10966568 t fired, .
Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 30/220 8/32 Echo-PT-d03r05-CTLFireability-10 1680590 m, 48925 m/sec, 13172126 t fired, .
Time elapsed: 538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 35/220 9/32 Echo-PT-d03r05-CTLFireability-10 1930839 m, 50049 m/sec, 15374227 t fired, .
Time elapsed: 543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 40/220 10/32 Echo-PT-d03r05-CTLFireability-10 2180113 m, 49854 m/sec, 17581422 t fired, .
Time elapsed: 548 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 45/220 11/32 Echo-PT-d03r05-CTLFireability-10 2453292 m, 54635 m/sec, 19774663 t fired, .
Time elapsed: 553 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 50/220 12/32 Echo-PT-d03r05-CTLFireability-10 2707856 m, 50912 m/sec, 21969464 t fired, .
Time elapsed: 558 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 55/220 14/32 Echo-PT-d03r05-CTLFireability-10 2957402 m, 49909 m/sec, 24168017 t fired, .
Time elapsed: 563 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 60/220 15/32 Echo-PT-d03r05-CTLFireability-10 3205644 m, 49648 m/sec, 26375170 t fired, .
Time elapsed: 568 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 65/220 16/32 Echo-PT-d03r05-CTLFireability-10 3468488 m, 52568 m/sec, 28567574 t fired, .
Time elapsed: 573 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 70/220 17/32 Echo-PT-d03r05-CTLFireability-10 3727059 m, 51714 m/sec, 30765261 t fired, .
Time elapsed: 578 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 75/220 18/32 Echo-PT-d03r05-CTLFireability-10 3975445 m, 49677 m/sec, 32954478 t fired, .
Time elapsed: 583 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 80/220 19/32 Echo-PT-d03r05-CTLFireability-10 4226296 m, 50170 m/sec, 35127538 t fired, .
Time elapsed: 588 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 85/220 20/32 Echo-PT-d03r05-CTLFireability-10 4465906 m, 47922 m/sec, 37302314 t fired, .
Time elapsed: 593 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 90/220 21/32 Echo-PT-d03r05-CTLFireability-10 4687792 m, 44377 m/sec, 39479564 t fired, .
Time elapsed: 598 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 95/220 22/32 Echo-PT-d03r05-CTLFireability-10 4912762 m, 44994 m/sec, 41687169 t fired, .
Time elapsed: 603 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 100/220 23/32 Echo-PT-d03r05-CTLFireability-10 5152158 m, 47879 m/sec, 43883373 t fired, .
Time elapsed: 608 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 105/220 24/32 Echo-PT-d03r05-CTLFireability-10 5383137 m, 46195 m/sec, 46085398 t fired, .
Time elapsed: 613 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 110/220 25/32 Echo-PT-d03r05-CTLFireability-10 5607724 m, 44917 m/sec, 48281278 t fired, .
Time elapsed: 618 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 115/220 26/32 Echo-PT-d03r05-CTLFireability-10 5832385 m, 44932 m/sec, 50486332 t fired, .
Time elapsed: 623 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 120/220 28/32 Echo-PT-d03r05-CTLFireability-10 6108211 m, 55165 m/sec, 52675691 t fired, .
Time elapsed: 628 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 125/220 29/32 Echo-PT-d03r05-CTLFireability-10 6358120 m, 49981 m/sec, 54873281 t fired, .
Time elapsed: 633 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 130/220 30/32 Echo-PT-d03r05-CTLFireability-10 6608695 m, 50115 m/sec, 57078413 t fired, .
Time elapsed: 638 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 135/220 31/32 Echo-PT-d03r05-CTLFireability-10 6857589 m, 49778 m/sec, 59271312 t fired, .
Time elapsed: 643 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 140/220 32/32 Echo-PT-d03r05-CTLFireability-10 7085367 m, 45555 m/sec, 61473311 t fired, .
Time elapsed: 648 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for Echo-PT-d03r05-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 653 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 36 (type EXCL) for 35 Echo-PT-d03r05-CTLFireability-09
lola: time limit : 226 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for Echo-PT-d03r05-CTLFireability-09
lola: result : false
lola: markings : 9268
lola: fired transitions : 9827
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 Echo-PT-d03r05-CTLFireability-08
lola: time limit : 245 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 5/245 2/32 Echo-PT-d03r05-CTLFireability-08 258018 m, 51603 m/sec, 2236247 t fired, .
Time elapsed: 658 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 10/245 3/32 Echo-PT-d03r05-CTLFireability-08 490978 m, 46592 m/sec, 4507423 t fired, .
Time elapsed: 663 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 15/245 4/32 Echo-PT-d03r05-CTLFireability-08 723804 m, 46565 m/sec, 6783153 t fired, .
Time elapsed: 668 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 20/245 5/32 Echo-PT-d03r05-CTLFireability-08 957017 m, 46642 m/sec, 9069632 t fired, .
Time elapsed: 673 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 25/245 6/32 Echo-PT-d03r05-CTLFireability-08 1187729 m, 46142 m/sec, 11348950 t fired, .
Time elapsed: 678 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 30/245 7/32 Echo-PT-d03r05-CTLFireability-08 1414144 m, 45283 m/sec, 13621546 t fired, .
Time elapsed: 683 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 35/245 8/32 Echo-PT-d03r05-CTLFireability-08 1624507 m, 42072 m/sec, 15904535 t fired, .
Time elapsed: 688 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 40/245 9/32 Echo-PT-d03r05-CTLFireability-08 1836152 m, 42329 m/sec, 18187180 t fired, .
Time elapsed: 693 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 45/245 10/32 Echo-PT-d03r05-CTLFireability-08 2047949 m, 42359 m/sec, 20471586 t fired, .
Time elapsed: 698 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 50/245 10/32 Echo-PT-d03r05-CTLFireability-08 2258821 m, 42174 m/sec, 22756920 t fired, .
Time elapsed: 703 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 55/245 11/32 Echo-PT-d03r05-CTLFireability-08 2489400 m, 46115 m/sec, 25039528 t fired, .
Time elapsed: 708 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 60/245 12/32 Echo-PT-d03r05-CTLFireability-08 2702521 m, 42624 m/sec, 27321523 t fired, .
Time elapsed: 713 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 65/245 13/32 Echo-PT-d03r05-CTLFireability-08 2913489 m, 42193 m/sec, 29600142 t fired, .
Time elapsed: 718 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 70/245 14/32 Echo-PT-d03r05-CTLFireability-08 3123770 m, 42056 m/sec, 31881564 t fired, .
Time elapsed: 723 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 75/245 15/32 Echo-PT-d03r05-CTLFireability-08 3330972 m, 41440 m/sec, 34174195 t fired, .
Time elapsed: 728 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 80/245 16/32 Echo-PT-d03r05-CTLFireability-08 3562777 m, 46361 m/sec, 36451858 t fired, .
Time elapsed: 733 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 85/245 17/32 Echo-PT-d03r05-CTLFireability-08 3775448 m, 42534 m/sec, 38739511 t fired, .
Time elapsed: 738 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 90/245 18/32 Echo-PT-d03r05-CTLFireability-08 3987487 m, 42407 m/sec, 41021703 t fired, .
Time elapsed: 743 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 95/245 19/32 Echo-PT-d03r05-CTLFireability-08 4199991 m, 42500 m/sec, 43307286 t fired, .
Time elapsed: 748 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 100/245 20/32 Echo-PT-d03r05-CTLFireability-08 4409694 m, 41940 m/sec, 45588670 t fired, .
Time elapsed: 753 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 105/245 21/32 Echo-PT-d03r05-CTLFireability-08 4602027 m, 38466 m/sec, 47870261 t fired, .
Time elapsed: 758 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 110/245 22/32 Echo-PT-d03r05-CTLFireability-08 4795215 m, 38637 m/sec, 50150815 t fired, .
Time elapsed: 763 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 115/245 23/32 Echo-PT-d03r05-CTLFireability-08 4990043 m, 38965 m/sec, 52435788 t fired, .
Time elapsed: 768 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 120/245 24/32 Echo-PT-d03r05-CTLFireability-08 5199921 m, 41975 m/sec, 54713504 t fired, .
Time elapsed: 773 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 125/245 24/32 Echo-PT-d03r05-CTLFireability-08 5395539 m, 39123 m/sec, 56996024 t fired, .
Time elapsed: 778 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 130/245 25/32 Echo-PT-d03r05-CTLFireability-08 5588826 m, 38657 m/sec, 59276761 t fired, .
Time elapsed: 783 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 135/245 26/32 Echo-PT-d03r05-CTLFireability-08 5783534 m, 38941 m/sec, 61566389 t fired, .
Time elapsed: 788 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 140/245 27/32 Echo-PT-d03r05-CTLFireability-08 6004045 m, 44102 m/sec, 63847408 t fired, .
Time elapsed: 793 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 145/245 28/32 Echo-PT-d03r05-CTLFireability-08 6221344 m, 43459 m/sec, 66129539 t fired, .
Time elapsed: 798 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 150/245 29/32 Echo-PT-d03r05-CTLFireability-08 6432801 m, 42291 m/sec, 68410241 t fired, .
Time elapsed: 803 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 155/245 30/32 Echo-PT-d03r05-CTLFireability-08 6645147 m, 42469 m/sec, 70700314 t fired, .
Time elapsed: 808 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 160/245 31/32 Echo-PT-d03r05-CTLFireability-08 6856900 m, 42350 m/sec, 72978883 t fired, .
Time elapsed: 813 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
33 CTL EXCL 165/245 32/32 Echo-PT-d03r05-CTLFireability-08 7052893 m, 39198 m/sec, 75255433 t fired, .
Time elapsed: 818 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 33 (type EXCL) for Echo-PT-d03r05-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-07: DISJ 0 2 0 0 3 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 823 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 30 (type EXCL) for 21 Echo-PT-d03r05-CTLFireability-07
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for Echo-PT-d03r05-CTLFireability-07
lola: result : false
lola: markings : 9276
lola: fired transitions : 18800
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 21 Echo-PT-d03r05-CTLFireability-07
lola: time limit : 277 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for Echo-PT-d03r05-CTLFireability-07
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 Echo-PT-d03r05-CTLFireability-05
lola: time limit : 308 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/308 2/32 Echo-PT-d03r05-CTLFireability-05 342402 m, 68480 m/sec, 2326387 t fired, .
Time elapsed: 828 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/308 3/32 Echo-PT-d03r05-CTLFireability-05 642835 m, 60086 m/sec, 4683616 t fired, .
Time elapsed: 833 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/308 5/32 Echo-PT-d03r05-CTLFireability-05 942292 m, 59891 m/sec, 7037947 t fired, .
Time elapsed: 838 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/308 6/32 Echo-PT-d03r05-CTLFireability-05 1240391 m, 59619 m/sec, 9383306 t fired, .
Time elapsed: 843 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/308 7/32 Echo-PT-d03r05-CTLFireability-05 1522082 m, 56338 m/sec, 11721716 t fired, .
Time elapsed: 848 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/308 8/32 Echo-PT-d03r05-CTLFireability-05 1785333 m, 52650 m/sec, 14047469 t fired, .
Time elapsed: 853 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/308 10/32 Echo-PT-d03r05-CTLFireability-05 2048417 m, 52616 m/sec, 16379973 t fired, .
Time elapsed: 858 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/308 11/32 Echo-PT-d03r05-CTLFireability-05 2322981 m, 54912 m/sec, 18716726 t fired, .
Time elapsed: 863 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 45/308 12/32 Echo-PT-d03r05-CTLFireability-05 2608825 m, 57168 m/sec, 21060397 t fired, .
Time elapsed: 868 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 50/308 13/32 Echo-PT-d03r05-CTLFireability-05 2873296 m, 52894 m/sec, 23404145 t fired, .
Time elapsed: 873 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 55/308 14/32 Echo-PT-d03r05-CTLFireability-05 3135777 m, 52496 m/sec, 25739572 t fired, .
Time elapsed: 878 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 60/308 16/32 Echo-PT-d03r05-CTLFireability-05 3407730 m, 54390 m/sec, 28082159 t fired, .
Time elapsed: 883 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 65/308 17/32 Echo-PT-d03r05-CTLFireability-05 3690210 m, 56496 m/sec, 30429390 t fired, .
Time elapsed: 888 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 70/308 18/32 Echo-PT-d03r05-CTLFireability-05 3953935 m, 52745 m/sec, 32761278 t fired, .
Time elapsed: 893 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 75/308 19/32 Echo-PT-d03r05-CTLFireability-05 4224524 m, 54117 m/sec, 35112358 t fired, .
Time elapsed: 898 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 80/308 20/32 Echo-PT-d03r05-CTLFireability-05 4481652 m, 51425 m/sec, 37464382 t fired, .
Time elapsed: 903 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 85/308 21/32 Echo-PT-d03r05-CTLFireability-05 4720764 m, 47822 m/sec, 39808348 t fired, .
Time elapsed: 908 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 90/308 22/32 Echo-PT-d03r05-CTLFireability-05 4959697 m, 47786 m/sec, 42163173 t fired, .
Time elapsed: 913 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 95/308 24/32 Echo-PT-d03r05-CTLFireability-05 5221012 m, 52263 m/sec, 44518056 t fired, .
Time elapsed: 918 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 100/308 25/32 Echo-PT-d03r05-CTLFireability-05 5465534 m, 48904 m/sec, 46869829 t fired, .
Time elapsed: 923 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 105/308 26/32 Echo-PT-d03r05-CTLFireability-05 5706350 m, 48163 m/sec, 49219993 t fired, .
Time elapsed: 928 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 110/308 27/32 Echo-PT-d03r05-CTLFireability-05 5972948 m, 53319 m/sec, 51578345 t fired, .
Time elapsed: 933 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 115/308 28/32 Echo-PT-d03r05-CTLFireability-05 6247667 m, 54943 m/sec, 53921358 t fired, .
Time elapsed: 938 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 120/308 29/32 Echo-PT-d03r05-CTLFireability-05 6516311 m, 53728 m/sec, 56259201 t fired, .
Time elapsed: 943 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 125/308 31/32 Echo-PT-d03r05-CTLFireability-05 6781554 m, 53048 m/sec, 58594949 t fired, .
Time elapsed: 948 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 130/308 32/32 Echo-PT-d03r05-CTLFireability-05 7032593 m, 50207 m/sec, 60943692 t fired, .
Time elapsed: 953 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for Echo-PT-d03r05-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 958 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 Echo-PT-d03r05-CTLFireability-04
lola: time limit : 330 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/330 2/32 Echo-PT-d03r05-CTLFireability-04 331051 m, 66210 m/sec, 2374748 t fired, .
Time elapsed: 963 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/330 3/32 Echo-PT-d03r05-CTLFireability-04 636238 m, 61037 m/sec, 4755880 t fired, .
Time elapsed: 968 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/330 5/32 Echo-PT-d03r05-CTLFireability-04 931792 m, 59110 m/sec, 7120030 t fired, .
Time elapsed: 973 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/330 6/32 Echo-PT-d03r05-CTLFireability-04 1195063 m, 52654 m/sec, 9466828 t fired, .
Time elapsed: 978 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/330 7/32 Echo-PT-d03r05-CTLFireability-04 1479757 m, 56938 m/sec, 11832279 t fired, .
Time elapsed: 983 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/330 8/32 Echo-PT-d03r05-CTLFireability-04 1757267 m, 55502 m/sec, 14205704 t fired, .
Time elapsed: 988 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/330 9/32 Echo-PT-d03r05-CTLFireability-04 2024819 m, 53510 m/sec, 16583107 t fired, .
Time elapsed: 993 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/330 11/32 Echo-PT-d03r05-CTLFireability-04 2310919 m, 57220 m/sec, 18946391 t fired, .
Time elapsed: 998 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/330 12/32 Echo-PT-d03r05-CTLFireability-04 2582743 m, 54364 m/sec, 21307413 t fired, .
Time elapsed: 1003 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/330 13/32 Echo-PT-d03r05-CTLFireability-04 2836781 m, 50807 m/sec, 23676846 t fired, .
Time elapsed: 1008 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/330 14/32 Echo-PT-d03r05-CTLFireability-04 3083066 m, 49257 m/sec, 26049499 t fired, .
Time elapsed: 1013 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/330 15/32 Echo-PT-d03r05-CTLFireability-04 3338314 m, 51049 m/sec, 28421064 t fired, .
Time elapsed: 1018 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/330 16/32 Echo-PT-d03r05-CTLFireability-04 3583813 m, 49099 m/sec, 30790269 t fired, .
Time elapsed: 1023 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/330 18/32 Echo-PT-d03r05-CTLFireability-04 3870711 m, 57379 m/sec, 33159885 t fired, .
Time elapsed: 1028 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/330 19/32 Echo-PT-d03r05-CTLFireability-04 4142020 m, 54261 m/sec, 35531387 t fired, .
Time elapsed: 1033 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 80/330 20/32 Echo-PT-d03r05-CTLFireability-04 4392444 m, 50084 m/sec, 37892451 t fired, .
Time elapsed: 1038 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 85/330 21/32 Echo-PT-d03r05-CTLFireability-04 4637709 m, 49053 m/sec, 40225039 t fired, .
Time elapsed: 1043 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 90/330 22/32 Echo-PT-d03r05-CTLFireability-04 4886875 m, 49833 m/sec, 42563729 t fired, .
Time elapsed: 1048 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 95/330 23/32 Echo-PT-d03r05-CTLFireability-04 5132842 m, 49193 m/sec, 44892435 t fired, .
Time elapsed: 1053 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 100/330 25/32 Echo-PT-d03r05-CTLFireability-04 5415230 m, 56477 m/sec, 47258949 t fired, .
Time elapsed: 1058 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 105/330 26/32 Echo-PT-d03r05-CTLFireability-04 5682563 m, 53466 m/sec, 49590118 t fired, .
Time elapsed: 1063 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 110/330 27/32 Echo-PT-d03r05-CTLFireability-04 5930492 m, 49585 m/sec, 51945913 t fired, .
Time elapsed: 1068 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 115/330 28/32 Echo-PT-d03r05-CTLFireability-04 6177249 m, 49351 m/sec, 54277946 t fired, .
Time elapsed: 1073 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 120/330 29/32 Echo-PT-d03r05-CTLFireability-04 6423459 m, 49242 m/sec, 56594725 t fired, .
Time elapsed: 1078 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 125/330 30/32 Echo-PT-d03r05-CTLFireability-04 6671308 m, 49569 m/sec, 58911212 t fired, .
Time elapsed: 1083 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 130/330 31/32 Echo-PT-d03r05-CTLFireability-04 6954159 m, 56570 m/sec, 61219559 t fired, .
Time elapsed: 1088 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for Echo-PT-d03r05-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1093 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 Echo-PT-d03r05-CTLFireability-03
lola: time limit : 358 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/358 2/32 Echo-PT-d03r05-CTLFireability-03 339687 m, 67937 m/sec, 2305238 t fired, .
Time elapsed: 1098 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/358 3/32 Echo-PT-d03r05-CTLFireability-03 633123 m, 58687 m/sec, 4615123 t fired, .
Time elapsed: 1103 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/358 5/32 Echo-PT-d03r05-CTLFireability-03 929927 m, 59360 m/sec, 6939620 t fired, .
Time elapsed: 1108 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/358 6/32 Echo-PT-d03r05-CTLFireability-03 1225974 m, 59209 m/sec, 9264573 t fired, .
Time elapsed: 1113 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/358 7/32 Echo-PT-d03r05-CTLFireability-03 1509693 m, 56743 m/sec, 11603718 t fired, .
Time elapsed: 1118 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/358 8/32 Echo-PT-d03r05-CTLFireability-03 1773732 m, 52807 m/sec, 13944873 t fired, .
Time elapsed: 1123 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/358 9/32 Echo-PT-d03r05-CTLFireability-03 2036234 m, 52500 m/sec, 16270797 t fired, .
Time elapsed: 1128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/358 11/32 Echo-PT-d03r05-CTLFireability-03 2312321 m, 55217 m/sec, 18633188 t fired, .
Time elapsed: 1133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/358 12/32 Echo-PT-d03r05-CTLFireability-03 2602160 m, 57967 m/sec, 21000492 t fired, .
Time elapsed: 1138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 50/358 13/32 Echo-PT-d03r05-CTLFireability-03 2864048 m, 52377 m/sec, 23325908 t fired, .
Time elapsed: 1143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 55/358 14/32 Echo-PT-d03r05-CTLFireability-03 3126006 m, 52391 m/sec, 25654223 t fired, .
Time elapsed: 1148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 60/358 16/32 Echo-PT-d03r05-CTLFireability-03 3396265 m, 54051 m/sec, 28001338 t fired, .
Time elapsed: 1153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 65/358 17/32 Echo-PT-d03r05-CTLFireability-03 3680072 m, 56761 m/sec, 30339583 t fired, .
Time elapsed: 1158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 70/358 18/32 Echo-PT-d03r05-CTLFireability-03 3946348 m, 53255 m/sec, 32691298 t fired, .
Time elapsed: 1163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 75/358 19/32 Echo-PT-d03r05-CTLFireability-03 4216622 m, 54054 m/sec, 35042858 t fired, .
Time elapsed: 1168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 80/358 20/32 Echo-PT-d03r05-CTLFireability-03 4474624 m, 51600 m/sec, 37388282 t fired, .
Time elapsed: 1173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 85/358 21/32 Echo-PT-d03r05-CTLFireability-03 4713405 m, 47756 m/sec, 39735026 t fired, .
Time elapsed: 1178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 90/358 22/32 Echo-PT-d03r05-CTLFireability-03 4952155 m, 47750 m/sec, 42084662 t fired, .
Time elapsed: 1183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 95/358 24/32 Echo-PT-d03r05-CTLFireability-03 5212335 m, 52036 m/sec, 44432613 t fired, .
Time elapsed: 1188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 100/358 25/32 Echo-PT-d03r05-CTLFireability-03 5453943 m, 48321 m/sec, 46765670 t fired, .
Time elapsed: 1193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 105/358 26/32 Echo-PT-d03r05-CTLFireability-03 5692257 m, 47662 m/sec, 49085223 t fired, .
Time elapsed: 1198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 110/358 27/32 Echo-PT-d03r05-CTLFireability-03 5955454 m, 52639 m/sec, 51444272 t fired, .
Time elapsed: 1203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 115/358 28/32 Echo-PT-d03r05-CTLFireability-03 6234091 m, 55727 m/sec, 53800095 t fired, .
Time elapsed: 1208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 120/358 29/32 Echo-PT-d03r05-CTLFireability-03 6504218 m, 54025 m/sec, 56153613 t fired, .
Time elapsed: 1213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 125/358 31/32 Echo-PT-d03r05-CTLFireability-03 6772869 m, 53730 m/sec, 58509392 t fired, .
Time elapsed: 1218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 130/358 32/32 Echo-PT-d03r05-CTLFireability-03 7021203 m, 49666 m/sec, 60825996 t fired, .
Time elapsed: 1223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for Echo-PT-d03r05-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 Echo-PT-d03r05-CTLFireability-01
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for Echo-PT-d03r05-CTLFireability-01
lola: result : false
lola: markings : 706
lola: fired transitions : 753
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Echo-PT-d03r05-CTLFireability-00
lola: time limit : 474 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/474 2/32 Echo-PT-d03r05-CTLFireability-00 347295 m, 69459 m/sec, 2365293 t fired, .
Time elapsed: 1233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/474 3/32 Echo-PT-d03r05-CTLFireability-00 651419 m, 60824 m/sec, 4749031 t fired, .
Time elapsed: 1238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/474 5/32 Echo-PT-d03r05-CTLFireability-00 953723 m, 60460 m/sec, 7128698 t fired, .
Time elapsed: 1243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/474 6/32 Echo-PT-d03r05-CTLFireability-00 1253112 m, 59877 m/sec, 9497037 t fired, .
Time elapsed: 1248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/474 7/32 Echo-PT-d03r05-CTLFireability-00 1534898 m, 56357 m/sec, 11848769 t fired, .
Time elapsed: 1253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/474 8/32 Echo-PT-d03r05-CTLFireability-00 1802998 m, 53620 m/sec, 14217512 t fired, .
Time elapsed: 1258 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/474 10/32 Echo-PT-d03r05-CTLFireability-00 2070985 m, 53597 m/sec, 16583946 t fired, .
Time elapsed: 1263 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/474 11/32 Echo-PT-d03r05-CTLFireability-00 2352644 m, 56331 m/sec, 18956353 t fired, .
Time elapsed: 1268 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/474 12/32 Echo-PT-d03r05-CTLFireability-00 2637173 m, 56905 m/sec, 21323391 t fired, .
Time elapsed: 1273 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/474 13/32 Echo-PT-d03r05-CTLFireability-00 2904241 m, 53413 m/sec, 23681469 t fired, .
Time elapsed: 1278 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/474 15/32 Echo-PT-d03r05-CTLFireability-00 3172077 m, 53567 m/sec, 26053983 t fired, .
Time elapsed: 1283 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/474 16/32 Echo-PT-d03r05-CTLFireability-00 3449909 m, 55566 m/sec, 28429074 t fired, .
Time elapsed: 1288 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/474 17/32 Echo-PT-d03r05-CTLFireability-00 3731064 m, 56231 m/sec, 30800626 t fired, .
Time elapsed: 1293 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/474 18/32 Echo-PT-d03r05-CTLFireability-00 4002810 m, 54349 m/sec, 33167563 t fired, .
Time elapsed: 1298 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 75/474 19/32 Echo-PT-d03r05-CTLFireability-00 4272707 m, 53979 m/sec, 35537354 t fired, .
Time elapsed: 1303 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 80/474 21/32 Echo-PT-d03r05-CTLFireability-00 4525978 m, 50654 m/sec, 37903392 t fired, .
Time elapsed: 1308 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 85/474 22/32 Echo-PT-d03r05-CTLFireability-00 4766440 m, 48092 m/sec, 40267145 t fired, .
Time elapsed: 1313 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 90/474 23/32 Echo-PT-d03r05-CTLFireability-00 5005677 m, 47847 m/sec, 42623399 t fired, .
Time elapsed: 1318 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 95/474 24/32 Echo-PT-d03r05-CTLFireability-00 5272957 m, 53456 m/sec, 44987329 t fired, .
Time elapsed: 1323 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 100/474 25/32 Echo-PT-d03r05-CTLFireability-00 5515756 m, 48559 m/sec, 47357163 t fired, .
Time elapsed: 1328 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 105/474 26/32 Echo-PT-d03r05-CTLFireability-00 5756888 m, 48226 m/sec, 49727638 t fired, .
Time elapsed: 1333 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 110/474 27/32 Echo-PT-d03r05-CTLFireability-00 6038754 m, 56373 m/sec, 52103488 t fired, .
Time elapsed: 1338 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 115/474 28/32 Echo-PT-d03r05-CTLFireability-00 6312707 m, 54790 m/sec, 54470996 t fired, .
Time elapsed: 1343 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 120/474 30/32 Echo-PT-d03r05-CTLFireability-00 6582249 m, 53908 m/sec, 56845306 t fired, .
Time elapsed: 1348 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 125/474 31/32 Echo-PT-d03r05-CTLFireability-00 6850565 m, 53663 m/sec, 59209581 t fired, .
Time elapsed: 1353 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 130/474 32/32 Echo-PT-d03r05-CTLFireability-00 7095383 m, 48963 m/sec, 61582328 t fired, .
Time elapsed: 1358 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for Echo-PT-d03r05-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-12: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1363 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 45 (type EXCL) for 44 Echo-PT-d03r05-CTLFireability-12
lola: time limit : 559 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for Echo-PT-d03r05-CTLFireability-12
lola: result : true
lola: markings : 250
lola: fired transitions : 249
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 6 Echo-PT-d03r05-CTLFireability-02
lola: time limit : 745 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 5/745 4/32 Echo-PT-d03r05-CTLFireability-02 551879 m, 110375 m/sec, 1204158 t fired, .
Time elapsed: 1368 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 10/745 8/32 Echo-PT-d03r05-CTLFireability-02 1069605 m, 103545 m/sec, 2406181 t fired, .
Time elapsed: 1373 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 15/745 11/32 Echo-PT-d03r05-CTLFireability-02 1565123 m, 99103 m/sec, 3586609 t fired, .
Time elapsed: 1378 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 20/745 15/32 Echo-PT-d03r05-CTLFireability-02 2084692 m, 103913 m/sec, 4826278 t fired, .
Time elapsed: 1383 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 25/745 17/32 Echo-PT-d03r05-CTLFireability-02 2359111 m, 54883 m/sec, 6079187 t fired, .
Time elapsed: 1388 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 30/745 23/32 Echo-PT-d03r05-CTLFireability-02 3156551 m, 159488 m/sec, 7146743 t fired, .
Time elapsed: 1393 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 1 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 LTL EXCL 35/745 29/32 Echo-PT-d03r05-CTLFireability-02 3970353 m, 162760 m/sec, 8298884 t fired, .
Time elapsed: 1398 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 56 (type EXCL) for Echo-PT-d03r05-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1403 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 Echo-PT-d03r05-CTLFireability-06
lola: time limit : 1098 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for Echo-PT-d03r05-CTLFireability-06
lola: result : true
lola: markings : 250
lola: fired transitions : 499
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 Echo-PT-d03r05-CTLFireability-15
lola: time limit : 2197 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/2197 2/32 Echo-PT-d03r05-CTLFireability-15 279831 m, 55966 m/sec, 2446259 t fired, .
Time elapsed: 1408 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/2197 3/32 Echo-PT-d03r05-CTLFireability-15 530070 m, 50047 m/sec, 4890561 t fired, .
Time elapsed: 1413 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 15/2197 4/32 Echo-PT-d03r05-CTLFireability-15 775461 m, 49078 m/sec, 7316400 t fired, .
Time elapsed: 1418 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 20/2197 5/32 Echo-PT-d03r05-CTLFireability-15 1024787 m, 49865 m/sec, 9755313 t fired, .
Time elapsed: 1423 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 25/2197 6/32 Echo-PT-d03r05-CTLFireability-15 1270906 m, 49223 m/sec, 12176233 t fired, .
Time elapsed: 1428 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 30/2197 7/32 Echo-PT-d03r05-CTLFireability-15 1506668 m, 47152 m/sec, 14589374 t fired, .
Time elapsed: 1433 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 35/2197 8/32 Echo-PT-d03r05-CTLFireability-15 1728664 m, 44399 m/sec, 17010548 t fired, .
Time elapsed: 1438 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 40/2197 9/32 Echo-PT-d03r05-CTLFireability-15 1947238 m, 43714 m/sec, 19432003 t fired, .
Time elapsed: 1443 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 45/2197 10/32 Echo-PT-d03r05-CTLFireability-15 2172056 m, 44963 m/sec, 21854551 t fired, .
Time elapsed: 1448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 50/2197 11/32 Echo-PT-d03r05-CTLFireability-15 2414674 m, 48523 m/sec, 24284458 t fired, .
Time elapsed: 1453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 55/2197 12/32 Echo-PT-d03r05-CTLFireability-15 2646678 m, 46400 m/sec, 26710949 t fired, .
Time elapsed: 1458 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 60/2197 13/32 Echo-PT-d03r05-CTLFireability-15 2871638 m, 44992 m/sec, 29132331 t fired, .
Time elapsed: 1463 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 65/2197 14/32 Echo-PT-d03r05-CTLFireability-15 3091811 m, 44034 m/sec, 31551547 t fired, .
Time elapsed: 1468 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 70/2197 15/32 Echo-PT-d03r05-CTLFireability-15 3314226 m, 44483 m/sec, 33978400 t fired, .
Time elapsed: 1473 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 75/2197 16/32 Echo-PT-d03r05-CTLFireability-15 3555143 m, 48183 m/sec, 36383301 t fired, .
Time elapsed: 1478 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 80/2197 17/32 Echo-PT-d03r05-CTLFireability-15 3782640 m, 45499 m/sec, 38810986 t fired, .
Time elapsed: 1483 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 85/2197 18/32 Echo-PT-d03r05-CTLFireability-15 4010021 m, 45476 m/sec, 41250575 t fired, .
Time elapsed: 1488 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 90/2197 19/32 Echo-PT-d03r05-CTLFireability-15 4235691 m, 45134 m/sec, 43676129 t fired, .
Time elapsed: 1493 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 95/2197 20/32 Echo-PT-d03r05-CTLFireability-15 4454165 m, 43694 m/sec, 46094109 t fired, .
Time elapsed: 1498 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 100/2197 21/32 Echo-PT-d03r05-CTLFireability-15 4658875 m, 40942 m/sec, 48506345 t fired, .
Time elapsed: 1503 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 105/2197 22/32 Echo-PT-d03r05-CTLFireability-15 4864022 m, 41029 m/sec, 50923176 t fired, .
Time elapsed: 1508 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 110/2197 23/32 Echo-PT-d03r05-CTLFireability-15 5074436 m, 42082 m/sec, 53335043 t fired, .
Time elapsed: 1513 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 115/2197 24/32 Echo-PT-d03r05-CTLFireability-15 5292224 m, 43557 m/sec, 55752819 t fired, .
Time elapsed: 1518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 120/2197 25/32 Echo-PT-d03r05-CTLFireability-15 5496660 m, 40887 m/sec, 58161812 t fired, .
Time elapsed: 1523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 125/2197 26/32 Echo-PT-d03r05-CTLFireability-15 5701023 m, 40872 m/sec, 60569814 t fired, .
Time elapsed: 1528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 130/2197 27/32 Echo-PT-d03r05-CTLFireability-15 5918306 m, 43456 m/sec, 62976589 t fired, .
Time elapsed: 1533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 135/2197 28/32 Echo-PT-d03r05-CTLFireability-15 6153497 m, 47038 m/sec, 65385649 t fired, .
Time elapsed: 1538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 140/2197 29/32 Echo-PT-d03r05-CTLFireability-15 6378022 m, 44905 m/sec, 67806232 t fired, .
Time elapsed: 1543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 145/2197 30/32 Echo-PT-d03r05-CTLFireability-15 6601162 m, 44628 m/sec, 70213824 t fired, .
Time elapsed: 1548 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 150/2197 31/32 Echo-PT-d03r05-CTLFireability-15 6824734 m, 44714 m/sec, 72626050 t fired, .
Time elapsed: 1553 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 155/2197 32/32 Echo-PT-d03r05-CTLFireability-15 7034649 m, 41983 m/sec, 75034736 t fired, .
Time elapsed: 1558 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for Echo-PT-d03r05-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1563 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-00: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-02: SP ACTL unknown AGGR
Echo-PT-d03r05-CTLFireability-03: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-04: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-05: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-08: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-10: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-11: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
Echo-PT-d03r05-CTLFireability-14: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-15: CTL unknown AGGR
Time elapsed: 1563 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d03r05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Echo-PT-d03r05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851200090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d03r05.tgz
mv Echo-PT-d03r05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;