fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r166-tall-167838851200090
Last Updated
May 14, 2023

About the Execution of LoLA for Echo-PT-d03r05

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
6058.756 1563350.00 1563832.00 3643.40 ?F????TF?F??TT?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851200090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Echo-PT-d03r05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851200090
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.6K Feb 25 14:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 25 14:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 14:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 14:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 14:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 14:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 716K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d03r05-CTLFireability-00
FORMULA_NAME Echo-PT-d03r05-CTLFireability-01
FORMULA_NAME Echo-PT-d03r05-CTLFireability-02
FORMULA_NAME Echo-PT-d03r05-CTLFireability-03
FORMULA_NAME Echo-PT-d03r05-CTLFireability-04
FORMULA_NAME Echo-PT-d03r05-CTLFireability-05
FORMULA_NAME Echo-PT-d03r05-CTLFireability-06
FORMULA_NAME Echo-PT-d03r05-CTLFireability-07
FORMULA_NAME Echo-PT-d03r05-CTLFireability-08
FORMULA_NAME Echo-PT-d03r05-CTLFireability-09
FORMULA_NAME Echo-PT-d03r05-CTLFireability-10
FORMULA_NAME Echo-PT-d03r05-CTLFireability-11
FORMULA_NAME Echo-PT-d03r05-CTLFireability-12
FORMULA_NAME Echo-PT-d03r05-CTLFireability-13
FORMULA_NAME Echo-PT-d03r05-CTLFireability-14
FORMULA_NAME Echo-PT-d03r05-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678414695779

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d03r05
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT Echo-PT-d03r05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA Echo-PT-d03r05-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r05-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r05-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r05-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r05-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r05-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678416259129

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
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lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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28 CTL EXCL 3/199 1/32 Echo-PT-d03r05-CTLFireability-07 182254 m, 36450 m/sec, 1366853 t fired, .

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28 CTL EXCL 8/199 2/32 Echo-PT-d03r05-CTLFireability-07 427494 m, 49048 m/sec, 3442032 t fired, .

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28 CTL EXCL 13/199 3/32 Echo-PT-d03r05-CTLFireability-07 666067 m, 47714 m/sec, 5531077 t fired, .

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28 CTL EXCL 18/199 4/32 Echo-PT-d03r05-CTLFireability-07 900498 m, 46886 m/sec, 7617541 t fired, .

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28 CTL EXCL 23/199 6/32 Echo-PT-d03r05-CTLFireability-07 1133155 m, 46531 m/sec, 9707353 t fired, .

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28 CTL EXCL 28/199 7/32 Echo-PT-d03r05-CTLFireability-07 1367727 m, 46914 m/sec, 11779536 t fired, .

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28 CTL EXCL 33/199 7/32 Echo-PT-d03r05-CTLFireability-07 1583659 m, 43186 m/sec, 13861806 t fired, .

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28 CTL EXCL 38/199 8/32 Echo-PT-d03r05-CTLFireability-07 1795728 m, 42413 m/sec, 15940547 t fired, .

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28 CTL EXCL 43/199 9/32 Echo-PT-d03r05-CTLFireability-07 2005654 m, 41985 m/sec, 18014811 t fired, .

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51 CTL EXCL 10/201 3/32 Echo-PT-d03r05-CTLFireability-14 470487 m, 44419 m/sec, 3344596 t fired, .

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51 CTL EXCL 15/201 4/32 Echo-PT-d03r05-CTLFireability-14 686040 m, 43110 m/sec, 5029590 t fired, .

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51 CTL EXCL 20/201 4/32 Echo-PT-d03r05-CTLFireability-14 901574 m, 43106 m/sec, 6725666 t fired, .

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51 CTL EXCL 25/201 5/32 Echo-PT-d03r05-CTLFireability-14 1113799 m, 42445 m/sec, 8442589 t fired, .

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51 CTL EXCL 30/201 6/32 Echo-PT-d03r05-CTLFireability-14 1334330 m, 44106 m/sec, 10154728 t fired, .

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51 CTL EXCL 35/201 7/32 Echo-PT-d03r05-CTLFireability-14 1537748 m, 40683 m/sec, 11877628 t fired, .

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51 CTL EXCL 40/201 8/32 Echo-PT-d03r05-CTLFireability-14 1734205 m, 39291 m/sec, 13602717 t fired, .

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51 CTL EXCL 45/201 9/32 Echo-PT-d03r05-CTLFireability-14 1926105 m, 38380 m/sec, 15330928 t fired, .

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51 CTL EXCL 50/201 10/32 Echo-PT-d03r05-CTLFireability-14 2123358 m, 39450 m/sec, 17062152 t fired, .

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51 CTL EXCL 55/201 11/32 Echo-PT-d03r05-CTLFireability-14 2330934 m, 41515 m/sec, 18780217 t fired, .

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51 CTL EXCL 60/201 12/32 Echo-PT-d03r05-CTLFireability-14 2542705 m, 42354 m/sec, 20495313 t fired, .

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51 CTL EXCL 65/201 13/32 Echo-PT-d03r05-CTLFireability-14 2736016 m, 38662 m/sec, 22221741 t fired, .

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51 CTL EXCL 70/201 13/32 Echo-PT-d03r05-CTLFireability-14 2931247 m, 39046 m/sec, 23940587 t fired, .

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51 CTL EXCL 75/201 14/32 Echo-PT-d03r05-CTLFireability-14 3126055 m, 38961 m/sec, 25654652 t fired, .

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51 CTL EXCL 80/201 15/32 Echo-PT-d03r05-CTLFireability-14 3318293 m, 38447 m/sec, 27387050 t fired, .

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51 CTL EXCL 85/201 16/32 Echo-PT-d03r05-CTLFireability-14 3533833 m, 43108 m/sec, 29088973 t fired, .

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51 CTL EXCL 90/201 17/32 Echo-PT-d03r05-CTLFireability-14 3731000 m, 39433 m/sec, 30800071 t fired, .

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51 CTL EXCL 95/201 18/32 Echo-PT-d03r05-CTLFireability-14 3925247 m, 38849 m/sec, 32505568 t fired, .

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51 CTL EXCL 100/201 19/32 Echo-PT-d03r05-CTLFireability-14 4120252 m, 39001 m/sec, 34221281 t fired, .

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51 CTL EXCL 106/201 20/32 Echo-PT-d03r05-CTLFireability-14 4318129 m, 39575 m/sec, 35940748 t fired, .

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51 CTL EXCL 111/201 20/32 Echo-PT-d03r05-CTLFireability-14 4502309 m, 36836 m/sec, 37669510 t fired, .

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51 CTL EXCL 116/201 21/32 Echo-PT-d03r05-CTLFireability-14 4680232 m, 35584 m/sec, 39399152 t fired, .

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51 CTL EXCL 121/201 22/32 Echo-PT-d03r05-CTLFireability-14 4856509 m, 35255 m/sec, 41126985 t fired, .

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51 CTL EXCL 126/201 23/32 Echo-PT-d03r05-CTLFireability-14 5035188 m, 35735 m/sec, 42859029 t fired, .

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54 CTL EXCL 15/2197 4/32 Echo-PT-d03r05-CTLFireability-15 775461 m, 49078 m/sec, 7316400 t fired, .

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54 CTL EXCL 25/2197 6/32 Echo-PT-d03r05-CTLFireability-15 1270906 m, 49223 m/sec, 12176233 t fired, .

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54 CTL EXCL 30/2197 7/32 Echo-PT-d03r05-CTLFireability-15 1506668 m, 47152 m/sec, 14589374 t fired, .

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54 CTL EXCL 35/2197 8/32 Echo-PT-d03r05-CTLFireability-15 1728664 m, 44399 m/sec, 17010548 t fired, .

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Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 135/2197 28/32 Echo-PT-d03r05-CTLFireability-15 6153497 m, 47038 m/sec, 65385649 t fired, .

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Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 140/2197 29/32 Echo-PT-d03r05-CTLFireability-15 6378022 m, 44905 m/sec, 67806232 t fired, .

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Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 145/2197 30/32 Echo-PT-d03r05-CTLFireability-15 6601162 m, 44628 m/sec, 70213824 t fired, .

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Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 150/2197 31/32 Echo-PT-d03r05-CTLFireability-15 6824734 m, 44714 m/sec, 72626050 t fired, .

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Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 155/2197 32/32 Echo-PT-d03r05-CTLFireability-15 7034649 m, 41983 m/sec, 75034736 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r05-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-02: SP ACTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r05-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r05-CTLFireability-00: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-02: SP ACTL unknown AGGR
Echo-PT-d03r05-CTLFireability-03: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-04: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-05: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r05-CTLFireability-07: DISJ false DISJ
Echo-PT-d03r05-CTLFireability-08: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-09: CTL false CTL model checker
Echo-PT-d03r05-CTLFireability-10: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-11: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-12: EFEG true state space /EFEG
Echo-PT-d03r05-CTLFireability-13: EXEF true state space /EXEF
Echo-PT-d03r05-CTLFireability-14: CTL unknown AGGR
Echo-PT-d03r05-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d03r05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Echo-PT-d03r05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851200090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d03r05.tgz
mv Echo-PT-d03r05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;