About the Execution of ITS-Tools for FamilyReunion-COL-L00800M0080C040P040G020
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 2332420.00 | 0.00 | 0.00 | FF?F???F???FF?F? | normal |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r165-tall-167838850300346.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool itstools
Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r165-tall-167838850300346
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 652K
-rw-r--r-- 1 mcc users 7.0K Feb 26 11:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 11:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 11:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 11:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 11:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 185K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679471279159
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=itstools
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00800M0080C040P040G020
Not applying reductions.
Model is COL
CTLFireability COL
Running Version 202303021504
[2023-03-22 07:48:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -its, -ltsmin, -greatspnpath, /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/, -order, META, -manyOrder, -smt, -timeout, 3600]
[2023-03-22 07:48:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 07:48:00] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-22 07:48:01] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-22 07:48:01] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 558 ms
[2023-03-22 07:48:01] [INFO ] Detected 5 constant HL places corresponding to 206 PT places.
[2023-03-22 07:48:01] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 2076109 PT places and 1977710.0 transition bindings in 56 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-22 07:48:01] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 6 ms.
[2023-03-22 07:48:01] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Initial state reduction rules removed 5 formulas.
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 6 formulas.
Remains 10 properties that can be checked using skeleton over-approximation.
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10428 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=548 ) properties (out of 21) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 19) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 17) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Running SMT prover for 16 properties.
// Phase 1: matrix 66 rows 99 cols
[2023-03-22 07:48:01] [INFO ] Computed 33 place invariants in 17 ms
[2023-03-22 07:48:04] [INFO ] [Real]Absence check using 4 positive place invariants in 9 ms returned sat
[2023-03-22 07:48:04] [INFO ] [Real]Absence check using 4 positive and 29 generalized place invariants in 7 ms returned sat
[2023-03-22 07:48:04] [INFO ] After 275ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2 real:14
[2023-03-22 07:48:05] [INFO ] After 292ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-22 07:48:05] [INFO ] After 3213ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-22 07:48:05] [INFO ] [Nat]Absence check using 4 positive place invariants in 4 ms returned sat
[2023-03-22 07:48:05] [INFO ] [Nat]Absence check using 4 positive and 29 generalized place invariants in 7 ms returned sat
[2023-03-22 07:48:05] [INFO ] After 91ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16
[2023-03-22 07:48:05] [INFO ] After 199ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16
Attempting to minimize the solution found.
Minimization took 79 ms.
[2023-03-22 07:48:05] [INFO ] After 398ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16
Finished Parikh walk after 179 steps, including 0 resets, run visited all 4 properties in 4 ms. (steps per millisecond=44 )
Parikh walk visited 16 properties in 38 ms.
[2023-03-22 07:48:05] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-22 07:48:05] [INFO ] Flatten gal took : 26 ms
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-22 07:48:05] [INFO ] Flatten gal took : 7 ms
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 41
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 21
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
[2023-03-22 07:48:09] [INFO ] Unfolded HLPN to a Petri net with 1835549 places and 1592429 transitions 4577797 arcs in 4401 ms.
[2023-03-22 07:48:09] [INFO ] Unfolded 9 HLPN properties in 59 ms.
Deduced a syphon composed of 801 places in 4856 ms
Reduce places removed 927 places and 0 transitions.
Support contains 962043 out of 1834622 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1834622/1834622 places, 1592429/1592429 transitions.
Reduce places removed 2569 places and 0 transitions.
Discarding 197046 places :
Implicit places reduction removed 197046 places
Iterating post reduction 0 with 199615 rules applied. Total rules applied 199615 place count 1635007 transition count 1592429
Applied a total of 199615 rules in 2019616 ms. Remains 1635007 /1834622 variables (removed 199615) and now considering 1592429/1592429 (removed 0) transitions.
// Phase 1: matrix 1592429 rows 1635007 cols
[2023-03-22 08:24:11] [WARNING] Invariant computation timed out after 120 seconds.
BK_STOP 1679473611579
--------------------
content from stderr:
+ export BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
+ BINDIR=/home/mcc/BenchKit/bin//../itstools/bin//../
++ pwd
+ export MODEL=/home/mcc/execution
+ MODEL=/home/mcc/execution
+ [[ CTLFireability = StateSpace ]]
+ /home/mcc/BenchKit/bin//../itstools/bin//..//runeclipse.sh /home/mcc/execution CTLFireability -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../itstools/bin//..//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -its -ltsmin -greatspnpath /home/mcc/BenchKit/bin//../itstools/bin//..//greatspn/ -order META -manyOrder -smt -timeout 3600
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00800M0080C040P040G020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="itstools"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool itstools"
echo " Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r165-tall-167838850300346"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00800M0080C040P040G020.tgz
mv FamilyReunion-COL-L00800M0080C040P040G020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;