About the Execution of LoLa+red for DoubleLock-PT-p3s2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2417.279 | 304275.00 | 597516.00 | 1002.10 | F?T??FTFFFTFFFF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414700554.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p3s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414700554
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 748K
-rw-r--r-- 1 mcc users 6.0K Feb 25 14:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 25 14:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 14:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 14:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Feb 25 14:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 25 14:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 25 14:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 14:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 330K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678407936254
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p3s2
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 00:25:39] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 00:25:39] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 00:25:39] [INFO ] Load time of PNML (sax parser for PT used): 181 ms
[2023-03-10 00:25:39] [INFO ] Transformed 112 places.
[2023-03-10 00:25:39] [INFO ] Transformed 744 transitions.
[2023-03-10 00:25:39] [INFO ] Parsed PT model containing 112 places and 744 transitions and 3008 arcs in 345 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Deduced a syphon composed of 20 places in 4 ms
Reduce places removed 20 places and 32 transitions.
Support contains 72 out of 92 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 92/92 places, 712/712 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 89 transition count 712
Applied a total of 3 rules in 29 ms. Remains 89 /92 variables (removed 3) and now considering 712/712 (removed 0) transitions.
[2023-03-10 00:25:40] [INFO ] Flow matrix only has 515 transitions (discarded 197 similar events)
// Phase 1: matrix 515 rows 89 cols
[2023-03-10 00:25:40] [INFO ] Computed 2 place invariants in 28 ms
[2023-03-10 00:25:40] [INFO ] Implicit Places using invariants in 259 ms returned []
[2023-03-10 00:25:40] [INFO ] Flow matrix only has 515 transitions (discarded 197 similar events)
[2023-03-10 00:25:40] [INFO ] Invariant cache hit.
[2023-03-10 00:25:40] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:25:40] [INFO ] Implicit Places using invariants and state equation in 459 ms returned []
Implicit Place search using SMT with State Equation took 757 ms to find 0 implicit places.
[2023-03-10 00:25:40] [INFO ] Flow matrix only has 515 transitions (discarded 197 similar events)
[2023-03-10 00:25:40] [INFO ] Invariant cache hit.
[2023-03-10 00:25:41] [INFO ] Dead Transitions using invariants and state equation in 746 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 89/92 places, 712/712 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1560 ms. Remains : 89/92 places, 712/712 transitions.
Support contains 72 out of 89 places after structural reductions.
[2023-03-10 00:25:42] [INFO ] Flatten gal took : 178 ms
[2023-03-10 00:25:42] [INFO ] Flatten gal took : 108 ms
[2023-03-10 00:25:42] [INFO ] Input system was already deterministic with 712 transitions.
Incomplete random walk after 10006 steps, including 118 resets, run finished after 724 ms. (steps per millisecond=13 ) properties (out of 79) seen :34
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 45) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 45) seen :1
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 44) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 44) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 4 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 43) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 42) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 41) seen :0
Running SMT prover for 41 properties.
[2023-03-10 00:25:43] [INFO ] Flow matrix only has 515 transitions (discarded 197 similar events)
[2023-03-10 00:25:43] [INFO ] Invariant cache hit.
[2023-03-10 00:25:44] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:25:44] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-10 00:25:44] [INFO ] After 365ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:41
[2023-03-10 00:25:44] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:25:44] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:25:46] [INFO ] After 1214ms SMT Verify possible using state equation in natural domain returned unsat :23 sat :18
[2023-03-10 00:25:46] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:25:47] [INFO ] After 1033ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :23 sat :18
[2023-03-10 00:25:48] [INFO ] After 2372ms SMT Verify possible using trap constraints in natural domain returned unsat :23 sat :18
Attempting to minimize the solution found.
Minimization took 1028 ms.
[2023-03-10 00:25:49] [INFO ] After 5121ms SMT Verify possible using all constraints in natural domain returned unsat :23 sat :18
Fused 41 Parikh solutions to 18 different solutions.
Parikh walk visited 0 properties in 277 ms.
Support contains 27 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 712/712 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 89 transition count 710
Applied a total of 2 rules in 69 ms. Remains 89 /89 variables (removed 0) and now considering 710/712 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 70 ms. Remains : 89/89 places, 710/712 transitions.
Incomplete random walk after 10001 steps, including 123 resets, run finished after 230 ms. (steps per millisecond=43 ) properties (out of 18) seen :4
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 86 ms. (steps per millisecond=116 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 73 ms. (steps per millisecond=137 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 22 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 25 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 14) seen :3
Running SMT prover for 11 properties.
[2023-03-10 00:25:50] [INFO ] Flow matrix only has 513 transitions (discarded 197 similar events)
// Phase 1: matrix 513 rows 89 cols
[2023-03-10 00:25:50] [INFO ] Computed 2 place invariants in 9 ms
[2023-03-10 00:25:50] [INFO ] [Real]Absence check using 1 positive place invariants in 4 ms returned sat
[2023-03-10 00:25:50] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:25:51] [INFO ] After 471ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:11
[2023-03-10 00:25:51] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:25:51] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:25:52] [INFO ] After 546ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :11
[2023-03-10 00:25:52] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:25:53] [INFO ] After 1000ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :0 sat :11
[2023-03-10 00:25:53] [INFO ] After 1915ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :11
Attempting to minimize the solution found.
Minimization took 677 ms.
[2023-03-10 00:25:54] [INFO ] After 3293ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :11
Parikh walk visited 0 properties in 125 ms.
Support contains 19 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 710/710 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 89 transition count 709
Applied a total of 1 rules in 41 ms. Remains 89 /89 variables (removed 0) and now considering 709/710 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 41 ms. Remains : 89/89 places, 709/710 transitions.
Incomplete random walk after 10003 steps, including 118 resets, run finished after 198 ms. (steps per millisecond=50 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10000 steps, including 22 resets, run finished after 73 ms. (steps per millisecond=136 ) properties (out of 11) seen :1
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 19 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 10) seen :1
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 23 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 22 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 9) seen :1
Running SMT prover for 8 properties.
[2023-03-10 00:25:55] [INFO ] Flow matrix only has 512 transitions (discarded 197 similar events)
// Phase 1: matrix 512 rows 89 cols
[2023-03-10 00:25:55] [INFO ] Computed 2 place invariants in 3 ms
[2023-03-10 00:25:55] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:25:55] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:25:56] [INFO ] After 446ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:8
[2023-03-10 00:25:56] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:25:56] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:25:56] [INFO ] After 474ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :8
[2023-03-10 00:25:56] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:25:57] [INFO ] After 841ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :0 sat :8
[2023-03-10 00:25:58] [INFO ] After 1428ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :8
Attempting to minimize the solution found.
Minimization took 509 ms.
[2023-03-10 00:25:58] [INFO ] After 2523ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :8
Parikh walk visited 0 properties in 100 ms.
Support contains 14 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 709/709 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 89 transition count 707
Applied a total of 2 rules in 39 ms. Remains 89 /89 variables (removed 0) and now considering 707/709 (removed 2) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 39 ms. Remains : 89/89 places, 707/709 transitions.
Incomplete random walk after 10001 steps, including 120 resets, run finished after 196 ms. (steps per millisecond=51 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 20 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 19 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 23 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10000 steps, including 25 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 8) seen :0
Interrupted probabilistic random walk after 215838 steps, run timeout after 3001 ms. (steps per millisecond=71 ) properties seen :{0=1, 2=1, 3=1, 5=1}
Probabilistic random walk after 215838 steps, saw 152802 distinct states, run finished after 3006 ms. (steps per millisecond=71 ) properties seen :4
Running SMT prover for 4 properties.
[2023-03-10 00:26:02] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
// Phase 1: matrix 510 rows 89 cols
[2023-03-10 00:26:02] [INFO ] Computed 2 place invariants in 10 ms
[2023-03-10 00:26:02] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:02] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:26:02] [INFO ] After 272ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-10 00:26:02] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:02] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-10 00:26:02] [INFO ] After 241ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-10 00:26:02] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:26:03] [INFO ] After 234ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :0 sat :4
[2023-03-10 00:26:03] [INFO ] After 410ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 141 ms.
[2023-03-10 00:26:03] [INFO ] After 853ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Parikh walk visited 0 properties in 41 ms.
Support contains 11 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 707/707 transitions.
Applied a total of 0 rules in 28 ms. Remains 89 /89 variables (removed 0) and now considering 707/707 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 29 ms. Remains : 89/89 places, 707/707 transitions.
Incomplete random walk after 10003 steps, including 120 resets, run finished after 176 ms. (steps per millisecond=56 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 23 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10000 steps, including 23 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 4) seen :1
Running SMT prover for 3 properties.
[2023-03-10 00:26:03] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
[2023-03-10 00:26:03] [INFO ] Invariant cache hit.
[2023-03-10 00:26:04] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:04] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-10 00:26:04] [INFO ] After 340ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 00:26:04] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:04] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 3 ms returned sat
[2023-03-10 00:26:04] [INFO ] After 290ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:04] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:26:04] [INFO ] After 130ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:04] [INFO ] After 264ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 88 ms.
[2023-03-10 00:26:05] [INFO ] After 722ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 25 ms.
Support contains 5 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 707/707 transitions.
Applied a total of 0 rules in 23 ms. Remains 89 /89 variables (removed 0) and now considering 707/707 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 24 ms. Remains : 89/89 places, 707/707 transitions.
Incomplete random walk after 10000 steps, including 118 resets, run finished after 95 ms. (steps per millisecond=105 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10000 steps, including 24 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 22 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 3) seen :0
Interrupted probabilistic random walk after 306177 steps, run timeout after 3001 ms. (steps per millisecond=102 ) properties seen :{}
Probabilistic random walk after 306177 steps, saw 214471 distinct states, run finished after 3002 ms. (steps per millisecond=101 ) properties seen :0
Running SMT prover for 3 properties.
[2023-03-10 00:26:08] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
[2023-03-10 00:26:08] [INFO ] Invariant cache hit.
[2023-03-10 00:26:08] [INFO ] [Real]Absence check using 1 positive place invariants in 2 ms returned sat
[2023-03-10 00:26:08] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:26:08] [INFO ] After 295ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 00:26:08] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:08] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:26:08] [INFO ] After 228ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:08] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:26:09] [INFO ] After 130ms SMT Verify possible using 47 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:09] [INFO ] After 259ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 88 ms.
[2023-03-10 00:26:09] [INFO ] After 641ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 46 ms.
Support contains 5 out of 89 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 707/707 transitions.
Applied a total of 0 rules in 24 ms. Remains 89 /89 variables (removed 0) and now considering 707/707 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 24 ms. Remains : 89/89 places, 707/707 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 89/89 places, 707/707 transitions.
Applied a total of 0 rules in 23 ms. Remains 89 /89 variables (removed 0) and now considering 707/707 (removed 0) transitions.
[2023-03-10 00:26:09] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
[2023-03-10 00:26:09] [INFO ] Invariant cache hit.
[2023-03-10 00:26:09] [INFO ] Implicit Places using invariants in 201 ms returned []
[2023-03-10 00:26:09] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
[2023-03-10 00:26:09] [INFO ] Invariant cache hit.
[2023-03-10 00:26:09] [INFO ] State equation strengthened by 47 read => feed constraints.
[2023-03-10 00:26:10] [INFO ] Implicit Places using invariants and state equation in 539 ms returned []
Implicit Place search using SMT with State Equation took 745 ms to find 0 implicit places.
[2023-03-10 00:26:10] [INFO ] Redundant transitions in 77 ms returned []
[2023-03-10 00:26:10] [INFO ] Flow matrix only has 510 transitions (discarded 197 similar events)
[2023-03-10 00:26:10] [INFO ] Invariant cache hit.
[2023-03-10 00:26:10] [INFO ] Dead Transitions using invariants and state equation in 693 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1550 ms. Remains : 89/89 places, 707/707 transitions.
Ensure Unique test removed 197 transitions
Reduce isomorphic transitions removed 197 transitions.
Iterating post reduction 0 with 197 rules applied. Total rules applied 197 place count 89 transition count 510
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 8 Pre rules applied. Total rules applied 197 place count 89 transition count 502
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 1 with 16 rules applied. Total rules applied 213 place count 81 transition count 502
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 1 with 4 rules applied. Total rules applied 217 place count 79 transition count 500
Free-agglomeration rule applied 1 times.
Iterating global reduction 1 with 1 rules applied. Total rules applied 218 place count 79 transition count 499
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 219 place count 78 transition count 499
Applied a total of 219 rules in 73 ms. Remains 78 /89 variables (removed 11) and now considering 499/707 (removed 208) transitions.
Running SMT prover for 3 properties.
// Phase 1: matrix 499 rows 78 cols
[2023-03-10 00:26:10] [INFO ] Computed 2 place invariants in 4 ms
[2023-03-10 00:26:11] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:11] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-10 00:26:11] [INFO ] After 261ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:2
[2023-03-10 00:26:11] [INFO ] State equation strengthened by 16 read => feed constraints.
[2023-03-10 00:26:11] [INFO ] After 32ms SMT Verify possible using 16 Read/Feed constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 00:26:11] [INFO ] After 374ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 00:26:11] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-10 00:26:11] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-10 00:26:11] [INFO ] After 252ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:11] [INFO ] After 84ms SMT Verify possible using 16 Read/Feed constraints in natural domain returned unsat :0 sat :3
[2023-03-10 00:26:11] [INFO ] After 203ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 80 ms.
[2023-03-10 00:26:11] [INFO ] After 603ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Successfully simplified 23 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA DoubleLock-PT-p3s2-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 00:26:12] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 74 ms
[2023-03-10 00:26:12] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
FORMULA DoubleLock-PT-p3s2-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DoubleLock-PT-p3s2-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DoubleLock-PT-p3s2-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DoubleLock-PT-p3s2-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 76 ms
[2023-03-10 00:26:12] [INFO ] Input system was already deterministic with 712 transitions.
Support contains 43 out of 89 places (down from 49) after GAL structural reductions.
Computed a total of 7 stabilizing places and 176 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 8 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 58 ms
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 63 ms
[2023-03-10 00:26:12] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 5 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 48 ms
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 49 ms
[2023-03-10 00:26:12] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 4 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 42 ms
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 35 ms
[2023-03-10 00:26:12] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 2 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 22 ms
[2023-03-10 00:26:12] [INFO ] Flatten gal took : 23 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 3 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 19 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 22 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 3 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 19 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 21 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 2 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 19 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 20 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 26 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 19 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 21 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 3 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 21 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 25 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 15 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 20 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 22 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
Starting structural reductions in LTL mode, iteration 0 : 89/89 places, 712/712 transitions.
Applied a total of 0 rules in 2 ms. Remains 89 /89 variables (removed 0) and now considering 712/712 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 89/89 places, 712/712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 19 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 20 ms
[2023-03-10 00:26:13] [INFO ] Input system was already deterministic with 712 transitions.
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 21 ms
[2023-03-10 00:26:13] [INFO ] Flatten gal took : 22 ms
[2023-03-10 00:26:13] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-10 00:26:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 89 places, 712 transitions and 2848 arcs took 4 ms.
Total runtime 34298 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p3s2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability
FORMULA DoubleLock-PT-p3s2-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s2-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678408240529
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 29 (type EXCL) for 26 DoubleLock-PT-p3s2-CTLFireability-09
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 54 (type FNDP) for 26 DoubleLock-PT-p3s2-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 26 DoubleLock-PT-p3s2-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 57 (type SRCH) for 26 DoubleLock-PT-p3s2-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 29 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-09
lola: result : false
lola: markings : 31
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 DoubleLock-PT-p3s2-CTLFireability-07
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 24 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-07
lola: result : false
lola: markings : 36
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 DoubleLock-PT-p3s2-CTLFireability-05
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-05
lola: result : false
lola: markings : 36
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DoubleLock-PT-p3s2-CTLFireability-02
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-02
lola: result : true
lola: markings : 32
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 26 DoubleLock-PT-p3s2-CTLFireability-09
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type SRCH) for DoubleLock-PT-p3s2-CTLFireability-09
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 54 (type FNDP) for DoubleLock-PT-p3s2-CTLFireability-09 (obsolete)
lola: CANCELED task # 55 (type EQUN) for DoubleLock-PT-p3s2-CTLFireability-09 (obsolete)
lola: CANCELED task # 56 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-09 (obsolete)
lola: LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p3s2-CTLFireability-01
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 54 (type FNDP) for DoubleLock-PT-p3s2-CTLFireability-09
lola: result : unknown
lola: fired transitions : 44
lola: tried executions : 3
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/371/CTLFireability-55.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/400 5/32 DoubleLock-PT-p3s2-CTLFireability-01 1127880 m, 225576 m/sec, 1218573 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
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DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/400 11/32 DoubleLock-PT-p3s2-CTLFireability-01 2421627 m, 258749 m/sec, 2616351 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
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DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
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1 CTL EXCL 15/400 17/32 DoubleLock-PT-p3s2-CTLFireability-01 3705320 m, 256738 m/sec, 4003270 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
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1 CTL EXCL 20/400 22/32 DoubleLock-PT-p3s2-CTLFireability-01 4980631 m, 255062 m/sec, 5381132 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
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1 CTL EXCL 25/400 28/32 DoubleLock-PT-p3s2-CTLFireability-01 6251901 m, 254254 m/sec, 6754629 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
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DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
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lola: LAUNCH task # 51 (type EXCL) for 50 DoubleLock-PT-p3s2-CTLFireability-15
lola: time limit : 446 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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51 CTL EXCL 5/446 7/32 DoubleLock-PT-p3s2-CTLFireability-15 1429506 m, 285901 m/sec, 1544455 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
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DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
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DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
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DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
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51 CTL EXCL 10/446 13/32 DoubleLock-PT-p3s2-CTLFireability-15 2881675 m, 290433 m/sec, 3113395 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
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51 CTL EXCL 15/446 19/32 DoubleLock-PT-p3s2-CTLFireability-15 4280836 m, 279832 m/sec, 4625068 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
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DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
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DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-13: F 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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lola: FINISHED task # 45 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-12
lola: result : false
lola: markings : 40
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
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lola: FINISHED task # 13 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-03
lola: result : false
lola: markings : 31
lola: fired transitions : 31
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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 AGEF EXCL 5/1120 8/32 DoubleLock-PT-p3s2-CTLFireability-04 1780360 m, 356072 m/sec, 1923520 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-13: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 1 0 0 4 0 1 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 AGEF EXCL 10/1120 14/32 DoubleLock-PT-p3s2-CTLFireability-04 3516072 m, 347142 m/sec, 3798804 t fired, .
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-13: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 1 0 0 4 0 1 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-13: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 1 0 0 4 0 1 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-13: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s2-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-03: CONJ 0 1 0 0 4 0 1 0
DoubleLock-PT-p3s2-CTLFireability-04: EFAG 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s2-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 42 (type EXCL) for 41 DoubleLock-PT-p3s2-CTLFireability-10
lola: time limit : 1667 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for DoubleLock-PT-p3s2-CTLFireability-10
lola: result : true
lola: markings : 32
lola: fired transitions : 128
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 DoubleLock-PT-p3s2-CTLFireability-03
lola: time limit : 3335 sec
lola: memory limit: 32 pages
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lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s2-CTLFireability-01: CTL unknown AGGR
DoubleLock-PT-p3s2-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-03: CONJ unknown CONJ
DoubleLock-PT-p3s2-CTLFireability-04: EFAG unknown AGGR
DoubleLock-PT-p3s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-07: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-09: DISJ false DISJ
DoubleLock-PT-p3s2-CTLFireability-10: CTL true CTL model checker
DoubleLock-PT-p3s2-CTLFireability-12: CTL false CTL model checker
DoubleLock-PT-p3s2-CTLFireability-13: F false state space / EG
DoubleLock-PT-p3s2-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p3s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p3s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414700554"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p3s2.tgz
mv DoubleLock-PT-p3s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;