About the Execution of LoLa+red for DoubleLock-PT-p2s1
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5512.808 | 325460.00 | 317048.00 | 1781.30 | ??F?FF??T?FF?T?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414600530.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p2s1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414600530
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 548K
-rw-r--r-- 1 mcc users 6.1K Feb 25 14:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 25 14:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 14:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 14:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 25 14:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 14:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 25 14:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 97K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p2s1-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678395322219
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p2s1
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 20:55:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 20:55:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 20:55:25] [INFO ] Load time of PNML (sax parser for PT used): 137 ms
[2023-03-09 20:55:25] [INFO ] Transformed 64 places.
[2023-03-09 20:55:25] [INFO ] Transformed 212 transitions.
[2023-03-09 20:55:25] [INFO ] Parsed PT model containing 64 places and 212 transitions and 860 arcs in 349 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 24 ms.
Deduced a syphon composed of 8 places in 4 ms
Reduce places removed 8 places and 8 transitions.
Support contains 48 out of 56 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 56/56 places, 204/204 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 52 transition count 204
Applied a total of 4 rules in 29 ms. Remains 52 /56 variables (removed 4) and now considering 204/204 (removed 0) transitions.
[2023-03-09 20:55:25] [INFO ] Flow matrix only has 152 transitions (discarded 52 similar events)
// Phase 1: matrix 152 rows 52 cols
[2023-03-09 20:55:25] [INFO ] Computed 2 place invariants in 29 ms
[2023-03-09 20:55:26] [INFO ] Implicit Places using invariants in 304 ms returned []
[2023-03-09 20:55:26] [INFO ] Flow matrix only has 152 transitions (discarded 52 similar events)
[2023-03-09 20:55:26] [INFO ] Invariant cache hit.
[2023-03-09 20:55:26] [INFO ] State equation strengthened by 27 read => feed constraints.
[2023-03-09 20:55:26] [INFO ] Implicit Places using invariants and state equation in 232 ms returned []
Implicit Place search using SMT with State Equation took 602 ms to find 0 implicit places.
[2023-03-09 20:55:26] [INFO ] Flow matrix only has 152 transitions (discarded 52 similar events)
[2023-03-09 20:55:26] [INFO ] Invariant cache hit.
[2023-03-09 20:55:26] [INFO ] Dead Transitions using invariants and state equation in 284 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 52/56 places, 204/204 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 947 ms. Remains : 52/56 places, 204/204 transitions.
Support contains 48 out of 52 places after structural reductions.
[2023-03-09 20:55:27] [INFO ] Flatten gal took : 93 ms
[2023-03-09 20:55:27] [INFO ] Flatten gal took : 42 ms
[2023-03-09 20:55:27] [INFO ] Input system was already deterministic with 204 transitions.
Incomplete random walk after 10002 steps, including 54 resets, run finished after 931 ms. (steps per millisecond=10 ) properties (out of 74) seen :67
Incomplete Best-First random walk after 10000 steps, including 8 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 13 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 98 ms. (steps per millisecond=102 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-09 20:55:28] [INFO ] Flow matrix only has 152 transitions (discarded 52 similar events)
[2023-03-09 20:55:28] [INFO ] Invariant cache hit.
[2023-03-09 20:55:29] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 20:55:29] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 2 ms returned sat
[2023-03-09 20:55:29] [INFO ] After 112ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-09 20:55:29] [INFO ] [Nat]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 20:55:29] [INFO ] [Nat]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 20:55:29] [INFO ] After 231ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :0
Fused 7 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 7 atomic propositions for a total of 16 simplifications.
FORMULA DoubleLock-PT-p2s1-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 31 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 27 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 204 transitions.
Support contains 46 out of 52 places (down from 47) after GAL structural reductions.
Computed a total of 4 stabilizing places and 24 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 47 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 47 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 19 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 23 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Applied a total of 2 rules in 7 ms. Remains 51 /52 variables (removed 1) and now considering 200/204 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 51/52 places, 200/204 transitions.
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 19 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 22 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 26 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 26 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 18 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 20 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 25 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 15 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 18 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 12 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 14 ms
[2023-03-09 20:55:29] [INFO ] Flatten gal took : 15 ms
[2023-03-09 20:55:29] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 17 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 10 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 10 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Applied a total of 4 rules in 6 ms. Remains 50 /52 variables (removed 2) and now considering 196/204 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 50/52 places, 196/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 16 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 11 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 18 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 10 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Finished random walk after 705 steps, including 5 resets, run visited all 1 properties in 2 ms. (steps per millisecond=352 )
FORMULA DoubleLock-PT-p2s1-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Applied a total of 0 rules in 1 ms. Remains 52 /52 variables (removed 0) and now considering 204/204 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 52/52 places, 204/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 10 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 204 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 6 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Applied a total of 2 rules in 10 ms. Remains 51 /52 variables (removed 1) and now considering 200/204 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 51/52 places, 200/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 8 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 200 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 13 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 7 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 8 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 11 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 6 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 7 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 10 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 7 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 15 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 204/204 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 200
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 200
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 196
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 196
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 192
Applied a total of 6 rules in 5 ms. Remains 49 /52 variables (removed 3) and now considering 192/204 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 49/52 places, 192/204 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 7 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 8 ms
[2023-03-09 20:55:30] [INFO ] Input system was already deterministic with 192 transitions.
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Flatten gal took : 9 ms
[2023-03-09 20:55:30] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-09 20:55:30] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 52 places, 204 transitions and 812 arcs took 1 ms.
Total runtime 5457 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p2s1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/365
CTLFireability
FORMULA DoubleLock-PT-p2s1-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678395647679
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ sed s/.jar//
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/365/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/365/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/365/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 DoubleLock-PT-p2s1-CTLFireability-01
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type FNDP) for 9 DoubleLock-PT-p2s1-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 9 DoubleLock-PT-p2s1-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type SRCH) for 9 DoubleLock-PT-p2s1-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 59 (type SRCH) for DoubleLock-PT-p2s1-CTLFireability-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 55 (type FNDP) for DoubleLock-PT-p2s1-CTLFireability-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for DoubleLock-PT-p2s1-CTLFireability-03 (obsolete)
sara: try reading problem file /home/mcc/execution/365/CTLFireability-56.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 56 (type EQUN) for DoubleLock-PT-p2s1-CTLFireability-03
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s1-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-03: CONJ 0 1 0 0 5 0 0 1
DoubleLock-PT-p2s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-11: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p2s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-13: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/224 3/32 DoubleLock-PT-p2s1-CTLFireability-01 523708 m, 104741 m/sec, 1629301 t fired, .
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DoubleLock-PT-p2s1-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-03: CONJ 0 1 0 0 5 0 0 1
DoubleLock-PT-p2s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-11: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p2s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-13: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/224 5/32 DoubleLock-PT-p2s1-CTLFireability-01 1073949 m, 110048 m/sec, 3341171 t fired, .
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DoubleLock-PT-p2s1-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-03: CONJ 0 1 0 0 5 0 0 1
DoubleLock-PT-p2s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-11: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p2s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-13: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/224 7/32 DoubleLock-PT-p2s1-CTLFireability-01 1612761 m, 107762 m/sec, 5017473 t fired, .
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DoubleLock-PT-p2s1-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-03: CONJ 0 1 0 0 5 0 0 1
DoubleLock-PT-p2s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-11: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p2s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-13: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/224 10/32 DoubleLock-PT-p2s1-CTLFireability-01 2158609 m, 109169 m/sec, 6715644 t fired, .
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DoubleLock-PT-p2s1-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-03: CONJ 0 1 0 0 5 0 0 1
DoubleLock-PT-p2s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s1-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s1-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s1-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 7 (type EXCL) for 6 DoubleLock-PT-p2s1-CTLFireability-02
lola: time limit : 3284 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for DoubleLock-PT-p2s1-CTLFireability-02
lola: result : false
lola: markings : 27
lola: fired transitions : 55
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s1-CTLFireability-00: EFAG unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-01: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p2s1-CTLFireability-03: CONJ unknown CONJ
DoubleLock-PT-p2s1-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p2s1-CTLFireability-06: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-07: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-09: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-10: CTL false CTL model checker
DoubleLock-PT-p2s1-CTLFireability-11: CONJ false CTL model checker
DoubleLock-PT-p2s1-CTLFireability-12: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-13: EG true state space / EG
DoubleLock-PT-p2s1-CTLFireability-14: CTL unknown AGGR
DoubleLock-PT-p2s1-CTLFireability-15: CTL false CTL model checker
Time elapsed: 316 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p2s1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p2s1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414600530"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p2s1.tgz
mv DoubleLock-PT-p2s1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;