About the Execution of LoLa+red for DoubleLock-PT-p1s1
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5603.979 | 275614.00 | 543959.00 | 1546.60 | TTT?FT??F?TFT?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414600506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleLock-PT-p1s1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414600506
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 5.5K Feb 25 14:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 14:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 14:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 14:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 14:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 113K Feb 25 14:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 14:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Feb 25 14:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 93K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678378435145
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p1s1
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 16:13:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 16:13:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 16:13:59] [INFO ] Load time of PNML (sax parser for PT used): 132 ms
[2023-03-09 16:13:59] [INFO ] Transformed 64 places.
[2023-03-09 16:13:59] [INFO ] Transformed 204 transitions.
[2023-03-09 16:13:59] [INFO ] Parsed PT model containing 64 places and 204 transitions and 828 arcs in 289 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Deduced a syphon composed of 8 places in 3 ms
Reduce places removed 8 places and 8 transitions.
FORMULA DoubleLock-PT-p1s1-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 45 out of 56 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 56/56 places, 196/196 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 52 transition count 196
Applied a total of 4 rules in 29 ms. Remains 52 /56 variables (removed 4) and now considering 196/196 (removed 0) transitions.
[2023-03-09 16:13:59] [INFO ] Flow matrix only has 148 transitions (discarded 48 similar events)
// Phase 1: matrix 148 rows 52 cols
[2023-03-09 16:13:59] [INFO ] Computed 2 place invariants in 25 ms
[2023-03-09 16:13:59] [INFO ] Implicit Places using invariants in 245 ms returned []
[2023-03-09 16:13:59] [INFO ] Flow matrix only has 148 transitions (discarded 48 similar events)
[2023-03-09 16:13:59] [INFO ] Invariant cache hit.
[2023-03-09 16:13:59] [INFO ] State equation strengthened by 23 read => feed constraints.
[2023-03-09 16:13:59] [INFO ] Implicit Places using invariants and state equation in 148 ms returned []
Implicit Place search using SMT with State Equation took 431 ms to find 0 implicit places.
[2023-03-09 16:13:59] [INFO ] Flow matrix only has 148 transitions (discarded 48 similar events)
[2023-03-09 16:13:59] [INFO ] Invariant cache hit.
[2023-03-09 16:14:00] [INFO ] Dead Transitions using invariants and state equation in 306 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 52/56 places, 196/196 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 768 ms. Remains : 52/56 places, 196/196 transitions.
Support contains 45 out of 52 places after structural reductions.
[2023-03-09 16:14:00] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 16:14:00] [INFO ] Flatten gal took : 89 ms
FORMULA DoubleLock-PT-p1s1-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 16:14:00] [INFO ] Flatten gal took : 39 ms
[2023-03-09 16:14:00] [INFO ] Input system was already deterministic with 196 transitions.
Incomplete random walk after 10000 steps, including 75 resets, run finished after 740 ms. (steps per millisecond=13 ) properties (out of 61) seen :54
Incomplete Best-First random walk after 10001 steps, including 14 resets, run finished after 114 ms. (steps per millisecond=87 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 218 ms. (steps per millisecond=45 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 111 ms. (steps per millisecond=90 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 99 ms. (steps per millisecond=101 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 21 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 13 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-09 16:14:02] [INFO ] Flow matrix only has 148 transitions (discarded 48 similar events)
[2023-03-09 16:14:02] [INFO ] Invariant cache hit.
[2023-03-09 16:14:02] [INFO ] [Real]Absence check using 1 positive place invariants in 1 ms returned sat
[2023-03-09 16:14:02] [INFO ] [Real]Absence check using 1 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 16:14:02] [INFO ] After 278ms SMT Verify possible using all constraints in real domain returned unsat :7 sat :0
Fused 7 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 7 atomic propositions for a total of 14 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA DoubleLock-PT-p1s1-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 16:14:02] [INFO ] Flatten gal took : 26 ms
[2023-03-09 16:14:02] [INFO ] Flatten gal took : 26 ms
[2023-03-09 16:14:02] [INFO ] Input system was already deterministic with 196 transitions.
Computed a total of 4 stabilizing places and 24 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 48 transition count 176
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 48 transition count 176
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 9 place count 47 transition count 168
Iterating global reduction 0 with 1 rules applied. Total rules applied 10 place count 47 transition count 168
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 11 place count 46 transition count 164
Iterating global reduction 0 with 1 rules applied. Total rules applied 12 place count 46 transition count 164
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 13 place count 45 transition count 160
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 45 transition count 160
Applied a total of 14 rules in 42 ms. Remains 45 /52 variables (removed 7) and now considering 160/196 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 45/52 places, 160/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 19 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 36 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 48 transition count 176
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 48 transition count 176
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 9 place count 47 transition count 168
Iterating global reduction 0 with 1 rules applied. Total rules applied 10 place count 47 transition count 168
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 11 place count 46 transition count 164
Iterating global reduction 0 with 1 rules applied. Total rules applied 12 place count 46 transition count 164
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 13 place count 45 transition count 160
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 45 transition count 160
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 15 place count 44 transition count 156
Iterating global reduction 0 with 1 rules applied. Total rules applied 16 place count 44 transition count 156
Applied a total of 16 rules in 35 ms. Remains 44 /52 variables (removed 8) and now considering 156/196 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 44/52 places, 156/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 18 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 21 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 156 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Applied a total of 0 rules in 3 ms. Remains 52 /52 variables (removed 0) and now considering 196/196 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 52/52 places, 196/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 21 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 24 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 196 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 48 transition count 176
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 48 transition count 176
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 9 place count 47 transition count 168
Iterating global reduction 0 with 1 rules applied. Total rules applied 10 place count 47 transition count 168
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 11 place count 46 transition count 164
Iterating global reduction 0 with 1 rules applied. Total rules applied 12 place count 46 transition count 164
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 13 place count 45 transition count 160
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 45 transition count 160
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 15 place count 44 transition count 156
Iterating global reduction 0 with 1 rules applied. Total rules applied 16 place count 44 transition count 156
Applied a total of 16 rules in 59 ms. Remains 44 /52 variables (removed 8) and now considering 156/196 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 60 ms. Remains : 44/52 places, 156/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 14 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 156 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 7 place count 48 transition count 176
Iterating global reduction 0 with 1 rules applied. Total rules applied 8 place count 48 transition count 176
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 9 place count 47 transition count 168
Iterating global reduction 0 with 1 rules applied. Total rules applied 10 place count 47 transition count 168
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 11 place count 46 transition count 164
Iterating global reduction 0 with 1 rules applied. Total rules applied 12 place count 46 transition count 164
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 13 place count 45 transition count 160
Iterating global reduction 0 with 1 rules applied. Total rules applied 14 place count 45 transition count 160
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 15 place count 44 transition count 156
Iterating global reduction 0 with 1 rules applied. Total rules applied 16 place count 44 transition count 156
Applied a total of 16 rules in 45 ms. Remains 44 /52 variables (removed 8) and now considering 156/196 (removed 40) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 45 ms. Remains : 44/52 places, 156/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 12 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 156 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Applied a total of 6 rules in 22 ms. Remains 49 /52 variables (removed 3) and now considering 184/196 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 49/52 places, 184/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 14 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 15 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Applied a total of 4 rules in 4 ms. Remains 50 /52 variables (removed 2) and now considering 188/196 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 50/52 places, 188/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Applied a total of 2 rules in 4 ms. Remains 51 /52 variables (removed 1) and now considering 192/196 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 51/52 places, 192/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 12 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Applied a total of 4 rules in 16 ms. Remains 50 /52 variables (removed 2) and now considering 188/196 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 50/52 places, 188/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 20 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 188 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Applied a total of 6 rules in 6 ms. Remains 49 /52 variables (removed 3) and now considering 184/196 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 49/52 places, 184/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 12 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 13 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Applied a total of 2 rules in 2 ms. Remains 51 /52 variables (removed 1) and now considering 192/196 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 51/52 places, 192/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 8 ms
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 8 ms
[2023-03-09 16:14:03] [INFO ] Input system was already deterministic with 192 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 3 place count 50 transition count 188
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 50 transition count 188
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 5 place count 49 transition count 184
Iterating global reduction 0 with 1 rules applied. Total rules applied 6 place count 49 transition count 184
Applied a total of 6 rules in 5 ms. Remains 49 /52 variables (removed 3) and now considering 184/196 (removed 12) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 49/52 places, 184/196 transitions.
[2023-03-09 16:14:03] [INFO ] Flatten gal took : 7 ms
[2023-03-09 16:14:04] [INFO ] Flatten gal took : 20 ms
[2023-03-09 16:14:04] [INFO ] Input system was already deterministic with 184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 52/52 places, 196/196 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 51 transition count 192
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 51 transition count 192
Applied a total of 2 rules in 3 ms. Remains 51 /52 variables (removed 1) and now considering 192/196 (removed 4) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 51/52 places, 192/196 transitions.
[2023-03-09 16:14:04] [INFO ] Flatten gal took : 8 ms
[2023-03-09 16:14:04] [INFO ] Flatten gal took : 8 ms
[2023-03-09 16:14:04] [INFO ] Input system was already deterministic with 192 transitions.
[2023-03-09 16:14:04] [INFO ] Flatten gal took : 9 ms
[2023-03-09 16:14:04] [INFO ] Flatten gal took : 8 ms
[2023-03-09 16:14:04] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-09 16:14:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 52 places, 196 transitions and 780 arcs took 1 ms.
Total runtime 5144 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleLock-PT-p1s1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DoubleLock-PT-p1s1-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678378710759
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 28 (type EXCL) for 25 DoubleLock-PT-p1s1-CTLFireability-10
lola: time limit : 109 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 28 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-10
lola: result : true
lola: markings : 26
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 60 (type EXCL) for 57 DoubleLock-PT-p1s1-CTLFireability-14
lola: time limit : 120 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 71 (type FNDP) for 32 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type EQUN) for 32 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type SRCH) for 32 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 71 (type FNDP) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : true
lola: fired transitions : 119
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: CANCELED task # 72 (type EQUN) for DoubleLock-PT-p1s1-CTLFireability-11 (obsolete)
lola: CANCELED task # 74 (type SRCH) for DoubleLock-PT-p1s1-CTLFireability-11 (obsolete)
lola: FINISHED task # 74 (type SRCH) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : true
lola: markings : 29
lola: fired transitions : 28
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/375/CTLFireability-72.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: sara: place or transition ordering is non-deterministic
rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 5/211 6/32 DoubleLock-PT-p1s1-CTLFireability-14 1385685 m, 277137 m/sec, 1590967 t fired, .
Time elapsed: 5 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 10/211 13/32 DoubleLock-PT-p1s1-CTLFireability-14 2884291 m, 299721 m/sec, 3311588 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 15/211 19/32 DoubleLock-PT-p1s1-CTLFireability-14 4357519 m, 294645 m/sec, 5003072 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 20/211 25/32 DoubleLock-PT-p1s1-CTLFireability-14 5790519 m, 286600 m/sec, 6648369 t fired, .
Time elapsed: 20 secs. Pages in use: 25
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
60 CTL EXCL 25/211 30/32 DoubleLock-PT-p1s1-CTLFireability-14 7161008 m, 274097 m/sec, 8221893 t fired, .
Time elapsed: 25 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 60 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 32
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lola: LAUNCH task # 69 (type EXCL) for 68 DoubleLock-PT-p1s1-CTLFireability-15
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: FINISHED task # 69 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-15
lola: result : true
lola: markings : 27
lola: fired transitions : 57
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 DoubleLock-PT-p1s1-CTLFireability-13
lola: time limit : 238 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/3365 29/32 DoubleLock-PT-p1s1-CTLFireability-07 6806871 m, 257928 m/sec, 14622163 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-11: DISJ false DISJ
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
DoubleLock-PT-p1s1-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-03: CTL unknown AGGR
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-06: DISJ unknown DISJ
DoubleLock-PT-p1s1-CTLFireability-07: CTL unknown AGGR
DoubleLock-PT-p1s1-CTLFireability-09: CTL unknown AGGR
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-11: DISJ false DISJ
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-13: CTL unknown AGGR
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
DoubleLock-PT-p1s1-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleLock-PT-p1s1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414600506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s1.tgz
mv DoubleLock-PT-p1s1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;