fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r135-smll-167819414500474
Last Updated
May 14, 2023

About the Execution of LoLa+red for DoubleExponent-PT-010

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16217.695 3600000.00 10491314.00 22740.60 ?T?TFTFTTFT?T??T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r135-smll-167819414500474.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DoubleExponent-PT-010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819414500474
=====================================================================


--------------------
preparation of the directory to be used:
/home/mcc/execution
total 604K
-rw-r--r-- 1 mcc users 7.2K Feb 26 13:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 26 13:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 26 13:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 26 13:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.2K Feb 26 13:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 13:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 26 13:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Feb 26 13:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 169K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-00
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-01
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-02
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-03
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-04
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-05
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-06
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-07
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-08
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-09
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-10
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-11
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-12
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-13
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-14
FORMULA_NAME DoubleExponent-PT-010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678340754790

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleExponent-PT-010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 05:45:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 05:45:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 05:45:58] [INFO ] Load time of PNML (sax parser for PT used): 242 ms
[2023-03-09 05:45:58] [INFO ] Transformed 534 places.
[2023-03-09 05:45:58] [INFO ] Transformed 498 transitions.
[2023-03-09 05:45:58] [INFO ] Parsed PT model containing 534 places and 498 transitions and 1404 arcs in 373 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 13 ms.
Support contains 125 out of 534 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 534/534 places, 498/498 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 530 transition count 498
Applied a total of 4 rules in 93 ms. Remains 530 /534 variables (removed 4) and now considering 498/498 (removed 0) transitions.
// Phase 1: matrix 498 rows 530 cols
[2023-03-09 05:45:58] [INFO ] Computed 51 place invariants in 121 ms
[2023-03-09 05:45:59] [INFO ] Implicit Places using invariants in 880 ms returned [437, 439]
Discarding 2 places :
Implicit Place search using SMT only with invariants took 925 ms to find 2 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 528/534 places, 498/498 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 527 transition count 497
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 527 transition count 497
Applied a total of 2 rules in 87 ms. Remains 527 /528 variables (removed 1) and now considering 497/498 (removed 1) transitions.
// Phase 1: matrix 497 rows 527 cols
[2023-03-09 05:45:59] [INFO ] Computed 49 place invariants in 42 ms
[2023-03-09 05:45:59] [INFO ] Implicit Places using invariants in 381 ms returned []
[2023-03-09 05:45:59] [INFO ] Invariant cache hit.
[2023-03-09 05:46:02] [INFO ] Implicit Places using invariants and state equation in 2259 ms returned []
Implicit Place search using SMT with State Equation took 2664 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 527/534 places, 497/498 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 3775 ms. Remains : 527/534 places, 497/498 transitions.
Support contains 125 out of 527 places after structural reductions.
[2023-03-09 05:46:02] [INFO ] Flatten gal took : 147 ms
[2023-03-09 05:46:02] [INFO ] Flatten gal took : 75 ms
[2023-03-09 05:46:02] [INFO ] Input system was already deterministic with 497 transitions.
Support contains 115 out of 527 places (down from 125) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 324 resets, run finished after 783 ms. (steps per millisecond=12 ) properties (out of 60) seen :3
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 52 ms. (steps per millisecond=19 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 46 ms. (steps per millisecond=21 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 45 ms. (steps per millisecond=22 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 42 ms. (steps per millisecond=23 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 45 ms. (steps per millisecond=22 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 24 resets, run finished after 44 ms. (steps per millisecond=22 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 44 ms. (steps per millisecond=22 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 27 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 25 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 61 ms. (steps per millisecond=16 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 23 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 28 resets, run finished after 35 ms. (steps per millisecond=28 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 30 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 25 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 42 ms. (steps per millisecond=23 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 31 resets, run finished after 42 ms. (steps per millisecond=23 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 28 resets, run finished after 44 ms. (steps per millisecond=22 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 26 resets, run finished after 38 ms. (steps per millisecond=26 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 30 resets, run finished after 30 ms. (steps per millisecond=33 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 27 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 33 ms. (steps per millisecond=30 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 28 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 43 ms. (steps per millisecond=23 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1001 steps, including 27 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 41 ms. (steps per millisecond=24 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 34 ms. (steps per millisecond=29 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 28 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 29 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 57) seen :0
Incomplete Best-First random walk after 1000 steps, including 26 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 57) seen :0
Interrupted probabilistic random walk after 204464 steps, run timeout after 6001 ms. (steps per millisecond=34 ) properties seen :{10=1, 11=1, 24=1, 29=1, 33=1, 38=1, 44=1, 51=1}
Probabilistic random walk after 204464 steps, saw 102245 distinct states, run finished after 6002 ms. (steps per millisecond=34 ) properties seen :8
Running SMT prover for 49 properties.
[2023-03-09 05:46:11] [INFO ] Invariant cache hit.
[2023-03-09 05:46:12] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 05:46:12] [INFO ] [Real]Absence check using 2 positive and 47 generalized place invariants in 31 ms returned sat
[2023-03-09 05:46:14] [INFO ] After 1015ms SMT Verify possible using state equation in real domain returned unsat :0 sat :5 real:44
[2023-03-09 05:46:14] [INFO ] Deduced a trap composed of 82 places in 287 ms of which 9 ms to minimize.
[2023-03-09 05:46:15] [INFO ] Deduced a trap composed of 104 places in 241 ms of which 2 ms to minimize.
[2023-03-09 05:46:15] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 649 ms
[2023-03-09 05:46:15] [INFO ] Deduced a trap composed of 103 places in 197 ms of which 1 ms to minimize.
[2023-03-09 05:46:15] [INFO ] Deduced a trap composed of 101 places in 144 ms of which 2 ms to minimize.
[2023-03-09 05:46:15] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 475 ms
[2023-03-09 05:46:16] [INFO ] Deduced a trap composed of 59 places in 239 ms of which 1 ms to minimize.
[2023-03-09 05:46:16] [INFO ] Deduced a trap composed of 41 places in 212 ms of which 1 ms to minimize.
[2023-03-09 05:46:16] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 555 ms
[2023-03-09 05:46:16] [INFO ] After 3127ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:49
[2023-03-09 05:46:16] [INFO ] After 4971ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:49
[2023-03-09 05:46:17] [INFO ] [Nat]Absence check using 2 positive place invariants in 3 ms returned sat
[2023-03-09 05:46:17] [INFO ] [Nat]Absence check using 2 positive and 47 generalized place invariants in 19 ms returned sat
[2023-03-09 05:46:21] [INFO ] After 3906ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :41
[2023-03-09 05:46:22] [INFO ] Deduced a trap composed of 43 places in 298 ms of which 1 ms to minimize.
[2023-03-09 05:46:22] [INFO ] Deduced a trap composed of 77 places in 166 ms of which 1 ms to minimize.
[2023-03-09 05:46:22] [INFO ] Deduced a trap composed of 79 places in 186 ms of which 0 ms to minimize.
[2023-03-09 05:46:22] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 789 ms
[2023-03-09 05:46:22] [INFO ] Deduced a trap composed of 115 places in 129 ms of which 0 ms to minimize.
[2023-03-09 05:46:22] [INFO ] Deduced a trap composed of 128 places in 118 ms of which 1 ms to minimize.
[2023-03-09 05:46:23] [INFO ] Deduced a trap composed of 121 places in 113 ms of which 1 ms to minimize.
[2023-03-09 05:46:23] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 497 ms
[2023-03-09 05:46:23] [INFO ] Deduced a trap composed of 55 places in 213 ms of which 1 ms to minimize.
[2023-03-09 05:46:23] [INFO ] Deduced a trap composed of 59 places in 218 ms of which 1 ms to minimize.
[2023-03-09 05:46:24] [INFO ] Deduced a trap composed of 41 places in 226 ms of which 1 ms to minimize.
[2023-03-09 05:46:24] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 831 ms
[2023-03-09 05:46:24] [INFO ] Deduced a trap composed of 113 places in 80 ms of which 0 ms to minimize.
[2023-03-09 05:46:24] [INFO ] Deduced a trap composed of 101 places in 91 ms of which 0 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Deduced a trap composed of 103 places in 100 ms of which 1 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Deduced a trap composed of 89 places in 146 ms of which 0 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Deduced a trap composed of 91 places in 161 ms of which 0 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Deduced a trap composed of 65 places in 230 ms of which 1 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Deduced a trap composed of 67 places in 136 ms of which 0 ms to minimize.
[2023-03-09 05:46:25] [INFO ] Trap strengthening (SAT) tested/added 8/7 trap constraints in 1237 ms
[2023-03-09 05:46:26] [INFO ] Deduced a trap composed of 53 places in 137 ms of which 1 ms to minimize.
[2023-03-09 05:46:26] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 210 ms
[2023-03-09 05:46:27] [INFO ] Deduced a trap composed of 47 places in 214 ms of which 0 ms to minimize.
[2023-03-09 05:46:27] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 289 ms
[2023-03-09 05:46:28] [INFO ] Deduced a trap composed of 127 places in 114 ms of which 1 ms to minimize.
[2023-03-09 05:46:28] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 215 ms
[2023-03-09 05:46:29] [INFO ] Deduced a trap composed of 95 places in 137 ms of which 1 ms to minimize.
[2023-03-09 05:46:29] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 232 ms
[2023-03-09 05:46:32] [INFO ] Deduced a trap composed of 83 places in 176 ms of which 1 ms to minimize.
[2023-03-09 05:46:32] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 270 ms
[2023-03-09 05:46:34] [INFO ] After 16186ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :41
Attempting to minimize the solution found.
Minimization took 6019 ms.
[2023-03-09 05:46:40] [INFO ] After 23371ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :41
Fused 49 Parikh solutions to 41 different solutions.
Parikh walk visited 0 properties in 31966 ms.
Support contains 70 out of 527 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 73 transitions
Trivial Post-agglo rules discarded 73 transitions
Performed 73 trivial Post agglomeration. Transition count delta: 73
Iterating post reduction 0 with 73 rules applied. Total rules applied 74 place count 526 transition count 423
Reduce places removed 73 places and 0 transitions.
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Iterating post reduction 1 with 90 rules applied. Total rules applied 164 place count 453 transition count 406
Reduce places removed 17 places and 0 transitions.
Iterating post reduction 2 with 17 rules applied. Total rules applied 181 place count 436 transition count 406
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 17 Pre rules applied. Total rules applied 181 place count 436 transition count 389
Deduced a syphon composed of 17 places in 4 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 3 with 34 rules applied. Total rules applied 215 place count 419 transition count 389
Performed 63 Post agglomeration using F-continuation condition.Transition count delta: 63
Deduced a syphon composed of 63 places in 2 ms
Reduce places removed 63 places and 0 transitions.
Iterating global reduction 3 with 126 rules applied. Total rules applied 341 place count 356 transition count 326
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 0
Deduced a syphon composed of 9 places in 5 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 359 place count 347 transition count 326
Free-agglomeration rule applied 1 times.
Iterating global reduction 3 with 1 rules applied. Total rules applied 360 place count 347 transition count 325
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 361 place count 346 transition count 325
Free-agglomeration rule (complex) applied 39 times.
Iterating global reduction 4 with 39 rules applied. Total rules applied 400 place count 346 transition count 286
Reduce places removed 39 places and 0 transitions.
Iterating post reduction 4 with 39 rules applied. Total rules applied 439 place count 307 transition count 286
Partial Free-agglomeration rule applied 29 times.
Drop transitions removed 29 transitions
Iterating global reduction 5 with 29 rules applied. Total rules applied 468 place count 307 transition count 286
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 5 with 1 rules applied. Total rules applied 469 place count 306 transition count 285
Applied a total of 469 rules in 180 ms. Remains 306 /527 variables (removed 221) and now considering 285/497 (removed 212) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 180 ms. Remains : 306/527 places, 285/497 transitions.
Incomplete random walk after 10000 steps, including 1279 resets, run finished after 499 ms. (steps per millisecond=20 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 90 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 88 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 70 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 86 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 82 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 88 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 87 resets, run finished after 36 ms. (steps per millisecond=27 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 88 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 85 resets, run finished after 39 ms. (steps per millisecond=25 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 82 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 93 resets, run finished after 37 ms. (steps per millisecond=27 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 87 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 84 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 94 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 86 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 83 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 82 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 80 resets, run finished after 40 ms. (steps per millisecond=25 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 88 resets, run finished after 51 ms. (steps per millisecond=19 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 85 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 79 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 91 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 88 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 90 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 93 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 92 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 88 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 96 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 81 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 80 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 82 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 71 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 85 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 81 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 93 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 81 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 89 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 80 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1000 steps, including 81 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 87 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 41) seen :0
Incomplete Best-First random walk after 1001 steps, including 89 resets, run finished after 24 ms. (steps per millisecond=41 ) properties (out of 41) seen :0
Interrupted probabilistic random walk after 120084 steps, run timeout after 3001 ms. (steps per millisecond=40 ) properties seen :{18=1}
Probabilistic random walk after 120084 steps, saw 60086 distinct states, run finished after 3001 ms. (steps per millisecond=40 ) properties seen :1
Running SMT prover for 40 properties.
// Phase 1: matrix 285 rows 306 cols
[2023-03-09 05:47:16] [INFO ] Computed 49 place invariants in 33 ms
[2023-03-09 05:47:17] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 05:47:17] [INFO ] [Real]Absence check using 2 positive and 47 generalized place invariants in 23 ms returned sat
[2023-03-09 05:47:19] [INFO ] After 1719ms SMT Verify possible using state equation in real domain returned unsat :0 sat :6 real:34
[2023-03-09 05:47:19] [INFO ] State equation strengthened by 26 read => feed constraints.
[2023-03-09 05:47:19] [INFO ] After 694ms SMT Verify possible using 26 Read/Feed constraints in real domain returned unsat :0 sat :2 real:38
[2023-03-09 05:47:20] [INFO ] After 777ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:40
[2023-03-09 05:47:20] [INFO ] After 3154ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:40
[2023-03-09 05:47:20] [INFO ] [Nat]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-09 05:47:20] [INFO ] [Nat]Absence check using 2 positive and 47 generalized place invariants in 26 ms returned sat
[2023-03-09 05:47:22] [INFO ] After 1945ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :40
[2023-03-09 05:47:25] [INFO ] After 2944ms SMT Verify possible using 26 Read/Feed constraints in natural domain returned unsat :0 sat :40
[2023-03-09 05:47:25] [INFO ] Deduced a trap composed of 11 places in 112 ms of which 2 ms to minimize.
[2023-03-09 05:47:26] [INFO ] Deduced a trap composed of 12 places in 93 ms of which 1 ms to minimize.
[2023-03-09 05:47:26] [INFO ] Deduced a trap composed of 17 places in 82 ms of which 1 ms to minimize.
[2023-03-09 05:47:26] [INFO ] Deduced a trap composed of 38 places in 92 ms of which 1 ms to minimize.
[2023-03-09 05:47:26] [INFO ] Deduced a trap composed of 17 places in 93 ms of which 1 ms to minimize.
[2023-03-09 05:47:26] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 646 ms
[2023-03-09 05:47:27] [INFO ] Deduced a trap composed of 17 places in 96 ms of which 2 ms to minimize.
[2023-03-09 05:47:27] [INFO ] Deduced a trap composed of 26 places in 84 ms of which 0 ms to minimize.
[2023-03-09 05:47:27] [INFO ] Deduced a trap composed of 24 places in 78 ms of which 1 ms to minimize.
[2023-03-09 05:47:27] [INFO ] Deduced a trap composed of 22 places in 86 ms of which 1 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 35 places in 129 ms of which 1 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 30 places in 114 ms of which 0 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 33 places in 103 ms of which 1 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 46 places in 103 ms of which 1 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 35 places in 89 ms of which 0 ms to minimize.
[2023-03-09 05:47:28] [INFO ] Deduced a trap composed of 45 places in 82 ms of which 0 ms to minimize.
[2023-03-09 05:47:29] [INFO ] Deduced a trap composed of 31 places in 83 ms of which 0 ms to minimize.
[2023-03-09 05:47:29] [INFO ] Deduced a trap composed of 34 places in 84 ms of which 1 ms to minimize.
[2023-03-09 05:47:29] [INFO ] Deduced a trap composed of 43 places in 70 ms of which 0 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 47 places in 64 ms of which 0 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 52 places in 70 ms of which 1 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 55 places in 66 ms of which 0 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 55 places in 65 ms of which 2 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 51 places in 69 ms of which 1 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 53 places in 57 ms of which 1 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 40 places in 72 ms of which 1 ms to minimize.
[2023-03-09 05:47:30] [INFO ] Deduced a trap composed of 41 places in 82 ms of which 1 ms to minimize.
[2023-03-09 05:47:31] [INFO ] Deduced a trap composed of 35 places in 73 ms of which 0 ms to minimize.
[2023-03-09 05:47:31] [INFO ] Deduced a trap composed of 29 places in 79 ms of which 1 ms to minimize.
[2023-03-09 05:47:31] [INFO ] Deduced a trap composed of 42 places in 68 ms of which 3 ms to minimize.
[2023-03-09 05:47:31] [INFO ] Deduced a trap composed of 47 places in 63 ms of which 0 ms to minimize.
[2023-03-09 05:47:32] [INFO ] Deduced a trap composed of 43 places in 73 ms of which 1 ms to minimize.
[2023-03-09 05:47:32] [INFO ] Deduced a trap composed of 55 places in 57 ms of which 0 ms to minimize.
[2023-03-09 05:47:32] [INFO ] Deduced a trap composed of 51 places in 58 ms of which 0 ms to minimize.
[2023-03-09 05:47:32] [INFO ] Deduced a trap composed of 53 places in 41 ms of which 0 ms to minimize.
[2023-03-09 05:47:32] [INFO ] Trap strengthening (SAT) tested/added 30/29 trap constraints in 5544 ms
[2023-03-09 05:47:35] [INFO ] Deduced a trap composed of 29 places in 98 ms of which 1 ms to minimize.
[2023-03-09 05:47:36] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 137 ms
[2023-03-09 05:47:36] [INFO ] After 13891ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :40
Attempting to minimize the solution found.
Minimization took 2939 ms.
[2023-03-09 05:47:39] [INFO ] After 19576ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :40
Parikh walk visited 0 properties in 31074 ms.
Support contains 68 out of 306 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 306/306 places, 285/285 transitions.
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 306 transition count 284
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 305 transition count 284
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 305 transition count 284
Applied a total of 3 rules in 51 ms. Remains 305 /306 variables (removed 1) and now considering 284/285 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 52 ms. Remains : 305/306 places, 284/285 transitions.
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
FORMULA DoubleExponent-PT-010-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 05:48:10] [INFO ] Flatten gal took : 34 ms
[2023-03-09 05:48:10] [INFO ] Flatten gal took : 36 ms
[2023-03-09 05:48:10] [INFO ] Input system was already deterministic with 497 transitions.
Support contains 81 out of 527 places (down from 86) after GAL structural reductions.
Computed a total of 7 stabilizing places and 7 stable transitions
Graph (complete) has 895 edges and 527 vertex of which 525 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.9 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.3 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 119 transitions
Trivial Post-agglo rules discarded 119 transitions
Performed 119 trivial Post agglomeration. Transition count delta: 119
Iterating post reduction 0 with 119 rules applied. Total rules applied 120 place count 525 transition count 376
Reduce places removed 119 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 121 rules applied. Total rules applied 241 place count 406 transition count 374
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 243 place count 404 transition count 374
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 20 Pre rules applied. Total rules applied 243 place count 404 transition count 354
Deduced a syphon composed of 20 places in 3 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 3 with 40 rules applied. Total rules applied 283 place count 384 transition count 354
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 1 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 3 with 140 rules applied. Total rules applied 423 place count 314 transition count 284
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 424 place count 313 transition count 283
Applied a total of 424 rules in 86 ms. Remains 313 /527 variables (removed 214) and now considering 283/497 (removed 214) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 86 ms. Remains : 313/527 places, 283/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 18 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 21 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 283 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 27 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 27 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 31 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.3 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 115 transitions
Trivial Post-agglo rules discarded 115 transitions
Performed 115 trivial Post agglomeration. Transition count delta: 115
Iterating post reduction 0 with 115 rules applied. Total rules applied 116 place count 525 transition count 380
Reduce places removed 115 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 1 with 119 rules applied. Total rules applied 235 place count 410 transition count 376
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 239 place count 406 transition count 376
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 21 Pre rules applied. Total rules applied 239 place count 406 transition count 355
Deduced a syphon composed of 21 places in 3 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 3 with 42 rules applied. Total rules applied 281 place count 385 transition count 355
Performed 68 Post agglomeration using F-continuation condition.Transition count delta: 68
Deduced a syphon composed of 68 places in 1 ms
Reduce places removed 68 places and 0 transitions.
Iterating global reduction 3 with 136 rules applied. Total rules applied 417 place count 317 transition count 287
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 418 place count 316 transition count 286
Applied a total of 418 rules in 80 ms. Remains 316 /527 variables (removed 211) and now considering 286/497 (removed 211) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 80 ms. Remains : 316/527 places, 286/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 18 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 286 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 26 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 25 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 23 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 49 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 51 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 23 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 23 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 121 transitions
Trivial Post-agglo rules discarded 121 transitions
Performed 121 trivial Post agglomeration. Transition count delta: 121
Iterating post reduction 0 with 121 rules applied. Total rules applied 122 place count 525 transition count 374
Reduce places removed 121 places and 0 transitions.
Iterating post reduction 1 with 121 rules applied. Total rules applied 243 place count 404 transition count 374
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 20 Pre rules applied. Total rules applied 243 place count 404 transition count 354
Deduced a syphon composed of 20 places in 6 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 2 with 40 rules applied. Total rules applied 283 place count 384 transition count 354
Performed 69 Post agglomeration using F-continuation condition.Transition count delta: 69
Deduced a syphon composed of 69 places in 2 ms
Reduce places removed 69 places and 0 transitions.
Iterating global reduction 2 with 138 rules applied. Total rules applied 421 place count 315 transition count 285
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 422 place count 314 transition count 284
Applied a total of 422 rules in 79 ms. Remains 314 /527 variables (removed 213) and now considering 284/497 (removed 213) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 80 ms. Remains : 314/527 places, 284/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 14 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 14 ms
[2023-03-09 05:48:11] [INFO ] Input system was already deterministic with 284 transitions.
Incomplete random walk after 10000 steps, including 1029 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 688 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Finished probabilistic random walk after 4276 steps, run visited all 1 properties in 37 ms. (steps per millisecond=115 )
Probabilistic random walk after 4276 steps, saw 2163 distinct states, run finished after 38 ms. (steps per millisecond=112 ) properties seen :1
FORMULA DoubleExponent-PT-010-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL PROBABILISTIC_WALK
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 26 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 22 ms
[2023-03-09 05:48:11] [INFO ] Flatten gal took : 18 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 24 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 17 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.1 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 121 transitions
Trivial Post-agglo rules discarded 121 transitions
Performed 121 trivial Post agglomeration. Transition count delta: 121
Iterating post reduction 0 with 121 rules applied. Total rules applied 122 place count 525 transition count 374
Reduce places removed 121 places and 0 transitions.
Iterating post reduction 1 with 121 rules applied. Total rules applied 243 place count 404 transition count 374
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 20 Pre rules applied. Total rules applied 243 place count 404 transition count 354
Deduced a syphon composed of 20 places in 3 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 2 with 40 rules applied. Total rules applied 283 place count 384 transition count 354
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 2 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 2 with 140 rules applied. Total rules applied 423 place count 314 transition count 284
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 424 place count 313 transition count 283
Applied a total of 424 rules in 56 ms. Remains 313 /527 variables (removed 214) and now considering 283/497 (removed 214) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 57 ms. Remains : 313/527 places, 283/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 10 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 11 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 283 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.1 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 118 transitions
Trivial Post-agglo rules discarded 118 transitions
Performed 118 trivial Post agglomeration. Transition count delta: 118
Iterating post reduction 0 with 118 rules applied. Total rules applied 119 place count 525 transition count 377
Reduce places removed 118 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 119 rules applied. Total rules applied 238 place count 407 transition count 376
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 239 place count 406 transition count 376
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 21 Pre rules applied. Total rules applied 239 place count 406 transition count 355
Deduced a syphon composed of 21 places in 6 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 3 with 42 rules applied. Total rules applied 281 place count 385 transition count 355
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 2 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 3 with 140 rules applied. Total rules applied 421 place count 315 transition count 285
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 422 place count 315 transition count 285
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 423 place count 314 transition count 284
Applied a total of 423 rules in 78 ms. Remains 314 /527 variables (removed 213) and now considering 284/497 (removed 213) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 79 ms. Remains : 314/527 places, 284/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 10 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 11 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 284 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.1 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 120 transitions
Trivial Post-agglo rules discarded 120 transitions
Performed 120 trivial Post agglomeration. Transition count delta: 120
Iterating post reduction 0 with 120 rules applied. Total rules applied 121 place count 525 transition count 375
Reduce places removed 120 places and 0 transitions.
Iterating post reduction 1 with 120 rules applied. Total rules applied 241 place count 405 transition count 375
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 20 Pre rules applied. Total rules applied 241 place count 405 transition count 355
Deduced a syphon composed of 20 places in 4 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 2 with 40 rules applied. Total rules applied 281 place count 385 transition count 355
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 3 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 2 with 140 rules applied. Total rules applied 421 place count 315 transition count 285
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 2 with 1 rules applied. Total rules applied 422 place count 314 transition count 284
Applied a total of 422 rules in 55 ms. Remains 314 /527 variables (removed 213) and now considering 284/497 (removed 213) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 56 ms. Remains : 314/527 places, 284/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 11 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 11 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 284 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Graph (complete) has 895 edges and 527 vertex of which 526 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.2 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 117 transitions
Trivial Post-agglo rules discarded 117 transitions
Performed 117 trivial Post agglomeration. Transition count delta: 117
Iterating post reduction 0 with 117 rules applied. Total rules applied 118 place count 525 transition count 378
Reduce places removed 117 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 119 rules applied. Total rules applied 237 place count 408 transition count 376
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 239 place count 406 transition count 376
Performed 21 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 21 Pre rules applied. Total rules applied 239 place count 406 transition count 355
Deduced a syphon composed of 21 places in 3 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 3 with 42 rules applied. Total rules applied 281 place count 385 transition count 355
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 1 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 3 with 140 rules applied. Total rules applied 421 place count 315 transition count 285
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 3 with 1 rules applied. Total rules applied 422 place count 314 transition count 284
Applied a total of 422 rules in 67 ms. Remains 314 /527 variables (removed 213) and now considering 284/497 (removed 213) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 67 ms. Remains : 314/527 places, 284/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 10 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 11 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 284 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 12 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 15 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 50 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in LTL mode, iteration 0 : 527/527 places, 497/497 transitions.
Applied a total of 0 rules in 23 ms. Remains 527 /527 variables (removed 0) and now considering 497/497 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 527/527 places, 497/497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 15 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 20 ms
[2023-03-09 05:48:12] [INFO ] Input system was already deterministic with 497 transitions.
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 15 ms
[2023-03-09 05:48:12] [INFO ] Flatten gal took : 16 ms
[2023-03-09 05:48:12] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-09 05:48:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 527 places, 497 transitions and 1392 arcs took 4 ms.
Total runtime 135150 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DoubleExponent-PT-010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA DoubleExponent-PT-010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DoubleExponent-PT-010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 11235712 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16278232 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 17 (type EXCL) for 16 DoubleExponent-PT-010-CTLFireability-04
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for DoubleExponent-PT-010-CTLFireability-04
lola: result : false
lola: markings : 27
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 39 (type EXCL) for 38 DoubleExponent-PT-010-CTLFireability-12
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DoubleExponent-PT-010-CTLFireability-12
lola: result : true
lola: markings : 8
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 52 (type EXCL) for 44 DoubleExponent-PT-010-CTLFireability-14
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 50 (type FNDP) for 44 DoubleExponent-PT-010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 44 DoubleExponent-PT-010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SRCH) for 44 DoubleExponent-PT-010-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 53 (type SRCH) for DoubleExponent-PT-010-CTLFireability-14
lola: result : unknown
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/375/CTLFireability-51.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:665
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 55 (type FNDP) for 0 DoubleExponent-PT-010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: warning, failure of lp_solve (at job 19)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 5 0 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 3 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 4/1199 0/5 DoubleExponent-PT-010-CTLFireability-14 1535851 t fired, 157531 attempts, .
51 EF STEQ 4/1199 0/5 DoubleExponent-PT-010-CTLFireability-14 sara is running.
52 EF EXCL 4/257 3/32 DoubleExponent-PT-010-CTLFireability-14 586305 m, 117261 m/sec, 586304 t fired, .
55 EF FNDP 4/1799 0/5 DoubleExponent-PT-010-CTLFireability-00 641442 t fired, 65705 attempts, .

Time elapsed: 5 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 14

lola: FINISHED task # 51 (type EQUN) for DoubleExponent-PT-010-CTLFireability-14
lola: result : unknown
lola: LAUNCH task # 62 (type FNDP) for 19 DoubleExponent-PT-010-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 9/1791 0/5 DoubleExponent-PT-010-CTLFireability-14 3234144 t fired, 331286 attempts, .
52 EF EXCL 9/257 5/32 DoubleExponent-PT-010-CTLFireability-14 1254884 m, 133715 m/sec, 1254883 t fired, .
55 EF FNDP 9/1791 0/5 DoubleExponent-PT-010-CTLFireability-00 1386245 t fired, 142111 attempts, .
62 EF FNDP 1/1197 0/5 DoubleExponent-PT-010-CTLFireability-06 403484 t fired, 41372 attempts, .

Time elapsed: 10 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 14/1790 0/5 DoubleExponent-PT-010-CTLFireability-14 4719378 t fired, 483427 attempts, .
52 EF EXCL 14/257 7/32 DoubleExponent-PT-010-CTLFireability-14 1905886 m, 130200 m/sec, 1905885 t fired, .
55 EF FNDP 14/1790 0/5 DoubleExponent-PT-010-CTLFireability-00 2086778 t fired, 214074 attempts, .
62 EF FNDP 6/1196 0/5 DoubleExponent-PT-010-CTLFireability-06 2022425 t fired, 207223 attempts, .

Time elapsed: 15 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 19/1785 0/5 DoubleExponent-PT-010-CTLFireability-14 6207164 t fired, 635960 attempts, .
52 EF EXCL 19/257 10/32 DoubleExponent-PT-010-CTLFireability-14 2553614 m, 129545 m/sec, 2553614 t fired, .
55 EF FNDP 19/1785 0/5 DoubleExponent-PT-010-CTLFireability-00 2787643 t fired, 286104 attempts, .
62 EF FNDP 11/1191 0/5 DoubleExponent-PT-010-CTLFireability-06 3642971 t fired, 373451 attempts, .

Time elapsed: 20 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 24/1780 0/5 DoubleExponent-PT-010-CTLFireability-14 7699364 t fired, 789160 attempts, .
52 EF EXCL 24/257 12/32 DoubleExponent-PT-010-CTLFireability-14 3198582 m, 128993 m/sec, 3198581 t fired, .
55 EF FNDP 24/1780 0/5 DoubleExponent-PT-010-CTLFireability-00 3488683 t fired, 358159 attempts, .
62 EF FNDP 16/1186 0/5 DoubleExponent-PT-010-CTLFireability-06 5263062 t fired, 539478 attempts, .

Time elapsed: 25 secs. Pages in use: 12
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 29/1775 0/5 DoubleExponent-PT-010-CTLFireability-14 9187486 t fired, 941975 attempts, .
52 EF EXCL 29/257 14/32 DoubleExponent-PT-010-CTLFireability-14 3843930 m, 129069 m/sec, 3843929 t fired, .
55 EF FNDP 29/1775 0/5 DoubleExponent-PT-010-CTLFireability-00 4188627 t fired, 429838 attempts, .
62 EF FNDP 21/1181 0/5 DoubleExponent-PT-010-CTLFireability-06 6878770 t fired, 704942 attempts, .

Time elapsed: 30 secs. Pages in use: 14
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 34/1770 0/5 DoubleExponent-PT-010-CTLFireability-14 10676442 t fired, 1094941 attempts, .
52 EF EXCL 34/257 17/32 DoubleExponent-PT-010-CTLFireability-14 4483257 m, 127865 m/sec, 4483256 t fired, .
55 EF FNDP 34/1770 0/5 DoubleExponent-PT-010-CTLFireability-00 4889592 t fired, 501855 attempts, .
62 EF FNDP 26/1176 0/5 DoubleExponent-PT-010-CTLFireability-06 8499717 t fired, 871276 attempts, .

Time elapsed: 35 secs. Pages in use: 17
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 39/1765 0/5 DoubleExponent-PT-010-CTLFireability-14 12165676 t fired, 1247576 attempts, .
52 EF EXCL 39/257 19/32 DoubleExponent-PT-010-CTLFireability-14 5123176 m, 127983 m/sec, 5123175 t fired, .
55 EF FNDP 39/1765 0/5 DoubleExponent-PT-010-CTLFireability-00 5590639 t fired, 573849 attempts, .
62 EF FNDP 31/1171 0/5 DoubleExponent-PT-010-CTLFireability-06 10117986 t fired, 1037170 attempts, .

Time elapsed: 40 secs. Pages in use: 19
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 44/1760 0/5 DoubleExponent-PT-010-CTLFireability-14 13653760 t fired, 1399793 attempts, .
52 EF EXCL 44/257 21/32 DoubleExponent-PT-010-CTLFireability-14 5757553 m, 126875 m/sec, 5757552 t fired, .
55 EF FNDP 44/1760 0/5 DoubleExponent-PT-010-CTLFireability-00 6291673 t fired, 645627 attempts, .
62 EF FNDP 36/1166 0/5 DoubleExponent-PT-010-CTLFireability-06 11739604 t fired, 1203554 attempts, .

Time elapsed: 45 secs. Pages in use: 21
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 49/1755 0/5 DoubleExponent-PT-010-CTLFireability-14 15139293 t fired, 1552148 attempts, .
52 EF EXCL 49/257 24/32 DoubleExponent-PT-010-CTLFireability-14 6396438 m, 127777 m/sec, 6396437 t fired, .
55 EF FNDP 49/1755 0/5 DoubleExponent-PT-010-CTLFireability-00 6993176 t fired, 717506 attempts, .
62 EF FNDP 41/1161 0/5 DoubleExponent-PT-010-CTLFireability-06 13360236 t fired, 1369559 attempts, .

Time elapsed: 50 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 54/1750 0/5 DoubleExponent-PT-010-CTLFireability-14 16624727 t fired, 1704399 attempts, .
52 EF EXCL 54/257 26/32 DoubleExponent-PT-010-CTLFireability-14 7035065 m, 127725 m/sec, 7035064 t fired, .
55 EF FNDP 54/1750 0/5 DoubleExponent-PT-010-CTLFireability-00 7693761 t fired, 789424 attempts, .
62 EF FNDP 46/1156 0/5 DoubleExponent-PT-010-CTLFireability-06 14977016 t fired, 1535467 attempts, .

Time elapsed: 55 secs. Pages in use: 26
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 59/1745 0/5 DoubleExponent-PT-010-CTLFireability-14 18109895 t fired, 1856200 attempts, .
52 EF EXCL 59/257 28/32 DoubleExponent-PT-010-CTLFireability-14 7669141 m, 126815 m/sec, 7669140 t fired, .
55 EF FNDP 59/1745 0/5 DoubleExponent-PT-010-CTLFireability-00 8395221 t fired, 861473 attempts, .
62 EF FNDP 51/1151 0/5 DoubleExponent-PT-010-CTLFireability-06 16593070 t fired, 1701217 attempts, .

Time elapsed: 60 secs. Pages in use: 28
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 64/1740 0/5 DoubleExponent-PT-010-CTLFireability-14 19594235 t fired, 2008758 attempts, .
52 EF EXCL 64/257 30/32 DoubleExponent-PT-010-CTLFireability-14 8305836 m, 127339 m/sec, 8305836 t fired, .
55 EF FNDP 64/1740 0/5 DoubleExponent-PT-010-CTLFireability-00 9096937 t fired, 933474 attempts, .
62 EF FNDP 56/1146 0/5 DoubleExponent-PT-010-CTLFireability-06 18208579 t fired, 1867152 attempts, .

Time elapsed: 65 secs. Pages in use: 30
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 52 (type EXCL) for DoubleExponent-PT-010-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-010-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 69/1735 0/5 DoubleExponent-PT-010-CTLFireability-14 21083453 t fired, 2161614 attempts, .
55 EF FNDP 69/1735 0/5 DoubleExponent-PT-010-CTLFireability-00 9799691 t fired, 1005413 attempts, .
62 EF FNDP 61/1141 0/5 DoubleExponent-PT-010-CTLFireability-06 19827323 t fired, 2033132 attempts, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 48 (type EXCL) for 47 DoubleExponent-PT-010-CTLFireability-15
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for DoubleExponent-PT-010-CTLFireability-15
lola: result : true
lola: markings : 25
lola: fired transitions : 50
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 DoubleExponent-PT-010-CTLFireability-13
lola: time limit : 294 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/294 6/32 DoubleExponent-PT-010-CTLFireability-13 1073447 m, 214689 m/sec, 1073448 t fired, .
50 EF FNDP 74/1730 0/5 DoubleExponent-PT-010-CTLFireability-14 22616061 t fired, 2318954 attempts, .
55 EF FNDP 74/1730 0/5 DoubleExponent-PT-010-CTLFireability-00 10506982 t fired, 1077905 attempts, .
62 EF FNDP 66/1136 0/5 DoubleExponent-PT-010-CTLFireability-06 21508232 t fired, 2205627 attempts, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/294 12/32 DoubleExponent-PT-010-CTLFireability-13 2132283 m, 211767 m/sec, 2132284 t fired, .
50 EF FNDP 79/1725 0/5 DoubleExponent-PT-010-CTLFireability-14 24146068 t fired, 2475823 attempts, .
55 EF FNDP 79/1725 0/5 DoubleExponent-PT-010-CTLFireability-00 11214377 t fired, 1150530 attempts, .
62 EF FNDP 71/1131 0/5 DoubleExponent-PT-010-CTLFireability-06 23187649 t fired, 2377939 attempts, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/294 17/32 DoubleExponent-PT-010-CTLFireability-13 3184318 m, 210407 m/sec, 3184319 t fired, .
50 EF FNDP 84/1720 0/5 DoubleExponent-PT-010-CTLFireability-14 25678193 t fired, 2632710 attempts, .
55 EF FNDP 84/1720 0/5 DoubleExponent-PT-010-CTLFireability-00 11922311 t fired, 1223047 attempts, .
62 EF FNDP 76/1126 0/5 DoubleExponent-PT-010-CTLFireability-06 24868249 t fired, 2550115 attempts, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/294 23/32 DoubleExponent-PT-010-CTLFireability-13 4220683 m, 207273 m/sec, 4220684 t fired, .
50 EF FNDP 89/1715 0/5 DoubleExponent-PT-010-CTLFireability-14 27210450 t fired, 2789810 attempts, .
55 EF FNDP 89/1715 0/5 DoubleExponent-PT-010-CTLFireability-00 12628131 t fired, 1295141 attempts, .
62 EF FNDP 81/1121 0/5 DoubleExponent-PT-010-CTLFireability-06 26548269 t fired, 2722641 attempts, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/294 28/32 DoubleExponent-PT-010-CTLFireability-13 5248355 m, 205534 m/sec, 5248356 t fired, .
50 EF FNDP 94/1710 0/5 DoubleExponent-PT-010-CTLFireability-14 28740886 t fired, 2946951 attempts, .
55 EF FNDP 94/1710 0/5 DoubleExponent-PT-010-CTLFireability-00 13334823 t fired, 1367630 attempts, .
62 EF FNDP 86/1116 0/5 DoubleExponent-PT-010-CTLFireability-06 28226539 t fired, 2894753 attempts, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 42 (type EXCL) for DoubleExponent-PT-010-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 99/1705 0/5 DoubleExponent-PT-010-CTLFireability-14 30265660 t fired, 3103325 attempts, .
55 EF FNDP 99/1705 0/5 DoubleExponent-PT-010-CTLFireability-00 14046504 t fired, 1440567 attempts, .
62 EF FNDP 91/1111 0/5 DoubleExponent-PT-010-CTLFireability-06 29894876 t fired, 3066028 attempts, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 27 (type EXCL) for 26 DoubleExponent-PT-010-CTLFireability-08
lola: time limit : 318 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/318 2/32 DoubleExponent-PT-010-CTLFireability-08 258074 m, 51614 m/sec, 1016026 t fired, .
50 EF FNDP 104/1700 0/5 DoubleExponent-PT-010-CTLFireability-14 31795495 t fired, 3260245 attempts, .
55 EF FNDP 104/1700 0/5 DoubleExponent-PT-010-CTLFireability-00 14750516 t fired, 1512582 attempts, .
62 EF FNDP 96/1106 0/5 DoubleExponent-PT-010-CTLFireability-06 31559160 t fired, 3236372 attempts, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/318 3/32 DoubleExponent-PT-010-CTLFireability-08 514800 m, 51345 m/sec, 2026688 t fired, .
50 EF FNDP 109/1695 0/5 DoubleExponent-PT-010-CTLFireability-14 33324187 t fired, 3417172 attempts, .
55 EF FNDP 109/1695 0/5 DoubleExponent-PT-010-CTLFireability-00 15456382 t fired, 1584748 attempts, .
62 EF FNDP 101/1101 0/5 DoubleExponent-PT-010-CTLFireability-06 33225926 t fired, 3407221 attempts, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/318 4/32 DoubleExponent-PT-010-CTLFireability-08 770804 m, 51200 m/sec, 3034538 t fired, .
50 EF FNDP 114/1690 0/5 DoubleExponent-PT-010-CTLFireability-14 34855578 t fired, 3574018 attempts, .
55 EF FNDP 114/1690 0/5 DoubleExponent-PT-010-CTLFireability-00 16163878 t fired, 1657351 attempts, .
62 EF FNDP 106/1096 0/5 DoubleExponent-PT-010-CTLFireability-06 34905090 t fired, 3579607 attempts, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 20/318 6/32 DoubleExponent-PT-010-CTLFireability-08 1025273 m, 50893 m/sec, 4036203 t fired, .
50 EF FNDP 119/1685 0/5 DoubleExponent-PT-010-CTLFireability-14 36382344 t fired, 3730480 attempts, .
55 EF FNDP 119/1685 0/5 DoubleExponent-PT-010-CTLFireability-00 16870254 t fired, 1729663 attempts, .
62 EF FNDP 111/1091 0/5 DoubleExponent-PT-010-CTLFireability-06 36578919 t fired, 3751542 attempts, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 25/318 7/32 DoubleExponent-PT-010-CTLFireability-08 1280131 m, 50971 m/sec, 5039558 t fired, .
50 EF FNDP 124/1680 0/5 DoubleExponent-PT-010-CTLFireability-14 37907817 t fired, 3886810 attempts, .
55 EF FNDP 124/1680 0/5 DoubleExponent-PT-010-CTLFireability-00 17575503 t fired, 1802038 attempts, .
62 EF FNDP 116/1086 0/5 DoubleExponent-PT-010-CTLFireability-06 38225189 t fired, 3920089 attempts, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 30/318 8/32 DoubleExponent-PT-010-CTLFireability-08 1533866 m, 50747 m/sec, 6038399 t fired, .
50 EF FNDP 129/1675 0/5 DoubleExponent-PT-010-CTLFireability-14 39429680 t fired, 4043084 attempts, .
55 EF FNDP 129/1675 0/5 DoubleExponent-PT-010-CTLFireability-00 18280989 t fired, 1874194 attempts, .
62 EF FNDP 121/1081 0/5 DoubleExponent-PT-010-CTLFireability-06 39868216 t fired, 4088329 attempts, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 35/318 10/32 DoubleExponent-PT-010-CTLFireability-08 1786740 m, 50574 m/sec, 7033917 t fired, .
50 EF FNDP 134/1670 0/5 DoubleExponent-PT-010-CTLFireability-14 40953784 t fired, 4199212 attempts, .
55 EF FNDP 134/1670 0/5 DoubleExponent-PT-010-CTLFireability-00 18987516 t fired, 1946792 attempts, .
62 EF FNDP 126/1076 0/5 DoubleExponent-PT-010-CTLFireability-06 41536357 t fired, 4259512 attempts, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 40/318 11/32 DoubleExponent-PT-010-CTLFireability-08 2038667 m, 50385 m/sec, 8025707 t fired, .
50 EF FNDP 139/1665 0/5 DoubleExponent-PT-010-CTLFireability-14 42479365 t fired, 4355620 attempts, .
55 EF FNDP 139/1665 0/5 DoubleExponent-PT-010-CTLFireability-00 19693349 t fired, 2019151 attempts, .
62 EF FNDP 131/1071 0/5 DoubleExponent-PT-010-CTLFireability-06 43213389 t fired, 4431356 attempts, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 4 1 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 45/318 12/32 DoubleExponent-PT-010-CTLFireability-08 2289404 m, 50147 m/sec, 9012721 t fired, .
50 EF FNDP 144/1660 0/5 DoubleExponent-PT-010-CTLFireability-14 44005351 t fired, 4512271 attempts, .
55 EF FNDP 144/1660 0/5 DoubleExponent-PT-010-CTLFireability-00 20398950 t fired, 2091177 attempts, .
62 EF FNDP 136/1066 0/5 DoubleExponent-PT-010-CTLFireability-06 44888747 t fired, 4603239 attempts, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: FINISHED task # 27 (type EXCL) for DoubleExponent-PT-010-CTLFireability-08
lola: result : true
lola: markings : 2385129
lola: fired transitions : 9387310
lola: time used : 47.000000
lola: memory pages used : 13
lola: LAUNCH task # 24 (type EXCL) for 19 DoubleExponent-PT-010-CTLFireability-06
lola: time limit : 345 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for DoubleExponent-PT-010-CTLFireability-06
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DoubleExponent-PT-010-CTLFireability-03
lola: time limit : 383 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for DoubleExponent-PT-010-CTLFireability-03
lola: result : true
lola: markings : 24
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 7 DoubleExponent-PT-010-CTLFireability-01
lola: time limit : 431 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for DoubleExponent-PT-010-CTLFireability-01
lola: result : true
lola: markings : 25
lola: fired transitions : 74
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 0 DoubleExponent-PT-010-CTLFireability-00
lola: time limit : 493 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 149/1653 0/5 DoubleExponent-PT-010-CTLFireability-14 45531577 t fired, 4668905 attempts, .
55 EF FNDP 149/1653 0/5 DoubleExponent-PT-010-CTLFireability-00 21103383 t fired, 2163682 attempts, .
57 EF EXCL 3/493 2/32 DoubleExponent-PT-010-CTLFireability-00 428535 m, 85707 m/sec, 428534 t fired, .
62 EF FNDP 141/1059 0/5 DoubleExponent-PT-010-CTLFireability-06 46565354 t fired, 4774892 attempts, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 154/1650 0/5 DoubleExponent-PT-010-CTLFireability-14 47063584 t fired, 4825954 attempts, .
55 EF FNDP 154/1650 0/5 DoubleExponent-PT-010-CTLFireability-00 21808195 t fired, 2236076 attempts, .
57 EF EXCL 8/493 4/32 DoubleExponent-PT-010-CTLFireability-00 1113261 m, 136945 m/sec, 1113261 t fired, .
62 EF FNDP 146/1056 0/5 DoubleExponent-PT-010-CTLFireability-06 48255922 t fired, 4948222 attempts, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 159/1645 0/5 DoubleExponent-PT-010-CTLFireability-14 48590417 t fired, 4982653 attempts, .
55 EF FNDP 159/1645 0/5 DoubleExponent-PT-010-CTLFireability-00 22516514 t fired, 2308721 attempts, .
57 EF EXCL 13/493 7/32 DoubleExponent-PT-010-CTLFireability-00 1794933 m, 136334 m/sec, 1794933 t fired, .
62 EF FNDP 151/1051 0/5 DoubleExponent-PT-010-CTLFireability-06 49941035 t fired, 5120901 attempts, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 164/1640 0/5 DoubleExponent-PT-010-CTLFireability-14 50114858 t fired, 5138973 attempts, .
55 EF FNDP 164/1640 0/5 DoubleExponent-PT-010-CTLFireability-00 23225267 t fired, 2381321 attempts, .
57 EF EXCL 18/493 9/32 DoubleExponent-PT-010-CTLFireability-00 2472738 m, 135561 m/sec, 2472737 t fired, .
62 EF FNDP 156/1046 0/5 DoubleExponent-PT-010-CTLFireability-06 51624303 t fired, 5293398 attempts, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 169/1635 0/5 DoubleExponent-PT-010-CTLFireability-14 51641325 t fired, 5295695 attempts, .
55 EF FNDP 169/1635 0/5 DoubleExponent-PT-010-CTLFireability-00 23933554 t fired, 2454080 attempts, .
57 EF EXCL 23/493 12/32 DoubleExponent-PT-010-CTLFireability-00 3144611 m, 134374 m/sec, 3144611 t fired, .
62 EF FNDP 161/1041 0/5 DoubleExponent-PT-010-CTLFireability-06 53308794 t fired, 5466046 attempts, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 174/1630 0/5 DoubleExponent-PT-010-CTLFireability-14 53173024 t fired, 5452604 attempts, .
55 EF FNDP 174/1630 0/5 DoubleExponent-PT-010-CTLFireability-00 24643067 t fired, 2526689 attempts, .
57 EF EXCL 28/493 14/32 DoubleExponent-PT-010-CTLFireability-00 3819114 m, 134900 m/sec, 3819114 t fired, .
62 EF FNDP 166/1036 0/5 DoubleExponent-PT-010-CTLFireability-06 54997185 t fired, 5639393 attempts, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 179/1625 0/5 DoubleExponent-PT-010-CTLFireability-14 54709386 t fired, 5610011 attempts, .
55 EF FNDP 179/1625 0/5 DoubleExponent-PT-010-CTLFireability-00 25350992 t fired, 2599142 attempts, .
57 EF EXCL 33/493 17/32 DoubleExponent-PT-010-CTLFireability-00 4485832 m, 133343 m/sec, 4485831 t fired, .
62 EF FNDP 171/1031 0/5 DoubleExponent-PT-010-CTLFireability-06 56690916 t fired, 5812992 attempts, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 184/1620 0/5 DoubleExponent-PT-010-CTLFireability-14 56246814 t fired, 5767560 attempts, .
55 EF FNDP 184/1620 0/5 DoubleExponent-PT-010-CTLFireability-00 26057191 t fired, 2671713 attempts, .
57 EF EXCL 38/493 19/32 DoubleExponent-PT-010-CTLFireability-00 5150149 m, 132863 m/sec, 5150148 t fired, .
62 EF FNDP 176/1026 0/5 DoubleExponent-PT-010-CTLFireability-06 58381608 t fired, 5986336 attempts, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 189/1615 0/5 DoubleExponent-PT-010-CTLFireability-14 57779551 t fired, 5924965 attempts, .
55 EF FNDP 189/1615 0/5 DoubleExponent-PT-010-CTLFireability-00 26762666 t fired, 2744183 attempts, .
57 EF EXCL 43/493 21/32 DoubleExponent-PT-010-CTLFireability-00 5811525 m, 132275 m/sec, 5811525 t fired, .
62 EF FNDP 181/1021 0/5 DoubleExponent-PT-010-CTLFireability-06 60066356 t fired, 6158971 attempts, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 194/1610 0/5 DoubleExponent-PT-010-CTLFireability-14 59309434 t fired, 6082004 attempts, .
55 EF FNDP 194/1610 0/5 DoubleExponent-PT-010-CTLFireability-00 27467620 t fired, 2816384 attempts, .
57 EF EXCL 48/493 24/32 DoubleExponent-PT-010-CTLFireability-00 6475691 m, 132833 m/sec, 6475690 t fired, .
62 EF FNDP 186/1016 0/5 DoubleExponent-PT-010-CTLFireability-06 61745745 t fired, 6330991 attempts, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 199/1605 0/5 DoubleExponent-PT-010-CTLFireability-14 60842317 t fired, 6238862 attempts, .
55 EF FNDP 199/1605 0/5 DoubleExponent-PT-010-CTLFireability-00 28173122 t fired, 2888900 attempts, .
57 EF EXCL 53/493 26/32 DoubleExponent-PT-010-CTLFireability-00 7139719 m, 132805 m/sec, 7139719 t fired, .
62 EF FNDP 191/1011 0/5 DoubleExponent-PT-010-CTLFireability-06 63427958 t fired, 6503648 attempts, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 204/1600 0/5 DoubleExponent-PT-010-CTLFireability-14 62348753 t fired, 6393543 attempts, .
55 EF FNDP 204/1600 0/5 DoubleExponent-PT-010-CTLFireability-00 28876941 t fired, 2960809 attempts, .
57 EF EXCL 58/493 29/32 DoubleExponent-PT-010-CTLFireability-00 7801413 m, 132338 m/sec, 7801413 t fired, .
62 EF FNDP 196/1006 0/5 DoubleExponent-PT-010-CTLFireability-06 65102702 t fired, 6675497 attempts, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 2 0 2 0 0 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 209/1595 0/5 DoubleExponent-PT-010-CTLFireability-14 63864025 t fired, 6548977 attempts, .
55 EF FNDP 209/1595 0/5 DoubleExponent-PT-010-CTLFireability-00 29580325 t fired, 3032704 attempts, .
57 EF EXCL 63/493 31/32 DoubleExponent-PT-010-CTLFireability-00 8460219 m, 131761 m/sec, 8460218 t fired, .
62 EF FNDP 201/1001 0/5 DoubleExponent-PT-010-CTLFireability-06 66770631 t fired, 6846788 attempts, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 57 (type EXCL) for DoubleExponent-PT-010-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 214/1590 0/5 DoubleExponent-PT-010-CTLFireability-14 65384946 t fired, 6704951 attempts, .
55 EF FNDP 214/1590 0/5 DoubleExponent-PT-010-CTLFireability-00 30290833 t fired, 3105401 attempts, .
62 EF FNDP 206/996 0/5 DoubleExponent-PT-010-CTLFireability-06 68424479 t fired, 7016071 attempts, .

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 59 (type EXCL) for 35 DoubleExponent-PT-010-CTLFireability-11
lola: time limit : 564 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 219/1585 0/5 DoubleExponent-PT-010-CTLFireability-14 66912951 t fired, 6861688 attempts, .
55 EF FNDP 219/1585 0/5 DoubleExponent-PT-010-CTLFireability-00 30994138 t fired, 3177446 attempts, .
59 LTL EXCL 5/564 6/32 DoubleExponent-PT-010-CTLFireability-11 799203 m, 159840 m/sec, 942189 t fired, .
62 EF FNDP 211/991 0/5 DoubleExponent-PT-010-CTLFireability-06 70096172 t fired, 7187324 attempts, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 224/1580 0/5 DoubleExponent-PT-010-CTLFireability-14 68445234 t fired, 7018797 attempts, .
55 EF FNDP 224/1580 0/5 DoubleExponent-PT-010-CTLFireability-00 31699540 t fired, 3249827 attempts, .
59 LTL EXCL 10/564 11/32 DoubleExponent-PT-010-CTLFireability-11 1583207 m, 156800 m/sec, 1867505 t fired, .
62 EF FNDP 216/986 0/5 DoubleExponent-PT-010-CTLFireability-06 71777486 t fired, 7359626 attempts, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 229/1575 0/5 DoubleExponent-PT-010-CTLFireability-14 69974995 t fired, 7175910 attempts, .
55 EF FNDP 229/1575 0/5 DoubleExponent-PT-010-CTLFireability-00 32404153 t fired, 3322142 attempts, .
59 LTL EXCL 15/564 16/32 DoubleExponent-PT-010-CTLFireability-11 2357939 m, 154946 m/sec, 2781965 t fired, .
62 EF FNDP 221/981 0/5 DoubleExponent-PT-010-CTLFireability-06 73454866 t fired, 7531614 attempts, .

Time elapsed: 230 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 234/1570 0/5 DoubleExponent-PT-010-CTLFireability-14 71505762 t fired, 7332449 attempts, .
55 EF FNDP 234/1570 0/5 DoubleExponent-PT-010-CTLFireability-00 33109183 t fired, 3394348 attempts, .
59 LTL EXCL 20/564 21/32 DoubleExponent-PT-010-CTLFireability-11 3130722 m, 154556 m/sec, 3694171 t fired, .
62 EF FNDP 226/976 0/5 DoubleExponent-PT-010-CTLFireability-06 75138912 t fired, 7704455 attempts, .

Time elapsed: 235 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 239/1565 0/5 DoubleExponent-PT-010-CTLFireability-14 73030773 t fired, 7488725 attempts, .
55 EF FNDP 239/1565 0/5 DoubleExponent-PT-010-CTLFireability-00 33811563 t fired, 3466461 attempts, .
59 LTL EXCL 25/564 26/32 DoubleExponent-PT-010-CTLFireability-11 3896513 m, 153158 m/sec, 4598124 t fired, .
62 EF FNDP 231/971 0/5 DoubleExponent-PT-010-CTLFireability-06 76816451 t fired, 7876595 attempts, .

Time elapsed: 240 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 244/1560 0/5 DoubleExponent-PT-010-CTLFireability-14 74565028 t fired, 7645979 attempts, .
55 EF FNDP 244/1560 0/5 DoubleExponent-PT-010-CTLFireability-00 34515971 t fired, 3538660 attempts, .
59 LTL EXCL 30/564 32/32 DoubleExponent-PT-010-CTLFireability-11 4661493 m, 152996 m/sec, 5501122 t fired, .
62 EF FNDP 236/966 0/5 DoubleExponent-PT-010-CTLFireability-06 78503423 t fired, 8049618 attempts, .

Time elapsed: 245 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 59 (type EXCL) for DoubleExponent-PT-010-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 3 1 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 249/1555 0/5 DoubleExponent-PT-010-CTLFireability-14 76087669 t fired, 7801660 attempts, .
55 EF FNDP 249/1555 0/5 DoubleExponent-PT-010-CTLFireability-00 35239426 t fired, 3613006 attempts, .
62 EF FNDP 241/961 0/5 DoubleExponent-PT-010-CTLFireability-06 80173974 t fired, 8220998 attempts, .

Time elapsed: 250 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 64 (type EXCL) for 19 DoubleExponent-PT-010-CTLFireability-06
lola: time limit : 670 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 2 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 254/1550 0/5 DoubleExponent-PT-010-CTLFireability-14 77622348 t fired, 7959007 attempts, .
55 EF FNDP 254/1550 0/5 DoubleExponent-PT-010-CTLFireability-00 35945578 t fired, 3685604 attempts, .
62 EF FNDP 246/956 0/5 DoubleExponent-PT-010-CTLFireability-06 81861973 t fired, 8394397 attempts, .
64 EF EXCL 5/670 3/32 DoubleExponent-PT-010-CTLFireability-06 624473 m, 124894 m/sec, 624472 t fired, .

Time elapsed: 255 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 3 1 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-06: CONJ 0 2 2 0 3 0 0 0
DoubleExponent-PT-010-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 259/1545 0/5 DoubleExponent-PT-010-CTLFireability-14 79159173 t fired, 8116884 attempts, .
55 EF FNDP 259/1545 0/5 DoubleExponent-PT-010-CTLFireability-00 36650529 t fired, 3757794 attempts, .
62 EF FNDP 251/951 0/5 DoubleExponent-PT-010-CTLFireability-06 83553344 t fired, 8567674 attempts, .
64 EF EXCL 10/670 5/32 DoubleExponent-PT-010-CTLFireability-06 1239099 m, 122925 m/sec, 1239098 t fired, .

Time elapsed: 260 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: FINISHED task # 64 (type EXCL) for DoubleExponent-PT-010-CTLFireability-06
lola: result : true
lola: markings : 1300292
lola: fired transitions : 1300291
lola: time used : 11.000000
lola: memory pages used : 5
lola: CANCELED task # 62 (type FNDP) for DoubleExponent-PT-010-CTLFireability-06 (obsolete)
lola: LAUNCH task # 30 (type EXCL) for 29 DoubleExponent-PT-010-CTLFireability-09
lola: time limit : 834 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 56 (type EQUN) for 0 DoubleExponent-PT-010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 62 (type FNDP) for DoubleExponent-PT-010-CTLFireability-06
lola: result : unknown
lola: fired transitions : 83723947
lola: tried executions : 8585221
lola: time used : 252.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 30 (type EXCL) for DoubleExponent-PT-010-CTLFireability-09
lola: result : false
lola: markings : 10
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 0 DoubleExponent-PT-010-CTLFireability-00
lola: time limit : 1113 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/375/CTLFireability-56.sara.
sara: place or transition ordering is non-deterministic
sara: warning, failure of lp_solve (at job 16)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 3 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 264/3339 0/5 DoubleExponent-PT-010-CTLFireability-14 80884027 t fired, 8293182 attempts, .
54 AGEF EXCL 4/1113 7/32 DoubleExponent-PT-010-CTLFireability-00 1550663 m, 310132 m/sec, 1550662 t fired, .
55 EF FNDP 264/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 37376160 t fired, 3832316 attempts, .
56 EF STEQ 4/1669 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 265 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 3 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 269/3335 0/5 DoubleExponent-PT-010-CTLFireability-14 82630368 t fired, 8472739 attempts, .
54 AGEF EXCL 9/1113 13/32 DoubleExponent-PT-010-CTLFireability-00 3240042 m, 337875 m/sec, 3240042 t fired, .
55 EF FNDP 269/3335 0/5 DoubleExponent-PT-010-CTLFireability-00 38134105 t fired, 3910268 attempts, .
56 EF STEQ 9/1665 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 270 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 3 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 274/3330 0/5 DoubleExponent-PT-010-CTLFireability-14 84373983 t fired, 8651248 attempts, .
54 AGEF EXCL 14/1113 20/32 DoubleExponent-PT-010-CTLFireability-00 4908160 m, 333623 m/sec, 4908160 t fired, .
55 EF FNDP 274/3330 0/5 DoubleExponent-PT-010-CTLFireability-00 38890156 t fired, 3987733 attempts, .
56 EF STEQ 14/1660 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 275 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 3 0 2 0 1 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 279/3325 0/5 DoubleExponent-PT-010-CTLFireability-14 86114245 t fired, 8829684 attempts, .
54 AGEF EXCL 19/1113 27/32 DoubleExponent-PT-010-CTLFireability-00 6566497 m, 331667 m/sec, 6566497 t fired, .
55 EF FNDP 279/3325 0/5 DoubleExponent-PT-010-CTLFireability-00 39648336 t fired, 4065406 attempts, .
56 EF STEQ 19/1655 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 280 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 54 (type EXCL) for DoubleExponent-PT-010-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 284/3320 0/5 DoubleExponent-PT-010-CTLFireability-14 87869345 t fired, 9009494 attempts, .
55 EF FNDP 284/3320 0/5 DoubleExponent-PT-010-CTLFireability-00 40410343 t fired, 4143672 attempts, .
56 EF STEQ 24/1650 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 285 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 11 (type EXCL) for 10 DoubleExponent-PT-010-CTLFireability-02
lola: time limit : 1657 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/1657 7/32 DoubleExponent-PT-010-CTLFireability-02 1510004 m, 302000 m/sec, 1510004 t fired, .
50 EF FNDP 289/3315 0/5 DoubleExponent-PT-010-CTLFireability-14 89594315 t fired, 9186146 attempts, .
55 EF FNDP 289/3315 0/5 DoubleExponent-PT-010-CTLFireability-00 41165750 t fired, 4221101 attempts, .
56 EF STEQ 29/1645 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 290 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/1657 14/32 DoubleExponent-PT-010-CTLFireability-02 2990391 m, 296077 m/sec, 2990390 t fired, .
50 EF FNDP 295/3310 0/5 DoubleExponent-PT-010-CTLFireability-14 91326602 t fired, 9364053 attempts, .
55 EF FNDP 295/3310 0/5 DoubleExponent-PT-010-CTLFireability-00 41922137 t fired, 4298872 attempts, .
56 EF STEQ 35/1640 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 16/1657 20/32 DoubleExponent-PT-010-CTLFireability-02 4446281 m, 291178 m/sec, 4446281 t fired, .
50 EF FNDP 300/3304 0/5 DoubleExponent-PT-010-CTLFireability-14 93078652 t fired, 9543554 attempts, .
55 EF FNDP 300/3304 0/5 DoubleExponent-PT-010-CTLFireability-00 42676542 t fired, 4376282 attempts, .
56 EF STEQ 40/1634 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 21/1657 26/32 DoubleExponent-PT-010-CTLFireability-02 5886717 m, 288087 m/sec, 5886716 t fired, .
50 EF FNDP 305/3299 0/5 DoubleExponent-PT-010-CTLFireability-14 94823795 t fired, 9721975 attempts, .
55 EF FNDP 305/3299 0/5 DoubleExponent-PT-010-CTLFireability-00 43433798 t fired, 4454097 attempts, .
56 EF STEQ 45/1629 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 26/1657 32/32 DoubleExponent-PT-010-CTLFireability-02 7341325 m, 290921 m/sec, 7341325 t fired, .
50 EF FNDP 310/3294 0/5 DoubleExponent-PT-010-CTLFireability-14 96572114 t fired, 9901063 attempts, .
55 EF FNDP 310/3294 0/5 DoubleExponent-PT-010-CTLFireability-00 44190298 t fired, 4531893 attempts, .
56 EF STEQ 50/1624 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: CANCELED task # 11 (type EXCL) for DoubleExponent-PT-010-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 1 2 0 2 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 315/3289 0/5 DoubleExponent-PT-010-CTLFireability-14 98346148 t fired, 10083106 attempts, .
55 EF FNDP 315/3289 0/5 DoubleExponent-PT-010-CTLFireability-00 44972106 t fired, 4611989 attempts, .
56 EF STEQ 55/1619 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 14
lola: LAUNCH task # 33 (type EXCL) for 32 DoubleExponent-PT-010-CTLFireability-10
lola: time limit : 3284 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for DoubleExponent-PT-010-CTLFireability-10
lola: result : true
lola: markings : 8
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type SRCH) for 0 DoubleExponent-PT-010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type SRCH) for DoubleExponent-PT-010-CTLFireability-00
lola: result : unknown
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 320/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 100101272 t fired, 10262949 attempts, .
55 EF FNDP 320/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 45758171 t fired, 4692625 attempts, .
56 EF STEQ 60/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 325/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 101854036 t fired, 10442638 attempts, .
55 EF FNDP 325/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 46543806 t fired, 4773244 attempts, .
56 EF STEQ 65/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 330/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 103622354 t fired, 10623695 attempts, .
55 EF FNDP 330/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 47326416 t fired, 4853467 attempts, .
56 EF STEQ 70/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 335/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 105372921 t fired, 10803231 attempts, .
55 EF FNDP 335/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 48077388 t fired, 4930572 attempts, .
56 EF STEQ 75/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 340/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 107125230 t fired, 10982768 attempts, .
55 EF FNDP 340/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 48862655 t fired, 5011028 attempts, .
56 EF STEQ 80/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 345/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 108871252 t fired, 11161806 attempts, .
55 EF FNDP 345/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 49645902 t fired, 5091243 attempts, .
56 EF STEQ 85/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 350/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 110641572 t fired, 11343321 attempts, .
55 EF FNDP 350/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 50419645 t fired, 5170716 attempts, .
56 EF STEQ 90/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 355/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 112386304 t fired, 11522174 attempts, .
55 EF FNDP 355/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 51201809 t fired, 5251038 attempts, .
56 EF STEQ 95/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 360/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 114174056 t fired, 11705474 attempts, .
55 EF FNDP 360/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 51970075 t fired, 5329705 attempts, .
56 EF STEQ 100/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 365/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 115987409 t fired, 11891590 attempts, .
55 EF FNDP 365/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 52705420 t fired, 5405108 attempts, .
56 EF STEQ 105/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 370/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 117824678 t fired, 12080217 attempts, .
55 EF FNDP 370/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 53469939 t fired, 5483555 attempts, .
56 EF STEQ 110/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 375/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 119575014 t fired, 12259824 attempts, .
55 EF FNDP 375/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 54255827 t fired, 5564331 attempts, .
56 EF STEQ 115/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 380/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 121322337 t fired, 12438441 attempts, .
55 EF FNDP 380/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 55005626 t fired, 5641003 attempts, .
56 EF STEQ 120/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 385/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 123069689 t fired, 12617441 attempts, .
55 EF FNDP 385/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 55788603 t fired, 5721108 attempts, .
56 EF STEQ 125/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 390/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 124816658 t fired, 12796552 attempts, .
55 EF FNDP 390/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 56571427 t fired, 5800986 attempts, .
56 EF STEQ 130/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 395/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 126588195 t fired, 12978350 attempts, .
55 EF FNDP 395/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 57351879 t fired, 5881076 attempts, .
56 EF STEQ 135/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 400/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 128356267 t fired, 13159652 attempts, .
55 EF FNDP 400/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 58131477 t fired, 5960693 attempts, .
56 EF STEQ 140/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 405/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 130205299 t fired, 13349400 attempts, .
55 EF FNDP 405/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 58924238 t fired, 6042293 attempts, .
56 EF STEQ 145/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 410/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 132053541 t fired, 13538773 attempts, .
55 EF FNDP 410/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 59716487 t fired, 6123600 attempts, .
56 EF STEQ 150/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 415/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 133905742 t fired, 13728668 attempts, .
55 EF FNDP 415/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 60508927 t fired, 6204893 attempts, .
56 EF STEQ 155/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 420/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 135757349 t fired, 13918439 attempts, .
55 EF FNDP 420/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 61302199 t fired, 6286540 attempts, .
56 EF STEQ 160/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 425/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 137605358 t fired, 14107926 attempts, .
55 EF FNDP 425/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 62093369 t fired, 6367774 attempts, .
56 EF STEQ 165/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 430/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 139458796 t fired, 14297778 attempts, .
55 EF FNDP 430/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 62886395 t fired, 6449225 attempts, .
56 EF STEQ 170/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 435/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 141306370 t fired, 14487102 attempts, .
55 EF FNDP 435/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 63675326 t fired, 6530343 attempts, .
56 EF STEQ 175/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 440/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 143154659 t fired, 14676284 attempts, .
55 EF FNDP 440/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 64466528 t fired, 6611535 attempts, .
56 EF STEQ 180/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 445/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 144998724 t fired, 14865571 attempts, .
55 EF FNDP 445/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 65256031 t fired, 6692343 attempts, .
56 EF STEQ 185/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 450/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 146845150 t fired, 15054859 attempts, .
55 EF FNDP 450/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 66044300 t fired, 6773078 attempts, .
56 EF STEQ 190/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 451 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 455/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 148671092 t fired, 15241995 attempts, .
55 EF FNDP 455/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 66799281 t fired, 6850476 attempts, .
56 EF STEQ 195/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 456 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 460/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 150416306 t fired, 15420802 attempts, .
55 EF FNDP 460/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 67583856 t fired, 6930896 attempts, .
56 EF STEQ 200/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 461 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 465/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 152165970 t fired, 15600597 attempts, .
55 EF FNDP 465/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 68336957 t fired, 7007907 attempts, .
56 EF STEQ 205/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 466 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 470/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 153949529 t fired, 15783532 attempts, .
55 EF FNDP 470/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 69114011 t fired, 7087659 attempts, .
56 EF STEQ 210/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 471 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 475/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 155706046 t fired, 15963590 attempts, .
55 EF FNDP 475/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 69899589 t fired, 7168238 attempts, .
56 EF STEQ 215/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 476 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 480/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 157492431 t fired, 16146966 attempts, .
55 EF FNDP 480/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 70678327 t fired, 7248139 attempts, .
56 EF STEQ 220/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 481 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 485/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 159233902 t fired, 16325850 attempts, .
55 EF FNDP 485/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 71459805 t fired, 7328153 attempts, .
56 EF STEQ 225/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 486 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 490/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 160986547 t fired, 16505445 attempts, .
55 EF FNDP 490/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 72237789 t fired, 7407865 attempts, .
56 EF STEQ 230/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 491 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 495/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 162740022 t fired, 16685223 attempts, .
55 EF FNDP 495/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 73019942 t fired, 7488076 attempts, .
56 EF STEQ 235/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 496 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 500/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 164494095 t fired, 16865067 attempts, .
55 EF FNDP 500/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 73803164 t fired, 7568225 attempts, .
56 EF STEQ 240/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 501 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 505/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 166254769 t fired, 17045211 attempts, .
55 EF FNDP 505/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 74585995 t fired, 7648276 attempts, .
56 EF STEQ 245/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 506 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 510/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 168005242 t fired, 17224671 attempts, .
55 EF FNDP 510/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 75372250 t fired, 7729036 attempts, .
56 EF STEQ 250/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 511 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 515/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 169763453 t fired, 17405158 attempts, .
55 EF FNDP 515/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 76155787 t fired, 7809601 attempts, .
56 EF STEQ 255/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 516 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 520/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 171518581 t fired, 17585135 attempts, .
55 EF FNDP 520/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 76938711 t fired, 7889996 attempts, .
56 EF STEQ 260/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 521 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 525/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 173280066 t fired, 17765535 attempts, .
55 EF FNDP 525/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 77724544 t fired, 7970543 attempts, .
56 EF STEQ 265/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 526 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 530/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 175023425 t fired, 17944334 attempts, .
55 EF FNDP 530/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 78509589 t fired, 8050960 attempts, .
56 EF STEQ 270/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 531 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 535/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 176782740 t fired, 18124497 attempts, .
55 EF FNDP 535/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 79295669 t fired, 8131586 attempts, .
56 EF STEQ 275/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 536 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 540/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 178548706 t fired, 18305489 attempts, .
55 EF FNDP 540/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 80080234 t fired, 8212224 attempts, .
56 EF STEQ 280/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 541 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 545/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 180302450 t fired, 18485845 attempts, .
55 EF FNDP 545/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 80866301 t fired, 8293010 attempts, .
56 EF STEQ 285/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 546 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 550/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 182059507 t fired, 18665865 attempts, .
55 EF FNDP 550/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 81655425 t fired, 8374020 attempts, .
56 EF STEQ 290/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 551 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 555/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 183810659 t fired, 18845623 attempts, .
55 EF FNDP 555/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 82440901 t fired, 8454464 attempts, .
56 EF STEQ 295/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 556 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 560/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 185566408 t fired, 19025961 attempts, .
55 EF FNDP 560/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 83228382 t fired, 8535126 attempts, .
56 EF STEQ 300/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 561 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 565/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 187318870 t fired, 19205507 attempts, .
55 EF FNDP 565/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 84014560 t fired, 8615703 attempts, .
56 EF STEQ 305/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 570/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 189068357 t fired, 19384778 attempts, .
55 EF FNDP 570/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 84799918 t fired, 8696315 attempts, .
56 EF STEQ 310/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 575/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 190833059 t fired, 19565549 attempts, .
55 EF FNDP 575/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 85581538 t fired, 8776320 attempts, .
56 EF STEQ 315/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 580/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 192597767 t fired, 19746288 attempts, .
55 EF FNDP 580/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 86369676 t fired, 8856876 attempts, .
56 EF STEQ 320/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 585/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 194349580 t fired, 19926068 attempts, .
55 EF FNDP 585/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 87155736 t fired, 8937478 attempts, .
56 EF STEQ 325/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 590/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 196105417 t fired, 20106022 attempts, .
55 EF FNDP 590/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 87943677 t fired, 9018156 attempts, .
56 EF STEQ 330/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 595/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 197865234 t fired, 20286141 attempts, .
55 EF FNDP 595/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 88731018 t fired, 9098881 attempts, .
56 EF STEQ 335/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 600/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 199631723 t fired, 20467454 attempts, .
55 EF FNDP 600/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 89515716 t fired, 9179267 attempts, .
56 EF STEQ 340/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 605/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 201388993 t fired, 20647502 attempts, .
55 EF FNDP 605/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 90301831 t fired, 9260000 attempts, .
56 EF STEQ 345/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 610/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 203147628 t fired, 20827418 attempts, .
55 EF FNDP 610/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 91085616 t fired, 9340491 attempts, .
56 EF STEQ 350/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 615/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 204905152 t fired, 21007848 attempts, .
55 EF FNDP 615/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 91869575 t fired, 9420713 attempts, .
56 EF STEQ 355/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 620/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 206668340 t fired, 21188872 attempts, .
55 EF FNDP 620/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 92651746 t fired, 9500961 attempts, .
56 EF STEQ 360/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 625/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 208429249 t fired, 21369378 attempts, .
55 EF FNDP 625/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 93431911 t fired, 9580859 attempts, .
56 EF STEQ 365/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 630/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 210206020 t fired, 21551532 attempts, .
55 EF FNDP 630/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 94209240 t fired, 9660528 attempts, .
56 EF STEQ 370/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 635/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 211956185 t fired, 21730969 attempts, .
55 EF FNDP 635/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 94993678 t fired, 9740868 attempts, .
56 EF STEQ 375/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 640/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 213714152 t fired, 21911267 attempts, .
55 EF FNDP 640/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 95747513 t fired, 9818184 attempts, .
56 EF STEQ 380/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 645/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 215468821 t fired, 22091302 attempts, .
55 EF FNDP 645/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 96535957 t fired, 9898933 attempts, .
56 EF STEQ 385/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 650/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 217221319 t fired, 22270958 attempts, .
55 EF FNDP 650/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 97323184 t fired, 9979548 attempts, .
56 EF STEQ 390/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 655/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 218964466 t fired, 22449713 attempts, .
55 EF FNDP 655/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 98111642 t fired, 10060308 attempts, .
56 EF STEQ 395/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 660/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 220697863 t fired, 22627400 attempts, .
55 EF FNDP 660/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 98873621 t fired, 10138618 attempts, .
56 EF STEQ 400/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 665/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 222435977 t fired, 22805350 attempts, .
55 EF FNDP 665/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 99666652 t fired, 10220057 attempts, .
56 EF STEQ 405/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 670/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 224238405 t fired, 22990255 attempts, .
55 EF FNDP 670/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 100442174 t fired, 10299395 attempts, .
56 EF STEQ 410/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 675/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 226002961 t fired, 23171043 attempts, .
55 EF FNDP 675/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 101227352 t fired, 10379931 attempts, .
56 EF STEQ 415/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 680/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 227763187 t fired, 23351245 attempts, .
55 EF FNDP 680/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 102021523 t fired, 10461608 attempts, .
56 EF STEQ 420/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 685/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 229524352 t fired, 23531968 attempts, .
55 EF FNDP 685/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 102815086 t fired, 10543055 attempts, .
56 EF STEQ 425/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 690/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 231283734 t fired, 23712377 attempts, .
55 EF FNDP 690/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 103607485 t fired, 10624366 attempts, .
56 EF STEQ 430/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 695/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 233045692 t fired, 23893084 attempts, .
55 EF FNDP 695/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 104401126 t fired, 10705814 attempts, .
56 EF STEQ 435/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 700/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 234804532 t fired, 24073570 attempts, .
55 EF FNDP 700/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 105194735 t fired, 10786985 attempts, .
56 EF STEQ 440/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 705/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 236563593 t fired, 24253813 attempts, .
55 EF FNDP 705/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 105972959 t fired, 10866716 attempts, .
56 EF STEQ 445/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 710/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 238310517 t fired, 24433116 attempts, .
55 EF FNDP 710/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 106763193 t fired, 10947490 attempts, .
56 EF STEQ 450/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 715/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 240069207 t fired, 24613583 attempts, .
55 EF FNDP 715/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 107549275 t fired, 11027966 attempts, .
56 EF STEQ 455/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 720/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 241823170 t fired, 24793728 attempts, .
55 EF FNDP 720/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 108333402 t fired, 11108158 attempts, .
56 EF STEQ 460/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 725/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 243585529 t fired, 24974325 attempts, .
55 EF FNDP 725/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 109117940 t fired, 11188539 attempts, .
56 EF STEQ 465/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 730/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 245352024 t fired, 25155422 attempts, .
55 EF FNDP 730/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 109871370 t fired, 11265502 attempts, .
56 EF STEQ 470/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 731 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 735/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 247149835 t fired, 25339720 attempts, .
55 EF FNDP 735/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 110646451 t fired, 11344984 attempts, .
56 EF STEQ 475/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 736 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 740/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 248906311 t fired, 25519690 attempts, .
55 EF FNDP 740/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 111432392 t fired, 11425746 attempts, .
56 EF STEQ 480/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 745/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 250657461 t fired, 25699430 attempts, .
55 EF FNDP 745/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 112215527 t fired, 11506145 attempts, .
56 EF STEQ 485/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 746 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 750/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 252399676 t fired, 25878143 attempts, .
55 EF FNDP 750/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 113002029 t fired, 11586933 attempts, .
56 EF STEQ 490/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 751 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 755/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 254150579 t fired, 26057803 attempts, .
55 EF FNDP 755/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 113785285 t fired, 11667146 attempts, .
56 EF STEQ 495/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 756 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 760/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 255897835 t fired, 26236893 attempts, .
55 EF FNDP 760/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 114572059 t fired, 11747639 attempts, .
56 EF STEQ 500/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 761 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 765/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 257641112 t fired, 26415529 attempts, .
55 EF FNDP 765/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 115360271 t fired, 11828537 attempts, .
56 EF STEQ 505/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 766 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 770/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 259411443 t fired, 26597312 attempts, .
55 EF FNDP 770/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 116148144 t fired, 11909159 attempts, .
56 EF STEQ 510/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 771 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 775/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 261252217 t fired, 26786574 attempts, .
55 EF FNDP 775/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 116940107 t fired, 11990122 attempts, .
56 EF STEQ 515/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 776 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 780/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 263068771 t fired, 26972713 attempts, .
55 EF FNDP 780/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 117728833 t fired, 12070912 attempts, .
56 EF STEQ 520/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 781 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 785/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 264837793 t fired, 27154060 attempts, .
55 EF FNDP 785/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 118510496 t fired, 12151141 attempts, .
56 EF STEQ 525/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 786 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 790/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 266607531 t fired, 27335484 attempts, .
55 EF FNDP 790/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 119289124 t fired, 12230764 attempts, .
56 EF STEQ 530/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 791 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 795/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 268363903 t fired, 27515711 attempts, .
55 EF FNDP 795/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 120056614 t fired, 12309344 attempts, .
56 EF STEQ 535/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 796 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 800/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 270116628 t fired, 27695157 attempts, .
55 EF FNDP 800/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 120835260 t fired, 12389115 attempts, .
56 EF STEQ 540/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 801 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 805/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 271868621 t fired, 27875386 attempts, .
55 EF FNDP 805/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 121614701 t fired, 12469157 attempts, .
56 EF STEQ 545/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 806 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 810/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 273615997 t fired, 28054639 attempts, .
55 EF FNDP 810/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 122390767 t fired, 12548881 attempts, .
56 EF STEQ 550/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 811 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 815/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 275367608 t fired, 28234208 attempts, .
55 EF FNDP 815/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 123168815 t fired, 12628913 attempts, .
56 EF STEQ 555/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 816 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 820/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 277121509 t fired, 28413714 attempts, .
55 EF FNDP 820/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 123948940 t fired, 12708936 attempts, .
56 EF STEQ 560/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 821 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 825/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 278874106 t fired, 28593803 attempts, .
55 EF FNDP 825/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 124728727 t fired, 12788929 attempts, .
56 EF STEQ 565/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 826 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 830/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 280612336 t fired, 28771597 attempts, .
55 EF FNDP 830/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 125505671 t fired, 12868576 attempts, .
56 EF STEQ 570/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 831 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 835/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 282352198 t fired, 28949801 attempts, .
55 EF FNDP 835/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 126284186 t fired, 12948276 attempts, .
56 EF STEQ 575/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 836 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 840/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 284113173 t fired, 29130181 attempts, .
55 EF FNDP 840/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 127053442 t fired, 13026944 attempts, .
56 EF STEQ 580/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 841 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 845/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 285877620 t fired, 29310835 attempts, .
55 EF FNDP 845/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 127825906 t fired, 13106178 attempts, .
56 EF STEQ 585/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 846 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 850/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 287659079 t fired, 29493579 attempts, .
55 EF FNDP 850/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 128592967 t fired, 13184921 attempts, .
56 EF STEQ 590/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 851 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 855/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 289439397 t fired, 29676121 attempts, .
55 EF FNDP 855/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 129363825 t fired, 13264112 attempts, .
56 EF STEQ 595/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 856 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 860/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 291189725 t fired, 29855132 attempts, .
55 EF FNDP 860/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 130139366 t fired, 13343455 attempts, .
56 EF STEQ 600/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 861 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 865/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 292951967 t fired, 30036057 attempts, .
55 EF FNDP 865/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 130914047 t fired, 13422858 attempts, .
56 EF STEQ 605/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 866 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 870/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 294706261 t fired, 30215932 attempts, .
55 EF FNDP 870/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 131690664 t fired, 13502263 attempts, .
56 EF STEQ 610/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 871 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 875/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 296465532 t fired, 30395710 attempts, .
55 EF FNDP 875/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 132463357 t fired, 13581660 attempts, .
56 EF STEQ 615/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 876 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 880/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 298230045 t fired, 30576674 attempts, .
55 EF FNDP 880/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 133223276 t fired, 13659628 attempts, .
56 EF STEQ 620/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 881 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 885/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 299980494 t fired, 30756010 attempts, .
55 EF FNDP 885/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 133980701 t fired, 13737006 attempts, .
56 EF STEQ 625/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 886 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 890/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 301725324 t fired, 30934974 attempts, .
55 EF FNDP 890/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 134729922 t fired, 13813604 attempts, .
56 EF STEQ 630/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 891 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 895/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 303472352 t fired, 31114014 attempts, .
55 EF FNDP 895/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 135476653 t fired, 13890031 attempts, .
56 EF STEQ 635/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 896 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 900/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 305221060 t fired, 31293068 attempts, .
55 EF FNDP 900/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 136255383 t fired, 13969947 attempts, .
56 EF STEQ 640/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 901 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 905/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 306985374 t fired, 31473969 attempts, .
55 EF FNDP 905/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 137029088 t fired, 14049307 attempts, .
56 EF STEQ 645/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 906 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 910/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 308747744 t fired, 31654752 attempts, .
55 EF FNDP 910/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 137802017 t fired, 14128743 attempts, .
56 EF STEQ 650/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 911 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 915/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 310490296 t fired, 31833350 attempts, .
55 EF FNDP 915/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 138550326 t fired, 14205522 attempts, .
56 EF STEQ 655/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 916 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 920/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 312274277 t fired, 32016267 attempts, .
55 EF FNDP 920/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 139317863 t fired, 14284337 attempts, .
56 EF STEQ 660/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 921 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 925/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 314061355 t fired, 32199311 attempts, .
55 EF FNDP 925/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 140088191 t fired, 14363384 attempts, .
56 EF STEQ 665/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 926 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 930/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 315815438 t fired, 32379315 attempts, .
55 EF FNDP 930/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 140865301 t fired, 14443158 attempts, .
56 EF STEQ 670/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 931 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 935/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 317564103 t fired, 32558729 attempts, .
55 EF FNDP 935/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 141641865 t fired, 14522782 attempts, .
56 EF STEQ 675/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 936 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 940/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 319330852 t fired, 32739761 attempts, .
55 EF FNDP 940/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 142418826 t fired, 14602457 attempts, .
56 EF STEQ 680/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 941 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 945/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 321069626 t fired, 32918148 attempts, .
55 EF FNDP 945/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 143193041 t fired, 14681832 attempts, .
56 EF STEQ 685/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 946 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 950/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 322809398 t fired, 33096721 attempts, .
55 EF FNDP 950/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 143970479 t fired, 14761617 attempts, .
56 EF STEQ 690/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 951 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 955/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 324592222 t fired, 33279476 attempts, .
55 EF FNDP 955/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 144712180 t fired, 14837807 attempts, .
56 EF STEQ 695/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 956 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 960/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 326339186 t fired, 33458554 attempts, .
55 EF FNDP 960/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 145491740 t fired, 14917717 attempts, .
56 EF STEQ 700/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 961 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 965/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 328080440 t fired, 33636649 attempts, .
55 EF FNDP 965/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 146270600 t fired, 14997704 attempts, .
56 EF STEQ 705/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 966 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 970/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 329842628 t fired, 33817185 attempts, .
55 EF FNDP 970/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 147046143 t fired, 15077242 attempts, .
56 EF STEQ 710/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 971 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 975/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 331603346 t fired, 33997736 attempts, .
55 EF FNDP 975/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 147823120 t fired, 15157007 attempts, .
56 EF STEQ 715/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 976 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 980/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 333353445 t fired, 34177732 attempts, .
55 EF FNDP 980/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 148604422 t fired, 15237016 attempts, .
56 EF STEQ 720/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 981 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 985/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 335130431 t fired, 34360142 attempts, .
55 EF FNDP 985/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 149374015 t fired, 15315935 attempts, .
56 EF STEQ 725/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 986 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 990/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 336879540 t fired, 34539355 attempts, .
55 EF FNDP 990/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 150132760 t fired, 15393743 attempts, .
56 EF STEQ 730/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 991 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 995/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 338636374 t fired, 34719619 attempts, .
55 EF FNDP 995/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 150878444 t fired, 15470098 attempts, .
56 EF STEQ 735/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 996 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1000/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 340389719 t fired, 34899313 attempts, .
55 EF FNDP 1000/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 151626449 t fired, 15546705 attempts, .
56 EF STEQ 740/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1001 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1005/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 342159288 t fired, 35080846 attempts, .
55 EF FNDP 1005/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 152409088 t fired, 15627077 attempts, .
56 EF STEQ 745/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1006 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1010/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 343931186 t fired, 35262335 attempts, .
55 EF FNDP 1010/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 153151014 t fired, 15703236 attempts, .
56 EF STEQ 750/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1011 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1015/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 345711811 t fired, 35445067 attempts, .
55 EF FNDP 1015/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 153924471 t fired, 15782603 attempts, .
56 EF STEQ 755/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1016 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1020/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 347456902 t fired, 35624021 attempts, .
55 EF FNDP 1020/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 154714162 t fired, 15863626 attempts, .
56 EF STEQ 760/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1021 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1025/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 349210578 t fired, 35803644 attempts, .
55 EF FNDP 1025/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 155496294 t fired, 15944004 attempts, .
56 EF STEQ 765/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1026 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1030/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 350963449 t fired, 35983197 attempts, .
55 EF FNDP 1030/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 156278277 t fired, 16023934 attempts, .
56 EF STEQ 770/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1031 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1035/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 352729200 t fired, 36164586 attempts, .
55 EF FNDP 1035/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 157057849 t fired, 16103885 attempts, .
56 EF STEQ 775/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1036 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1040/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 354489802 t fired, 36344927 attempts, .
55 EF FNDP 1040/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 157836040 t fired, 16183658 attempts, .
56 EF STEQ 780/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1041 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1045/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 356282820 t fired, 36528902 attempts, .
55 EF FNDP 1045/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 158608600 t fired, 16262841 attempts, .
56 EF STEQ 785/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1046 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1050/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 358035326 t fired, 36708492 attempts, .
55 EF FNDP 1050/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 159387984 t fired, 16342736 attempts, .
56 EF STEQ 790/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1051 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1055/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 359784301 t fired, 36887928 attempts, .
55 EF FNDP 1055/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 160167728 t fired, 16422795 attempts, .
56 EF STEQ 795/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1056 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1060/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 361535021 t fired, 37067187 attempts, .
55 EF FNDP 1060/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 160950751 t fired, 16502950 attempts, .
56 EF STEQ 800/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1061 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1065/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 363288901 t fired, 37246992 attempts, .
55 EF FNDP 1065/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 161733849 t fired, 16583153 attempts, .
56 EF STEQ 805/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1066 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1070/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 365041474 t fired, 37426378 attempts, .
55 EF FNDP 1070/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 162515502 t fired, 16663487 attempts, .
56 EF STEQ 810/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1071 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1075/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 366806252 t fired, 37607608 attempts, .
55 EF FNDP 1075/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 163291397 t fired, 16742850 attempts, .
56 EF STEQ 815/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1076 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1080/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 368572910 t fired, 37788726 attempts, .
55 EF FNDP 1080/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 164067579 t fired, 16822260 attempts, .
56 EF STEQ 820/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1081 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1085/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 370343175 t fired, 37970362 attempts, .
55 EF FNDP 1085/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 164843854 t fired, 16901969 attempts, .
56 EF STEQ 825/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1086 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1090/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 372106991 t fired, 38151257 attempts, .
55 EF FNDP 1090/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 165623072 t fired, 16982010 attempts, .
56 EF STEQ 830/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1091 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1095/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 373853721 t fired, 38330371 attempts, .
55 EF FNDP 1095/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 166403799 t fired, 17062076 attempts, .
56 EF STEQ 835/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1096 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1100/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 375599610 t fired, 38509425 attempts, .
55 EF FNDP 1100/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 167185431 t fired, 17142452 attempts, .
56 EF STEQ 840/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1101 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1105/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 377360164 t fired, 38690116 attempts, .
55 EF FNDP 1105/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 167962804 t fired, 17222147 attempts, .
56 EF STEQ 845/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1106 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1110/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 379119748 t fired, 38870643 attempts, .
55 EF FNDP 1110/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 168740383 t fired, 17302201 attempts, .
56 EF STEQ 850/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1111 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1115/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 380883648 t fired, 39051356 attempts, .
55 EF FNDP 1115/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 169517291 t fired, 17381807 attempts, .
56 EF STEQ 855/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1116 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1120/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 382626930 t fired, 39230044 attempts, .
55 EF FNDP 1120/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 170296899 t fired, 17461698 attempts, .
56 EF STEQ 860/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1121 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1125/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 384403528 t fired, 39412404 attempts, .
55 EF FNDP 1125/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 171068400 t fired, 17540619 attempts, .
56 EF STEQ 865/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1126 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1130/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 386178275 t fired, 39594381 attempts, .
55 EF FNDP 1130/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 171847617 t fired, 17620368 attempts, .
56 EF STEQ 870/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1131 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1135/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 387968726 t fired, 39778123 attempts, .
55 EF FNDP 1135/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 172618469 t fired, 17699636 attempts, .
56 EF STEQ 875/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1136 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1140/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 389736330 t fired, 39959719 attempts, .
55 EF FNDP 1140/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 173392196 t fired, 17779146 attempts, .
56 EF STEQ 880/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1141 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1145/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 391492923 t fired, 40139939 attempts, .
55 EF FNDP 1145/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 174172353 t fired, 17859160 attempts, .
56 EF STEQ 885/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1146 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1150/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 393263988 t fired, 40321509 attempts, .
55 EF FNDP 1150/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 174948463 t fired, 17938673 attempts, .
56 EF STEQ 890/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1151 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1155/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 395042848 t fired, 40504099 attempts, .
55 EF FNDP 1155/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 175719871 t fired, 18017503 attempts, .
56 EF STEQ 895/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1156 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1160/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 396821195 t fired, 40686745 attempts, .
55 EF FNDP 1160/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 176493566 t fired, 18096948 attempts, .
56 EF STEQ 900/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1161 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1165/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 398570292 t fired, 40866179 attempts, .
55 EF FNDP 1165/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 177275450 t fired, 18177278 attempts, .
56 EF STEQ 905/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1166 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1170/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 400307108 t fired, 41044584 attempts, .
55 EF FNDP 1170/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 178054372 t fired, 18257388 attempts, .
56 EF STEQ 910/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1171 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1175/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 402126579 t fired, 41231573 attempts, .
55 EF FNDP 1175/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 178817475 t fired, 18335599 attempts, .
56 EF STEQ 915/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1176 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1180/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 403965013 t fired, 41420317 attempts, .
55 EF FNDP 1180/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 179572618 t fired, 18413178 attempts, .
56 EF STEQ 920/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1181 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1185/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 405804118 t fired, 41608485 attempts, .
55 EF FNDP 1185/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 180328063 t fired, 18490488 attempts, .
56 EF STEQ 925/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1186 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1190/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 407641237 t fired, 41797297 attempts, .
55 EF FNDP 1190/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 181085311 t fired, 18568078 attempts, .
56 EF STEQ 930/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1191 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1195/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 409479209 t fired, 41986214 attempts, .
55 EF FNDP 1195/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 181843289 t fired, 18645639 attempts, .
56 EF STEQ 935/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1196 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1200/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 411316772 t fired, 42175048 attempts, .
55 EF FNDP 1200/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 182596757 t fired, 18722984 attempts, .
56 EF STEQ 940/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1201 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1205/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 413154344 t fired, 42363624 attempts, .
55 EF FNDP 1205/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 183354978 t fired, 18800775 attempts, .
56 EF STEQ 945/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1206 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1210/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 414986023 t fired, 42551591 attempts, .
55 EF FNDP 1210/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 184112874 t fired, 18878356 attempts, .
56 EF STEQ 950/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1211 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1215/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 416743225 t fired, 42731652 attempts, .
55 EF FNDP 1215/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 184890183 t fired, 18958031 attempts, .
56 EF STEQ 955/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1216 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1220/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 418477324 t fired, 42909621 attempts, .
55 EF FNDP 1220/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 185666267 t fired, 19037512 attempts, .
56 EF STEQ 960/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1221 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1225/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 420217133 t fired, 43088207 attempts, .
55 EF FNDP 1225/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 186446393 t fired, 19117383 attempts, .
56 EF STEQ 965/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1226 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1230/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 421977066 t fired, 43268649 attempts, .
55 EF FNDP 1230/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 187219917 t fired, 19196627 attempts, .
56 EF STEQ 970/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1231 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1235/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 423743631 t fired, 43449501 attempts, .
55 EF FNDP 1235/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 187992158 t fired, 19275776 attempts, .
56 EF STEQ 975/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1236 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1240/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 425481884 t fired, 43627594 attempts, .
55 EF FNDP 1240/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 188749892 t fired, 19353498 attempts, .
56 EF STEQ 980/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1241 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1245/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 427234547 t fired, 43807421 attempts, .
55 EF FNDP 1245/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 189521162 t fired, 19432495 attempts, .
56 EF STEQ 985/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1246 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1250/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 428994696 t fired, 43987954 attempts, .
55 EF FNDP 1250/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 190299470 t fired, 19512056 attempts, .
56 EF STEQ 990/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1251 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1255/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 430786822 t fired, 44171097 attempts, .
55 EF FNDP 1255/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 191084798 t fired, 19592726 attempts, .
56 EF STEQ 995/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1256 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1260/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 432622817 t fired, 44359710 attempts, .
55 EF FNDP 1260/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 191876025 t fired, 19673685 attempts, .
56 EF STEQ 1000/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1261 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1265/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 434386462 t fired, 44540390 attempts, .
55 EF FNDP 1265/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 192654183 t fired, 19753684 attempts, .
56 EF STEQ 1005/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1266 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1270/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 436161732 t fired, 44722149 attempts, .
55 EF FNDP 1270/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 193428569 t fired, 19833182 attempts, .
56 EF STEQ 1010/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1271 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1275/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 437913436 t fired, 44901855 attempts, .
55 EF FNDP 1275/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 194208176 t fired, 19913097 attempts, .
56 EF STEQ 1015/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1276 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1280/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 439661379 t fired, 45081401 attempts, .
55 EF FNDP 1280/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 194955937 t fired, 19989819 attempts, .
56 EF STEQ 1020/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1281 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1285/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 441407107 t fired, 45260376 attempts, .
55 EF FNDP 1285/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 195736272 t fired, 20069983 attempts, .
56 EF STEQ 1025/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1286 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1290/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 443160142 t fired, 45440371 attempts, .
55 EF FNDP 1290/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 196515562 t fired, 20149862 attempts, .
56 EF STEQ 1030/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1291 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1295/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 444949508 t fired, 45623656 attempts, .
55 EF FNDP 1295/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 197295358 t fired, 20229803 attempts, .
56 EF STEQ 1035/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1296 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1300/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 446725881 t fired, 45805801 attempts, .
55 EF FNDP 1300/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 198066963 t fired, 20309130 attempts, .
56 EF STEQ 1040/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1301 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1305/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 448541685 t fired, 45991990 attempts, .
55 EF FNDP 1305/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 198827695 t fired, 20387042 attempts, .
56 EF STEQ 1045/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1306 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1310/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 450380307 t fired, 46180749 attempts, .
55 EF FNDP 1310/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 199586215 t fired, 20464852 attempts, .
56 EF STEQ 1050/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1311 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1315/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 452217677 t fired, 46369628 attempts, .
55 EF FNDP 1315/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 200343656 t fired, 20542328 attempts, .
56 EF STEQ 1055/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1316 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1320/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 454054808 t fired, 46557985 attempts, .
55 EF FNDP 1320/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 201101150 t fired, 20619936 attempts, .
56 EF STEQ 1060/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1321 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1325/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 455893028 t fired, 46746380 attempts, .
55 EF FNDP 1325/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 201859716 t fired, 20697912 attempts, .
56 EF STEQ 1065/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1326 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1330/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 457718075 t fired, 46933835 attempts, .
55 EF FNDP 1330/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 202621774 t fired, 20776047 attempts, .
56 EF STEQ 1070/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1331 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1335/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 459542568 t fired, 47121015 attempts, .
55 EF FNDP 1335/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 203382465 t fired, 20854084 attempts, .
56 EF STEQ 1075/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1336 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1340/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 461317717 t fired, 47303091 attempts, .
55 EF FNDP 1340/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 204153421 t fired, 20933067 attempts, .
56 EF STEQ 1080/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1341 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1345/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 463064452 t fired, 47482255 attempts, .
55 EF FNDP 1345/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 204899350 t fired, 21009435 attempts, .
56 EF STEQ 1085/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1346 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1350/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 464826628 t fired, 47662880 attempts, .
55 EF FNDP 1350/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 205677093 t fired, 21088989 attempts, .
56 EF STEQ 1090/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1351 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1355/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 466588684 t fired, 47843519 attempts, .
55 EF FNDP 1355/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 206455675 t fired, 21168682 attempts, .
56 EF STEQ 1095/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1356 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1360/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 468348672 t fired, 48024064 attempts, .
55 EF FNDP 1360/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 207234848 t fired, 21248675 attempts, .
56 EF STEQ 1100/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1361 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1365/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 470107200 t fired, 48204278 attempts, .
55 EF FNDP 1365/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 208014350 t fired, 21328572 attempts, .
56 EF STEQ 1105/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1366 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1370/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 471869492 t fired, 48384741 attempts, .
55 EF FNDP 1370/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 208794249 t fired, 21408653 attempts, .
56 EF STEQ 1110/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1371 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1375/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 473634533 t fired, 48565576 attempts, .
55 EF FNDP 1375/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 209542963 t fired, 21485537 attempts, .
56 EF STEQ 1115/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1376 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1380/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 475412582 t fired, 48747851 attempts, .
55 EF FNDP 1380/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 210297482 t fired, 21562764 attempts, .
56 EF STEQ 1120/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1381 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1385/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 477161368 t fired, 48927535 attempts, .
55 EF FNDP 1385/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 211074689 t fired, 21642562 attempts, .
56 EF STEQ 1125/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1386 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1390/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 478913972 t fired, 49107043 attempts, .
55 EF FNDP 1390/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 211821900 t fired, 21719293 attempts, .
56 EF STEQ 1130/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1391 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1395/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 480670926 t fired, 49287586 attempts, .
55 EF FNDP 1395/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 212602067 t fired, 21799297 attempts, .
56 EF STEQ 1135/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1396 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1400/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 482451618 t fired, 49470198 attempts, .
55 EF FNDP 1400/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 213376012 t fired, 21878630 attempts, .
56 EF STEQ 1140/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1401 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1405/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 484282262 t fired, 49658188 attempts, .
55 EF FNDP 1405/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 214137099 t fired, 21956404 attempts, .
56 EF STEQ 1145/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1406 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1410/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 486118574 t fired, 49846713 attempts, .
55 EF FNDP 1410/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 214897006 t fired, 22034233 attempts, .
56 EF STEQ 1150/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1411 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1415/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 487959689 t fired, 50035487 attempts, .
55 EF FNDP 1415/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 215655234 t fired, 22111837 attempts, .
56 EF STEQ 1155/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1416 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1420/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 489767099 t fired, 50220506 attempts, .
55 EF FNDP 1420/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 216421650 t fired, 22190564 attempts, .
56 EF STEQ 1160/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1421 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1425/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 491598004 t fired, 50408333 attempts, .
55 EF FNDP 1425/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 217182386 t fired, 22268657 attempts, .
56 EF STEQ 1165/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1426 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1430/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 493418253 t fired, 50594988 attempts, .
55 EF FNDP 1430/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 217944586 t fired, 22346621 attempts, .
56 EF STEQ 1170/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1431 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1435/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 495249479 t fired, 50782854 attempts, .
55 EF FNDP 1435/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 218704788 t fired, 22424571 attempts, .
56 EF STEQ 1175/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1436 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1440/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 497089369 t fired, 50971653 attempts, .
55 EF FNDP 1440/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 219462983 t fired, 22502132 attempts, .
56 EF STEQ 1180/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1441 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1445/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 498881727 t fired, 51155252 attempts, .
55 EF FNDP 1445/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 220230917 t fired, 22581130 attempts, .
56 EF STEQ 1185/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1446 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1450/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 500678331 t fired, 51339402 attempts, .
55 EF FNDP 1450/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 220973896 t fired, 22657327 attempts, .
56 EF STEQ 1190/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1451 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1455/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 502505862 t fired, 51526832 attempts, .
55 EF FNDP 1455/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 221734378 t fired, 22735371 attempts, .
56 EF STEQ 1195/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1456 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1460/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 504336659 t fired, 51714754 attempts, .
55 EF FNDP 1460/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 222496010 t fired, 22813549 attempts, .
56 EF STEQ 1200/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1461 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1465/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 506162131 t fired, 51901854 attempts, .
55 EF FNDP 1465/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 223257973 t fired, 22891800 attempts, .
56 EF STEQ 1205/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1466 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1470/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 507994452 t fired, 52089569 attempts, .
55 EF FNDP 1470/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 224018443 t fired, 22969996 attempts, .
56 EF STEQ 1210/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1471 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1475/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 509823542 t fired, 52277605 attempts, .
55 EF FNDP 1475/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 224779360 t fired, 23048177 attempts, .
56 EF STEQ 1215/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1476 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1480/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 511610235 t fired, 52461132 attempts, .
55 EF FNDP 1480/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 225565626 t fired, 23129109 attempts, .
56 EF STEQ 1220/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1481 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1485/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 513362541 t fired, 52640691 attempts, .
55 EF FNDP 1485/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 226313234 t fired, 23205611 attempts, .
56 EF STEQ 1225/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1486 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1490/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 515108618 t fired, 52819655 attempts, .
55 EF FNDP 1490/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 227091222 t fired, 23285200 attempts, .
56 EF STEQ 1230/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1491 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1495/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 516866782 t fired, 53000117 attempts, .
55 EF FNDP 1495/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 227870348 t fired, 23364963 attempts, .
56 EF STEQ 1235/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1496 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1500/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 518697286 t fired, 53187465 attempts, .
55 EF FNDP 1500/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 228630483 t fired, 23442945 attempts, .
56 EF STEQ 1240/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1501 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1505/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 520527356 t fired, 53375266 attempts, .
55 EF FNDP 1505/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 229391239 t fired, 23521129 attempts, .
56 EF STEQ 1245/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1506 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1510/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 522358277 t fired, 53563056 attempts, .
55 EF FNDP 1510/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 230151702 t fired, 23599023 attempts, .
56 EF STEQ 1250/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1511 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1515/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 524181975 t fired, 53750302 attempts, .
55 EF FNDP 1515/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 230914077 t fired, 23677336 attempts, .
56 EF STEQ 1255/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1516 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1520/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 525987666 t fired, 53935489 attempts, .
55 EF FNDP 1520/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 231680685 t fired, 23756073 attempts, .
56 EF STEQ 1260/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1521 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1525/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 527801909 t fired, 54121825 attempts, .
55 EF FNDP 1525/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 232446064 t fired, 23834692 attempts, .
56 EF STEQ 1265/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1526 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1530/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 529618977 t fired, 54307998 attempts, .
55 EF FNDP 1530/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 233210432 t fired, 23913103 attempts, .
56 EF STEQ 1270/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1531 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1535/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 531457953 t fired, 54496506 attempts, .
55 EF FNDP 1535/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 233969803 t fired, 23991026 attempts, .
56 EF STEQ 1275/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1536 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1540/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 533293488 t fired, 54684727 attempts, .
55 EF FNDP 1540/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 234725497 t fired, 24068340 attempts, .
56 EF STEQ 1280/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1541 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1545/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 535117887 t fired, 54871982 attempts, .
55 EF FNDP 1545/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 235483643 t fired, 24146119 attempts, .
56 EF STEQ 1285/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1546 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1550/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 536926796 t fired, 55057552 attempts, .
55 EF FNDP 1550/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 236245082 t fired, 24224312 attempts, .
56 EF STEQ 1290/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1551 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1555/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 538752619 t fired, 55244894 attempts, .
55 EF FNDP 1555/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 237002868 t fired, 24301876 attempts, .
56 EF STEQ 1295/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1556 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1560/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 540571278 t fired, 55431496 attempts, .
55 EF FNDP 1560/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 237761381 t fired, 24379839 attempts, .
56 EF STEQ 1300/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1561 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1565/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 542323087 t fired, 55611428 attempts, .
55 EF FNDP 1565/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 238535740 t fired, 24459257 attempts, .
56 EF STEQ 1305/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1566 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1570/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 544075926 t fired, 55791315 attempts, .
55 EF FNDP 1570/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 239286306 t fired, 24536080 attempts, .
56 EF STEQ 1310/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1571 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1575/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 545829057 t fired, 55971215 attempts, .
55 EF FNDP 1575/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 240066761 t fired, 24615884 attempts, .
56 EF STEQ 1315/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1576 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1580/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 547605722 t fired, 56153522 attempts, .
55 EF FNDP 1580/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 240809937 t fired, 24692105 attempts, .
56 EF STEQ 1320/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1581 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1585/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 549359234 t fired, 56333364 attempts, .
55 EF FNDP 1585/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 241590472 t fired, 24772169 attempts, .
56 EF STEQ 1325/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1586 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1590/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 551125966 t fired, 56514148 attempts, .
55 EF FNDP 1590/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 242366806 t fired, 24851892 attempts, .
56 EF STEQ 1330/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1591 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1595/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 552899589 t fired, 56695498 attempts, .
55 EF FNDP 1595/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 243140697 t fired, 24931054 attempts, .
56 EF STEQ 1335/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1596 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1600/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 554656241 t fired, 56875888 attempts, .
55 EF FNDP 1600/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 243920437 t fired, 25011114 attempts, .
56 EF STEQ 1340/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1601 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1605/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 556400144 t fired, 57055030 attempts, .
55 EF FNDP 1605/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 244700680 t fired, 25091024 attempts, .
56 EF STEQ 1345/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1606 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1610/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 558177882 t fired, 57237608 attempts, .
55 EF FNDP 1610/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 245475952 t fired, 25170994 attempts, .
56 EF STEQ 1350/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1611 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1615/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 559927667 t fired, 57417101 attempts, .
55 EF FNDP 1615/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 246258010 t fired, 25251095 attempts, .
56 EF STEQ 1355/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1616 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1620/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 561747833 t fired, 57603763 attempts, .
55 EF FNDP 1620/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 247021732 t fired, 25329317 attempts, .
56 EF STEQ 1360/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1621 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1625/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 563547352 t fired, 57788493 attempts, .
55 EF FNDP 1625/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 247795488 t fired, 25408802 attempts, .
56 EF STEQ 1365/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1626 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1630/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 565298992 t fired, 57968319 attempts, .
55 EF FNDP 1630/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 248579595 t fired, 25489264 attempts, .
56 EF STEQ 1370/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1631 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1635/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 567051650 t fired, 58148134 attempts, .
55 EF FNDP 1635/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 249355199 t fired, 25568808 attempts, .
56 EF STEQ 1375/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1636 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1640/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 568880599 t fired, 58335797 attempts, .
55 EF FNDP 1640/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 250109810 t fired, 25645935 attempts, .
56 EF STEQ 1380/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1641 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1645/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 570623031 t fired, 58514685 attempts, .
55 EF FNDP 1645/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 250886376 t fired, 25725745 attempts, .
56 EF STEQ 1385/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1646 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1650/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 572367561 t fired, 58693570 attempts, .
55 EF FNDP 1650/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 251608786 t fired, 25800026 attempts, .
56 EF STEQ 1390/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1651 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1655/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 574110710 t fired, 58872256 attempts, .
55 EF FNDP 1655/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 252391501 t fired, 25880000 attempts, .
56 EF STEQ 1395/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1656 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1660/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 575852602 t fired, 59050570 attempts, .
55 EF FNDP 1660/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 253174212 t fired, 25960344 attempts, .
56 EF STEQ 1400/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1661 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1665/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 577585572 t fired, 59228154 attempts, .
55 EF FNDP 1665/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 253957791 t fired, 26040655 attempts, .
56 EF STEQ 1405/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1666 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1670/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 579326890 t fired, 59406986 attempts, .
55 EF FNDP 1670/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 254740788 t fired, 26120950 attempts, .
56 EF STEQ 1410/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1671 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1675/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 581067793 t fired, 59585509 attempts, .
55 EF FNDP 1675/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 255524186 t fired, 26201442 attempts, .
56 EF STEQ 1415/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1676 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1680/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 582807607 t fired, 59764002 attempts, .
55 EF FNDP 1680/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 256308561 t fired, 26281909 attempts, .
56 EF STEQ 1420/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1681 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1685/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 584547300 t fired, 59942661 attempts, .
55 EF FNDP 1685/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 257091472 t fired, 26362081 attempts, .
56 EF STEQ 1425/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1686 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1690/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 586270396 t fired, 60119756 attempts, .
55 EF FNDP 1690/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 257873478 t fired, 26442062 attempts, .
56 EF STEQ 1430/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1691 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1695/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 588025355 t fired, 60300008 attempts, .
55 EF FNDP 1695/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 258648557 t fired, 26521515 attempts, .
56 EF STEQ 1435/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1696 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1700/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 589760159 t fired, 60478093 attempts, .
55 EF FNDP 1700/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 259428338 t fired, 26601490 attempts, .
56 EF STEQ 1440/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1701 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1705/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 591502267 t fired, 60656882 attempts, .
55 EF FNDP 1705/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 260210887 t fired, 26681528 attempts, .
56 EF STEQ 1445/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1706 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1710/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 593241112 t fired, 60835315 attempts, .
55 EF FNDP 1710/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 260995103 t fired, 26761732 attempts, .
56 EF STEQ 1450/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1711 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1715/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 594987402 t fired, 61014368 attempts, .
55 EF FNDP 1715/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 261776807 t fired, 26842054 attempts, .
56 EF STEQ 1455/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1716 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1720/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 596735528 t fired, 61193430 attempts, .
55 EF FNDP 1720/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 262525223 t fired, 26918566 attempts, .
56 EF STEQ 1460/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1721 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1725/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 598475398 t fired, 61371614 attempts, .
55 EF FNDP 1725/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 263308583 t fired, 26999029 attempts, .
56 EF STEQ 1465/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1726 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1730/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 600249109 t fired, 61553173 attempts, .
55 EF FNDP 1730/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 264079056 t fired, 27077977 attempts, .
56 EF STEQ 1470/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1731 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1735/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 601996315 t fired, 61732451 attempts, .
55 EF FNDP 1735/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 264858154 t fired, 27157913 attempts, .
56 EF STEQ 1475/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1736 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1740/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 603759573 t fired, 61912991 attempts, .
55 EF FNDP 1740/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 265632191 t fired, 27237336 attempts, .
56 EF STEQ 1480/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1741 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1745/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 605504787 t fired, 62092004 attempts, .
55 EF FNDP 1745/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 266415397 t fired, 27317629 attempts, .
56 EF STEQ 1485/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1746 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1750/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 607273735 t fired, 62273399 attempts, .
55 EF FNDP 1750/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 267191200 t fired, 27397071 attempts, .
56 EF STEQ 1490/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1751 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1755/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 609038002 t fired, 62454348 attempts, .
55 EF FNDP 1755/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 267969547 t fired, 27477021 attempts, .
56 EF STEQ 1495/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1756 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1760/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 610789563 t fired, 62633941 attempts, .
55 EF FNDP 1760/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 268750992 t fired, 27557178 attempts, .
56 EF STEQ 1500/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1761 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1765/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 612536340 t fired, 62812957 attempts, .
55 EF FNDP 1765/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 269533606 t fired, 27637581 attempts, .
56 EF STEQ 1505/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1766 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1770/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 614280190 t fired, 62991608 attempts, .
55 EF FNDP 1770/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 270310036 t fired, 27717171 attempts, .
56 EF STEQ 1510/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1771 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1775/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 616029427 t fired, 63170789 attempts, .
55 EF FNDP 1775/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 271086674 t fired, 27796612 attempts, .
56 EF STEQ 1515/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1776 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1780/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 617778494 t fired, 63350079 attempts, .
55 EF FNDP 1780/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 271865879 t fired, 27876333 attempts, .
56 EF STEQ 1520/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1781 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1785/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 619526041 t fired, 63529213 attempts, .
55 EF FNDP 1785/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 272644934 t fired, 27956277 attempts, .
56 EF STEQ 1525/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1786 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1790/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 621272457 t fired, 63708109 attempts, .
55 EF FNDP 1790/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 273421199 t fired, 28035779 attempts, .
56 EF STEQ 1530/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1791 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1795/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 623016493 t fired, 63886802 attempts, .
55 EF FNDP 1795/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 274199954 t fired, 28115870 attempts, .
56 EF STEQ 1535/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1796 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1800/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 624763570 t fired, 64065832 attempts, .
55 EF FNDP 1800/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 274977799 t fired, 28195709 attempts, .
56 EF STEQ 1540/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1801 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1805/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 626506241 t fired, 64244373 attempts, .
55 EF FNDP 1805/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 275754922 t fired, 28275715 attempts, .
56 EF STEQ 1545/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1806 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1810/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 628283659 t fired, 64426682 attempts, .
55 EF FNDP 1810/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 276526622 t fired, 28354791 attempts, .
56 EF STEQ 1550/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1811 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1815/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 630113363 t fired, 64614506 attempts, .
55 EF FNDP 1815/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 277315206 t fired, 28435769 attempts, .
56 EF STEQ 1555/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1816 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1820/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 631944608 t fired, 64802610 attempts, .
55 EF FNDP 1820/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 278106232 t fired, 28516744 attempts, .
56 EF STEQ 1560/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1821 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1825/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 633773201 t fired, 64990307 attempts, .
55 EF FNDP 1825/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 278894885 t fired, 28597281 attempts, .
56 EF STEQ 1565/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1826 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1830/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 635542631 t fired, 65172040 attempts, .
55 EF FNDP 1830/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 279635854 t fired, 28673127 attempts, .
56 EF STEQ 1570/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1831 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1835/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 637284648 t fired, 65350784 attempts, .
55 EF FNDP 1835/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 280417853 t fired, 28753425 attempts, .
56 EF STEQ 1575/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1836 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1840/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 639028283 t fired, 65529126 attempts, .
55 EF FNDP 1840/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 281199091 t fired, 28833629 attempts, .
56 EF STEQ 1580/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1841 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1845/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 640763903 t fired, 65707382 attempts, .
55 EF FNDP 1845/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 281943638 t fired, 28909921 attempts, .
56 EF STEQ 1585/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1846 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1850/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 642505461 t fired, 65886039 attempts, .
55 EF FNDP 1850/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 282724311 t fired, 28989788 attempts, .
56 EF STEQ 1590/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1851 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1855/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 644315604 t fired, 66071753 attempts, .
55 EF FNDP 1855/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 283513091 t fired, 29070570 attempts, .
56 EF STEQ 1595/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1856 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1860/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 646081731 t fired, 66252471 attempts, .
55 EF FNDP 1860/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 284287045 t fired, 29149872 attempts, .
56 EF STEQ 1600/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1861 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1865/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 647888837 t fired, 66437774 attempts, .
55 EF FNDP 1865/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 285075035 t fired, 29230558 attempts, .
56 EF STEQ 1605/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1866 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1870/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 649725150 t fired, 66625701 attempts, .
55 EF FNDP 1870/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 285867273 t fired, 29311751 attempts, .
56 EF STEQ 1610/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1871 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1875/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 651511356 t fired, 66808512 attempts, .
55 EF FNDP 1875/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 286639075 t fired, 29390875 attempts, .
56 EF STEQ 1615/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1876 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1880/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 653264893 t fired, 66988286 attempts, .
55 EF FNDP 1880/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 287417913 t fired, 29470748 attempts, .
56 EF STEQ 1620/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1881 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1885/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 655024703 t fired, 67168551 attempts, .
55 EF FNDP 1885/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 288192973 t fired, 29550107 attempts, .
56 EF STEQ 1625/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1886 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1890/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 656767406 t fired, 67347197 attempts, .
55 EF FNDP 1890/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 288972003 t fired, 29629797 attempts, .
56 EF STEQ 1630/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1891 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1895/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 658514193 t fired, 67526249 attempts, .
55 EF FNDP 1895/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 289751568 t fired, 29709602 attempts, .
56 EF STEQ 1635/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1896 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1900/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 660263798 t fired, 67705441 attempts, .
55 EF FNDP 1900/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 290530020 t fired, 29789261 attempts, .
56 EF STEQ 1640/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1901 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1905/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 662007414 t fired, 67884389 attempts, .
55 EF FNDP 1905/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 291307539 t fired, 29869297 attempts, .
56 EF STEQ 1645/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1906 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1910/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 663753495 t fired, 68063543 attempts, .
55 EF FNDP 1910/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 292054367 t fired, 29945936 attempts, .
56 EF STEQ 1650/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1911 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1915/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 665494610 t fired, 68241913 attempts, .
55 EF FNDP 1915/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 292835222 t fired, 30026143 attempts, .
56 EF STEQ 1655/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1916 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1920/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 667233886 t fired, 68419922 attempts, .
55 EF FNDP 1920/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 293614346 t fired, 30105963 attempts, .
56 EF STEQ 1660/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1921 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1925/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 668972205 t fired, 68597873 attempts, .
55 EF FNDP 1925/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 294390873 t fired, 30185753 attempts, .
56 EF STEQ 1665/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1926 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1930/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 670710433 t fired, 68776177 attempts, .
55 EF FNDP 1930/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 295166704 t fired, 30265241 attempts, .
56 EF STEQ 1670/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1931 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1935/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 672447132 t fired, 68954562 attempts, .
55 EF FNDP 1935/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 295941662 t fired, 30344911 attempts, .
56 EF STEQ 1675/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1936 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1940/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 674184185 t fired, 69132539 attempts, .
55 EF FNDP 1940/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 296717978 t fired, 30424492 attempts, .
56 EF STEQ 1680/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1941 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1945/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 675923920 t fired, 69310530 attempts, .
55 EF FNDP 1945/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 297494474 t fired, 30503943 attempts, .
56 EF STEQ 1685/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1946 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1950/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 677660613 t fired, 69488315 attempts, .
55 EF FNDP 1950/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 298241165 t fired, 30580319 attempts, .
56 EF STEQ 1690/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1951 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1955/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 679397362 t fired, 69666517 attempts, .
55 EF FNDP 1955/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 299018969 t fired, 30660127 attempts, .
56 EF STEQ 1695/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1956 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1960/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 681137793 t fired, 69844923 attempts, .
55 EF FNDP 1960/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 299801189 t fired, 30740120 attempts, .
56 EF STEQ 1700/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1961 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1965/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 682880028 t fired, 70023330 attempts, .
55 EF FNDP 1965/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 300582874 t fired, 30820186 attempts, .
56 EF STEQ 1705/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1966 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1970/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 684618977 t fired, 70201818 attempts, .
55 EF FNDP 1970/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 301363327 t fired, 30900364 attempts, .
56 EF STEQ 1710/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1971 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1975/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 686360744 t fired, 70380132 attempts, .
55 EF FNDP 1975/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 302145469 t fired, 30980410 attempts, .
56 EF STEQ 1715/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1976 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1980/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 688100822 t fired, 70558398 attempts, .
55 EF FNDP 1980/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 302926105 t fired, 31060471 attempts, .
56 EF STEQ 1720/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1981 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1985/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 689847672 t fired, 70737335 attempts, .
55 EF FNDP 1985/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 303705452 t fired, 31140544 attempts, .
56 EF STEQ 1725/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1986 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1990/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 691596832 t fired, 70916866 attempts, .
55 EF FNDP 1990/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 304486879 t fired, 31220734 attempts, .
56 EF STEQ 1730/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1991 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 1995/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 693339425 t fired, 71095434 attempts, .
55 EF FNDP 1995/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 305263517 t fired, 31299952 attempts, .
56 EF STEQ 1735/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 1996 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 2000/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 695089203 t fired, 71274501 attempts, .
55 EF FNDP 2000/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 306043583 t fired, 31380171 attempts, .
56 EF STEQ 1740/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 2001 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-09: AFAG false CTL model checker
DoubleExponent-PT-010-CTLFireability-10: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-12: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-010-CTLFireability-00: DISJ 0 0 2 0 3 0 2 0
DoubleExponent-PT-010-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-010-CTLFireability-14: EF 0 0 1 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 EF FNDP 2005/3599 0/5 DoubleExponent-PT-010-CTLFireability-14 696836635 t fired, 71453377 attempts, .
55 EF FNDP 2005/3599 0/5 DoubleExponent-PT-010-CTLFireability-00 306824780 t fired, 31460302 attempts, .
56 EF STEQ 1745/3339 0/5 DoubleExponent-PT-010-CTLFireability-00 sara is running.

Time elapsed: 2006 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-010-CTLFireability-01: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-03: CTL true CTL model checker
DoubleExponent-PT-010-CTLFireability-04: CTL false CTL model checker
DoubleExponent-PT-010-CTLFireability-06: CONJ false state space
DoubleExponent-PT-010-CTLFireability-08: CTL true CTL model checker

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DoubleExponent-PT-010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819414500474"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-010.tgz
mv DoubleExponent-PT-010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;