Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r135-smll-167819413800234.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Diffusion2D-PT-D40N100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819413800234
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.1M
-rw-r--r-- 1 mcc users 7.0K Feb 26 04:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 04:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 26 04:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 26 04:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 15:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 15:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 04:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 26 04:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K Feb 26 04:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 26 04:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:58 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:58 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 4.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-00
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-01
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-02
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-03
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-04
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-05
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-06
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-07
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-08
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-09
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-10
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-11
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-12
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-13
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-14
FORMULA_NAME Diffusion2D-PT-D40N100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678298601562

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Diffusion2D-PT-D40N100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 18:03:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 18:03:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 18:03:25] [INFO ] Load time of PNML (sax parser for PT used): 677 ms
[2023-03-08 18:03:25] [INFO ] Transformed 1600 places.
[2023-03-08 18:03:25] [INFO ] Transformed 12324 transitions.
[2023-03-08 18:03:25] [INFO ] Parsed PT model containing 1600 places and 12324 transitions and 24648 arcs in 1039 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 27 ms.
Support contains 97 out of 1600 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 504 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
// Phase 1: matrix 12324 rows 1600 cols
[2023-03-08 18:03:26] [INFO ] Computed 1 place invariants in 161 ms
[2023-03-08 18:03:27] [INFO ] Implicit Places using invariants in 851 ms returned []
Implicit Place search using SMT only with invariants took 897 ms to find 0 implicit places.
[2023-03-08 18:03:27] [INFO ] Invariant cache hit.
[2023-03-08 18:03:35] [INFO ] Dead Transitions using invariants and state equation in 7458 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8867 ms. Remains : 1600/1600 places, 12324/12324 transitions.
Support contains 97 out of 1600 places after structural reductions.
[2023-03-08 18:03:36] [INFO ] Flatten gal took : 880 ms
[2023-03-08 18:03:36] [INFO ] Flatten gal took : 364 ms
[2023-03-08 18:03:37] [INFO ] Input system was already deterministic with 12324 transitions.
Support contains 95 out of 1600 places (down from 97) after GAL structural reductions.
Incomplete random walk after 10092 steps, including 2 resets, run finished after 113 ms. (steps per millisecond=89 ) properties (out of 70) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 68) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 68) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 67) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 67) seen :0
Interrupted probabilistic random walk after 113263 steps, run timeout after 3001 ms. (steps per millisecond=37 ) properties seen :{3=1, 4=1, 6=1, 7=1, 10=1, 13=1, 27=1, 32=1, 34=1, 46=1, 52=1, 66=1}
Probabilistic random walk after 113263 steps, saw 93957 distinct states, run finished after 3002 ms. (steps per millisecond=37 ) properties seen :12
Running SMT prover for 55 properties.
[2023-03-08 18:03:41] [INFO ] Invariant cache hit.
[2023-03-08 18:03:44] [INFO ] [Real]Absence check using 1 positive place invariants in 24 ms returned sat
[2023-03-08 18:04:06] [INFO ] After 19772ms SMT Verify possible using state equation in real domain returned unsat :0 sat :12 real:43
[2023-03-08 18:04:06] [INFO ] After 19793ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :12 real:43
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-08 18:04:06] [INFO ] After 25132ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :12 real:43
[2023-03-08 18:04:08] [INFO ] [Nat]Absence check using 1 positive place invariants in 13 ms returned sat
[2023-03-08 18:04:31] [INFO ] After 21197ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :55
[2023-03-08 18:04:31] [INFO ] After 21200ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :55
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-08 18:04:31] [INFO ] After 25132ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :55
Fused 55 Parikh solutions to 47 different solutions.
Parikh walk visited 54 properties in 30555 ms.
Support contains 1 out of 1600 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12308 edges and 1600 vertex of which 1599 / 1600 are part of one of the 1 SCC in 26 ms
Free SCC test removed 1598 places
Drop transitions removed 12308 transitions
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 12322 transitions.
Applied a total of 1 rules in 62 ms. Remains 2 /1600 variables (removed 1598) and now considering 2/12324 (removed 12322) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 62 ms. Remains : 2/1600 places, 2/12324 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
[2023-03-08 18:05:02] [INFO ] Flatten gal took : 252 ms
[2023-03-08 18:05:02] [INFO ] Flatten gal took : 240 ms
[2023-03-08 18:05:03] [INFO ] Input system was already deterministic with 12324 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 463 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 468 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:04] [INFO ] Flatten gal took : 289 ms
[2023-03-08 18:05:04] [INFO ] Flatten gal took : 197 ms
[2023-03-08 18:05:05] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 207 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 211 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:05] [INFO ] Flatten gal took : 184 ms
[2023-03-08 18:05:05] [INFO ] Flatten gal took : 196 ms
[2023-03-08 18:05:06] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 206 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 207 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:06] [INFO ] Flatten gal took : 176 ms
[2023-03-08 18:05:06] [INFO ] Flatten gal took : 188 ms
[2023-03-08 18:05:07] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12308 edges and 1600 vertex of which 1599 / 1600 are part of one of the 1 SCC in 11 ms
Free SCC test removed 1598 places
Ensure Unique test removed 12321 transitions
Reduce isomorphic transitions removed 12321 transitions.
Applied a total of 1 rules in 34 ms. Remains 2 /1600 variables (removed 1598) and now considering 3/12324 (removed 12321) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 2/1600 places, 3/12324 transitions.
[2023-03-08 18:05:07] [INFO ] Flatten gal took : 1 ms
[2023-03-08 18:05:07] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:07] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA Diffusion2D-PT-D40N100-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 207 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 208 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:07] [INFO ] Flatten gal took : 178 ms
[2023-03-08 18:05:07] [INFO ] Flatten gal took : 200 ms
[2023-03-08 18:05:08] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 231 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 232 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:08] [INFO ] Flatten gal took : 183 ms
[2023-03-08 18:05:08] [INFO ] Flatten gal took : 190 ms
[2023-03-08 18:05:09] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 216 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 219 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:09] [INFO ] Flatten gal took : 182 ms
[2023-03-08 18:05:09] [INFO ] Flatten gal took : 195 ms
[2023-03-08 18:05:10] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 213 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 215 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:10] [INFO ] Flatten gal took : 181 ms
[2023-03-08 18:05:10] [INFO ] Flatten gal took : 192 ms
[2023-03-08 18:05:11] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12292 edges and 1600 vertex of which 1598 / 1600 are part of one of the 1 SCC in 10 ms
Free SCC test removed 1597 places
Ensure Unique test removed 12319 transitions
Reduce isomorphic transitions removed 12319 transitions.
Applied a total of 1 rules in 26 ms. Remains 3 /1600 variables (removed 1597) and now considering 5/12324 (removed 12319) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 3/1600 places, 5/12324 transitions.
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:11] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12276 edges and 1600 vertex of which 1597 / 1600 are part of one of the 1 SCC in 6 ms
Free SCC test removed 1596 places
Ensure Unique test removed 12317 transitions
Reduce isomorphic transitions removed 12317 transitions.
Applied a total of 1 rules in 19 ms. Remains 4 /1600 variables (removed 1596) and now considering 7/12324 (removed 12317) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 4/1600 places, 7/12324 transitions.
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:11] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 225 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 226 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 181 ms
[2023-03-08 18:05:11] [INFO ] Flatten gal took : 192 ms
[2023-03-08 18:05:12] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12212 edges and 1600 vertex of which 1593 / 1600 are part of one of the 1 SCC in 5 ms
Free SCC test removed 1592 places
Ensure Unique test removed 12309 transitions
Reduce isomorphic transitions removed 12309 transitions.
Applied a total of 1 rules in 18 ms. Remains 8 /1600 variables (removed 1592) and now considering 15/12324 (removed 12309) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 8/1600 places, 15/12324 transitions.
[2023-03-08 18:05:12] [INFO ] Flatten gal took : 1 ms
[2023-03-08 18:05:12] [INFO ] Flatten gal took : 0 ms
[2023-03-08 18:05:12] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 214 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 215 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:12] [INFO ] Flatten gal took : 187 ms
[2023-03-08 18:05:12] [INFO ] Flatten gal took : 191 ms
[2023-03-08 18:05:13] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 208 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 209 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:13] [INFO ] Flatten gal took : 185 ms
[2023-03-08 18:05:14] [INFO ] Flatten gal took : 193 ms
[2023-03-08 18:05:14] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 208 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 209 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:14] [INFO ] Flatten gal took : 180 ms
[2023-03-08 18:05:15] [INFO ] Flatten gal took : 193 ms
[2023-03-08 18:05:15] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 207 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 208 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 18:05:15] [INFO ] Flatten gal took : 180 ms
[2023-03-08 18:05:16] [INFO ] Flatten gal took : 216 ms
[2023-03-08 18:05:16] [INFO ] Input system was already deterministic with 12324 transitions.
[2023-03-08 18:05:16] [INFO ] Flatten gal took : 232 ms
[2023-03-08 18:05:16] [INFO ] Flatten gal took : 203 ms
[2023-03-08 18:05:16] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 18:05:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1600 places, 12324 transitions and 24648 arcs took 74 ms.
Total runtime 112168 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Diffusion2D-PT-D40N100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability

FORMULA Diffusion2D-PT-D40N100-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Diffusion2D-PT-D40N100-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678299816054

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
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lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
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lola: Created skeleton in 0.000000 secs.
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lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ 0 0 0 0 3 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 22 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 15
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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Diffusion2D-PT-D40N100-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ 0 0 0 0 3 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 43 (type EXCL) for 42 Diffusion2D-PT-D40N100-CTLFireability-11
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for Diffusion2D-PT-D40N100-CTLFireability-11
lola: result : false
lola: markings : 701
lola: fired transitions : 2233
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 45 Diffusion2D-PT-D40N100-CTLFireability-12
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for Diffusion2D-PT-D40N100-CTLFireability-12
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 37 (type EXCL) for 36 Diffusion2D-PT-D40N100-CTLFireability-09
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type FNDP) for 45 Diffusion2D-PT-D40N100-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 45 Diffusion2D-PT-D40N100-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SRCH) for 45 Diffusion2D-PT-D40N100-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type SRCH) for Diffusion2D-PT-D40N100-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 66 (type FNDP) for Diffusion2D-PT-D40N100-CTLFireability-12 (obsolete)
lola: CANCELED task # 67 (type EQUN) for Diffusion2D-PT-D40N100-CTLFireability-12 (obsolete)
lola: FINISHED task # 37 (type EXCL) for Diffusion2D-PT-D40N100-CTLFireability-09
lola: result : false
lola: markings : 201
lola: fired transitions : 1100
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 66 (type FNDP) for Diffusion2D-PT-D40N100-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/370/CTLFireability-67.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 67 (type EQUN) for Diffusion2D-PT-D40N100-CTLFireability-12
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 34 (type EXCL) for 33 Diffusion2D-PT-D40N100-CTLFireability-08
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for Diffusion2D-PT-D40N100-CTLFireability-08
lola: result : false
lola: markings : 5151
lola: fired transitions : 36052
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 57 (type EXCL) for 56 Diffusion2D-PT-D40N100-CTLFireability-13
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 57 (type EXCL) for Diffusion2D-PT-D40N100-CTLFireability-13
lola: result : true
lola: markings : 18
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 40 (type EXCL) for 39 Diffusion2D-PT-D40N100-CTLFireability-10
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-01: CTL 1 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 1 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 2/274 1/32 Diffusion2D-PT-D40N100-CTLFireability-10 21027 m, 4205 m/sec, 88155 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF

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Diffusion2D-PT-D40N100-CTLFireability-15: EXEF 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 7/274 3/32 Diffusion2D-PT-D40N100-CTLFireability-10 102758 m, 16346 m/sec, 430810 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 12/274 4/32 Diffusion2D-PT-D40N100-CTLFireability-10 177094 m, 14867 m/sec, 734436 t fired, .

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40 CTL EXCL 17/274 5/32 Diffusion2D-PT-D40N100-CTLFireability-10 254171 m, 15415 m/sec, 1028680 t fired, .

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40 CTL EXCL 22/274 6/32 Diffusion2D-PT-D40N100-CTLFireability-10 330559 m, 15277 m/sec, 1327438 t fired, .

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40 CTL EXCL 27/274 7/32 Diffusion2D-PT-D40N100-CTLFireability-10 407907 m, 15469 m/sec, 1625542 t fired, .

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40 CTL EXCL 32/274 8/32 Diffusion2D-PT-D40N100-CTLFireability-10 482104 m, 14839 m/sec, 1919172 t fired, .

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40 CTL EXCL 37/274 9/32 Diffusion2D-PT-D40N100-CTLFireability-10 554411 m, 14461 m/sec, 2204530 t fired, .

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40 CTL EXCL 42/274 10/32 Diffusion2D-PT-D40N100-CTLFireability-10 626612 m, 14440 m/sec, 2486496 t fired, .

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40 CTL EXCL 47/274 11/32 Diffusion2D-PT-D40N100-CTLFireability-10 696159 m, 13909 m/sec, 2758050 t fired, .

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40 CTL EXCL 52/274 12/32 Diffusion2D-PT-D40N100-CTLFireability-10 766921 m, 14152 m/sec, 3036124 t fired, .

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40 CTL EXCL 57/274 13/32 Diffusion2D-PT-D40N100-CTLFireability-10 838309 m, 14277 m/sec, 3319174 t fired, .

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40 CTL EXCL 62/274 14/32 Diffusion2D-PT-D40N100-CTLFireability-10 912036 m, 14745 m/sec, 3605598 t fired, .

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40 CTL EXCL 67/274 15/32 Diffusion2D-PT-D40N100-CTLFireability-10 982720 m, 14136 m/sec, 3881063 t fired, .

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40 CTL EXCL 77/274 17/32 Diffusion2D-PT-D40N100-CTLFireability-10 1126159 m, 14569 m/sec, 4436705 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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28 CTL EXCL 56/379 8/32 Diffusion2D-PT-D40N100-CTLFireability-06 437295 m, 7939 m/sec, 3299194 t fired, .

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28 CTL EXCL 81/379 10/32 Diffusion2D-PT-D40N100-CTLFireability-06 622959 m, 7310 m/sec, 4690725 t fired, .

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28 CTL EXCL 86/379 11/32 Diffusion2D-PT-D40N100-CTLFireability-06 659522 m, 7312 m/sec, 4961899 t fired, .

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28 CTL EXCL 91/379 11/32 Diffusion2D-PT-D40N100-CTLFireability-06 695191 m, 7133 m/sec, 5226414 t fired, .

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28 CTL EXCL 96/379 12/32 Diffusion2D-PT-D40N100-CTLFireability-06 731408 m, 7243 m/sec, 5499502 t fired, .

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28 CTL EXCL 101/379 12/32 Diffusion2D-PT-D40N100-CTLFireability-06 768921 m, 7502 m/sec, 5771435 t fired, .

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28 CTL EXCL 106/379 13/32 Diffusion2D-PT-D40N100-CTLFireability-06 806726 m, 7561 m/sec, 6050518 t fired, .

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28 CTL EXCL 126/379 15/32 Diffusion2D-PT-D40N100-CTLFireability-06 951407 m, 7245 m/sec, 7126949 t fired, .

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28 CTL EXCL 271/379 32/32 Diffusion2D-PT-D40N100-CTLFireability-06 1995804 m, 7049 m/sec, 14849728 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

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Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

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25 CTL EXCL 60/392 23/32 Diffusion2D-PT-D40N100-CTLFireability-05 1018503 m, 17157 m/sec, 4281548 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

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9 CTL EXCL 20/964 5/32 Diffusion2D-PT-D40N100-CTLFireability-02 220671 m, 10460 m/sec, 1122289 t fired, .

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9 CTL EXCL 25/964 5/32 Diffusion2D-PT-D40N100-CTLFireability-02 271228 m, 10111 m/sec, 1366591 t fired, .

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9 CTL EXCL 30/964 6/32 Diffusion2D-PT-D40N100-CTLFireability-02 321549 m, 10064 m/sec, 1615277 t fired, .

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9 CTL EXCL 90/964 14/32 Diffusion2D-PT-D40N100-CTLFireability-02 907330 m, 9685 m/sec, 4497601 t fired, .

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9 CTL EXCL 95/964 15/32 Diffusion2D-PT-D40N100-CTLFireability-02 955062 m, 9546 m/sec, 4731896 t fired, .

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9 CTL EXCL 100/964 15/32 Diffusion2D-PT-D40N100-CTLFireability-02 1001424 m, 9272 m/sec, 4962016 t fired, .

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9 CTL EXCL 105/964 16/32 Diffusion2D-PT-D40N100-CTLFireability-02 1049779 m, 9671 m/sec, 5199214 t fired, .

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9 CTL EXCL 120/964 18/32 Diffusion2D-PT-D40N100-CTLFireability-02 1193379 m, 9739 m/sec, 5902392 t fired, .

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9 CTL EXCL 125/964 19/32 Diffusion2D-PT-D40N100-CTLFireability-02 1240633 m, 9450 m/sec, 6137886 t fired, .

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9 CTL EXCL 130/964 20/32 Diffusion2D-PT-D40N100-CTLFireability-02 1285425 m, 8958 m/sec, 6363229 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
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Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

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9 CTL EXCL 160/964 24/32 Diffusion2D-PT-D40N100-CTLFireability-02 1567058 m, 9249 m/sec, 7750394 t fired, .

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9 CTL EXCL 165/964 25/32 Diffusion2D-PT-D40N100-CTLFireability-02 1614766 m, 9541 m/sec, 7986612 t fired, .

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9 CTL EXCL 180/964 28/32 Diffusion2D-PT-D40N100-CTLFireability-02 1755792 m, 9442 m/sec, 8680996 t fired, .

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9 CTL EXCL 205/964 32/32 Diffusion2D-PT-D40N100-CTLFireability-02 1990488 m, 8774 m/sec, 9831259 t fired, .

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1 CTL EXCL 143/2671 28/32 Diffusion2D-PT-D40N100-CTLFireability-00 1764940 m, 10740 m/sec, 7921120 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

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Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 148/2671 29/32 Diffusion2D-PT-D40N100-CTLFireability-00 1818549 m, 10721 m/sec, 8186207 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 153/2671 30/32 Diffusion2D-PT-D40N100-CTLFireability-00 1869675 m, 10225 m/sec, 8440107 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 158/2671 31/32 Diffusion2D-PT-D40N100-CTLFireability-00 1922752 m, 10615 m/sec, 8702493 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 163/2671 32/32 Diffusion2D-PT-D40N100-CTLFireability-00 1974256 m, 10300 m/sec, 8955101 t fired, .

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Diffusion2D-PT-D40N100-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ 0 0 0 0 2 0 2 0
Diffusion2D-PT-D40N100-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N100-CTLFireability-10: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N100-CTLFireability-00: CTL unknown AGGR
Diffusion2D-PT-D40N100-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-02: DISJ unknown DISJ
Diffusion2D-PT-D40N100-CTLFireability-04: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-05: DISJ true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-06: CTL unknown AGGR
Diffusion2D-PT-D40N100-CTLFireability-07: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-09: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-10: CTL unknown AGGR
Diffusion2D-PT-D40N100-CTLFireability-11: CTL false CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-12: CONJ false search / frozen tokens
Diffusion2D-PT-D40N100-CTLFireability-13: EXEF true state space /EXEF
Diffusion2D-PT-D40N100-CTLFireability-14: CTL true CTL model checker
Diffusion2D-PT-D40N100-CTLFireability-15: EXEF true state space /EXEF


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D40N100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Diffusion2D-PT-D40N100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819413800234"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D40N100.tgz
mv Diffusion2D-PT-D40N100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;