About the Execution of LoLa+red for Diffusion2D-PT-D40N050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 7588.663 | 1361998.00 | 1448898.00 | 4597.80 | ?TFTTF?TT?F?TTT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819413800226.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Diffusion2D-PT-D40N050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819413800226
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.1M
-rw-r--r-- 1 mcc users 12K Feb 26 04:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 113K Feb 26 04:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 04:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 26 04:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 15:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 15:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 04:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 26 04:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 26 04:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 04:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:58 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:58 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 4.7M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-00
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-01
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-02
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-03
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-04
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-05
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-06
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-07
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-08
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-09
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-10
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-11
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-12
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-13
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-14
FORMULA_NAME Diffusion2D-PT-D40N050-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678296387008
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Diffusion2D-PT-D40N050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 17:26:30] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 17:26:30] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 17:26:30] [INFO ] Load time of PNML (sax parser for PT used): 594 ms
[2023-03-08 17:26:30] [INFO ] Transformed 1600 places.
[2023-03-08 17:26:30] [INFO ] Transformed 12324 transitions.
[2023-03-08 17:26:30] [INFO ] Parsed PT model containing 1600 places and 12324 transitions and 24648 arcs in 781 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 18 ms.
Support contains 91 out of 1600 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 587 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
// Phase 1: matrix 12324 rows 1600 cols
[2023-03-08 17:26:31] [INFO ] Computed 1 place invariants in 159 ms
[2023-03-08 17:26:32] [INFO ] Implicit Places using invariants in 951 ms returned []
Implicit Place search using SMT only with invariants took 994 ms to find 0 implicit places.
[2023-03-08 17:26:32] [INFO ] Invariant cache hit.
[2023-03-08 17:26:41] [INFO ] Dead Transitions using invariants and state equation in 9052 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10656 ms. Remains : 1600/1600 places, 12324/12324 transitions.
Support contains 91 out of 1600 places after structural reductions.
[2023-03-08 17:26:42] [INFO ] Flatten gal took : 879 ms
[2023-03-08 17:26:43] [INFO ] Flatten gal took : 354 ms
[2023-03-08 17:26:44] [INFO ] Input system was already deterministic with 12324 transitions.
Support contains 88 out of 1600 places (down from 91) after GAL structural reductions.
Incomplete random walk after 10044 steps, including 2 resets, run finished after 194 ms. (steps per millisecond=51 ) properties (out of 67) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 60) seen :0
Running SMT prover for 60 properties.
[2023-03-08 17:26:45] [INFO ] Invariant cache hit.
[2023-03-08 17:26:48] [INFO ] [Real]Absence check using 1 positive place invariants in 25 ms returned sat
[2023-03-08 17:27:04] [INFO ] After 19339ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:60
[2023-03-08 17:27:07] [INFO ] [Nat]Absence check using 1 positive place invariants in 24 ms returned sat
[2023-03-08 17:27:29] [INFO ] After 20149ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :60
[2023-03-08 17:27:29] [INFO ] After 20180ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :60
Attempting to minimize the solution found.
Minimization took 8 ms.
[2023-03-08 17:27:29] [INFO ] After 25118ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :60
Fused 60 Parikh solutions to 38 different solutions.
Parikh walk visited 53 properties in 31643 ms.
Support contains 10 out of 1600 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12178 edges and 1600 vertex of which 1590 / 1600 are part of one of the 1 SCC in 30 ms
Free SCC test removed 1589 places
Drop transitions removed 12178 transitions
Ensure Unique test removed 124 transitions
Reduce isomorphic transitions removed 12302 transitions.
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 4 place count 11 transition count 19
Applied a total of 4 rules in 80 ms. Remains 11 /1600 variables (removed 1589) and now considering 19/12324 (removed 12305) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 80 ms. Remains : 11/1600 places, 19/12324 transitions.
Finished random walk after 7672 steps, including 2 resets, run visited all 7 properties in 31 ms. (steps per millisecond=247 )
[2023-03-08 17:28:01] [INFO ] Flatten gal took : 226 ms
[2023-03-08 17:28:02] [INFO ] Flatten gal took : 239 ms
[2023-03-08 17:28:02] [INFO ] Input system was already deterministic with 12324 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 423 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 426 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:03] [INFO ] Flatten gal took : 199 ms
[2023-03-08 17:28:03] [INFO ] Flatten gal took : 185 ms
[2023-03-08 17:28:03] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 216 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 218 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:04] [INFO ] Flatten gal took : 187 ms
[2023-03-08 17:28:04] [INFO ] Flatten gal took : 203 ms
[2023-03-08 17:28:05] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 203 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 206 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:05] [INFO ] Flatten gal took : 186 ms
[2023-03-08 17:28:05] [INFO ] Flatten gal took : 191 ms
[2023-03-08 17:28:06] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 198 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 200 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:06] [INFO ] Flatten gal took : 185 ms
[2023-03-08 17:28:06] [INFO ] Flatten gal took : 189 ms
[2023-03-08 17:28:07] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12276 edges and 1600 vertex of which 1597 / 1600 are part of one of the 1 SCC in 17 ms
Free SCC test removed 1596 places
Ensure Unique test removed 12317 transitions
Reduce isomorphic transitions removed 12317 transitions.
Applied a total of 1 rules in 39 ms. Remains 4 /1600 variables (removed 1596) and now considering 7/12324 (removed 12317) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 39 ms. Remains : 4/1600 places, 7/12324 transitions.
[2023-03-08 17:28:07] [INFO ] Flatten gal took : 1 ms
[2023-03-08 17:28:07] [INFO ] Flatten gal took : 0 ms
[2023-03-08 17:28:07] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 237 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 239 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:07] [INFO ] Flatten gal took : 319 ms
[2023-03-08 17:28:08] [INFO ] Flatten gal took : 329 ms
[2023-03-08 17:28:08] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 207 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 208 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:09] [INFO ] Flatten gal took : 176 ms
[2023-03-08 17:28:09] [INFO ] Flatten gal took : 192 ms
[2023-03-08 17:28:09] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 212 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 212 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:10] [INFO ] Flatten gal took : 174 ms
[2023-03-08 17:28:10] [INFO ] Flatten gal took : 186 ms
[2023-03-08 17:28:10] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 208 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 209 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:11] [INFO ] Flatten gal took : 196 ms
[2023-03-08 17:28:11] [INFO ] Flatten gal took : 202 ms
[2023-03-08 17:28:11] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 212 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 212 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:12] [INFO ] Flatten gal took : 205 ms
[2023-03-08 17:28:12] [INFO ] Flatten gal took : 188 ms
[2023-03-08 17:28:12] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12244 edges and 1600 vertex of which 1595 / 1600 are part of one of the 1 SCC in 11 ms
Free SCC test removed 1594 places
Ensure Unique test removed 12313 transitions
Reduce isomorphic transitions removed 12313 transitions.
Applied a total of 1 rules in 24 ms. Remains 6 /1600 variables (removed 1594) and now considering 11/12324 (removed 12313) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 24 ms. Remains : 6/1600 places, 11/12324 transitions.
[2023-03-08 17:28:12] [INFO ] Flatten gal took : 1 ms
[2023-03-08 17:28:12] [INFO ] Flatten gal took : 1 ms
[2023-03-08 17:28:12] [INFO ] Input system was already deterministic with 11 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 264 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 265 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:13] [INFO ] Flatten gal took : 299 ms
[2023-03-08 17:28:13] [INFO ] Flatten gal took : 227 ms
[2023-03-08 17:28:13] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 201 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 201 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:14] [INFO ] Flatten gal took : 192 ms
[2023-03-08 17:28:14] [INFO ] Flatten gal took : 210 ms
[2023-03-08 17:28:14] [INFO ] Input system was already deterministic with 12324 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12308 edges and 1600 vertex of which 1599 / 1600 are part of one of the 1 SCC in 5 ms
Free SCC test removed 1598 places
Ensure Unique test removed 12321 transitions
Reduce isomorphic transitions removed 12321 transitions.
Applied a total of 1 rules in 16 ms. Remains 2 /1600 variables (removed 1598) and now considering 3/12324 (removed 12321) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 2/1600 places, 3/12324 transitions.
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 0 ms
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 0 ms
[2023-03-08 17:28:15] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA Diffusion2D-PT-D40N050-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Graph (trivial) has 12308 edges and 1600 vertex of which 1599 / 1600 are part of one of the 1 SCC in 4 ms
Free SCC test removed 1598 places
Ensure Unique test removed 12321 transitions
Reduce isomorphic transitions removed 12321 transitions.
Applied a total of 1 rules in 15 ms. Remains 2 /1600 variables (removed 1598) and now considering 3/12324 (removed 12321) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 2/1600 places, 3/12324 transitions.
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 0 ms
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 0 ms
[2023-03-08 17:28:15] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA Diffusion2D-PT-D40N050-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 1600/1600 places, 12324/12324 transitions.
Applied a total of 0 rules in 206 ms. Remains 1600 /1600 variables (removed 0) and now considering 12324/12324 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 206 ms. Remains : 1600/1600 places, 12324/12324 transitions.
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 182 ms
[2023-03-08 17:28:15] [INFO ] Flatten gal took : 187 ms
[2023-03-08 17:28:16] [INFO ] Input system was already deterministic with 12324 transitions.
[2023-03-08 17:28:16] [INFO ] Flatten gal took : 175 ms
[2023-03-08 17:28:16] [INFO ] Flatten gal took : 187 ms
[2023-03-08 17:28:16] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 17:28:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1600 places, 12324 transitions and 24648 arcs took 47 ms.
Total runtime 106393 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Diffusion2D-PT-D40N050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/371
CTLFireability
FORMULA Diffusion2D-PT-D40N050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D40N050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678297749006
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/371/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/371/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/371/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 21 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ 0 0 0 0 2 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
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48 CTL EXCL 5/254 2/32 Diffusion2D-PT-D40N050-CTLFireability-15 49839 m, 9967 m/sec, 208955 t fired, .
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48 CTL EXCL 10/254 3/32 Diffusion2D-PT-D40N050-CTLFireability-15 109799 m, 11992 m/sec, 448871 t fired, .
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48 CTL EXCL 15/254 3/32 Diffusion2D-PT-D40N050-CTLFireability-15 168588 m, 11757 m/sec, 674098 t fired, .
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48 CTL EXCL 20/254 4/32 Diffusion2D-PT-D40N050-CTLFireability-15 225764 m, 11435 m/sec, 894864 t fired, .
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48 CTL EXCL 25/254 5/32 Diffusion2D-PT-D40N050-CTLFireability-15 282173 m, 11281 m/sec, 1118208 t fired, .
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48 CTL EXCL 30/254 6/32 Diffusion2D-PT-D40N050-CTLFireability-15 340686 m, 11702 m/sec, 1341849 t fired, .
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48 CTL EXCL 35/254 6/32 Diffusion2D-PT-D40N050-CTLFireability-15 397878 m, 11438 m/sec, 1569485 t fired, .
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48 CTL EXCL 40/254 7/32 Diffusion2D-PT-D40N050-CTLFireability-15 453585 m, 11141 m/sec, 1788717 t fired, .
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48 CTL EXCL 45/254 8/32 Diffusion2D-PT-D40N050-CTLFireability-15 510794 m, 11441 m/sec, 2011798 t fired, .
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48 CTL EXCL 55/254 10/32 Diffusion2D-PT-D40N050-CTLFireability-15 619623 m, 10680 m/sec, 2439144 t fired, .
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48 CTL EXCL 60/254 10/32 Diffusion2D-PT-D40N050-CTLFireability-15 672015 m, 10478 m/sec, 2647383 t fired, .
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48 CTL EXCL 65/254 11/32 Diffusion2D-PT-D40N050-CTLFireability-15 727904 m, 11177 m/sec, 2863280 t fired, .
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48 CTL EXCL 70/254 12/32 Diffusion2D-PT-D40N050-CTLFireability-15 780459 m, 10511 m/sec, 3072639 t fired, .
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48 CTL EXCL 75/254 12/32 Diffusion2D-PT-D40N050-CTLFireability-15 834639 m, 10836 m/sec, 3284564 t fired, .
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48 CTL EXCL 80/254 13/32 Diffusion2D-PT-D40N050-CTLFireability-15 887658 m, 10603 m/sec, 3490280 t fired, .
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48 CTL EXCL 85/254 14/32 Diffusion2D-PT-D40N050-CTLFireability-15 939556 m, 10379 m/sec, 3693887 t fired, .
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48 CTL EXCL 90/254 15/32 Diffusion2D-PT-D40N050-CTLFireability-15 993157 m, 10720 m/sec, 3904401 t fired, .
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48 CTL EXCL 95/254 15/32 Diffusion2D-PT-D40N050-CTLFireability-15 1046446 m, 10657 m/sec, 4107207 t fired, .
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48 CTL EXCL 100/254 16/32 Diffusion2D-PT-D40N050-CTLFireability-15 1099179 m, 10546 m/sec, 4318559 t fired, .
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48 CTL EXCL 105/254 17/32 Diffusion2D-PT-D40N050-CTLFireability-15 1153899 m, 10944 m/sec, 4534307 t fired, .
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48 CTL EXCL 125/254 20/32 Diffusion2D-PT-D40N050-CTLFireability-15 1359168 m, 10145 m/sec, 5341011 t fired, .
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48 CTL EXCL 130/254 21/32 Diffusion2D-PT-D40N050-CTLFireability-15 1415435 m, 11253 m/sec, 5559238 t fired, .
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48 CTL EXCL 135/254 22/32 Diffusion2D-PT-D40N050-CTLFireability-15 1466983 m, 10309 m/sec, 5764331 t fired, .
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48 CTL EXCL 140/254 23/32 Diffusion2D-PT-D40N050-CTLFireability-15 1518878 m, 10379 m/sec, 5970373 t fired, .
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48 CTL EXCL 145/254 24/32 Diffusion2D-PT-D40N050-CTLFireability-15 1570912 m, 10406 m/sec, 6174813 t fired, .
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48 CTL EXCL 150/254 25/32 Diffusion2D-PT-D40N050-CTLFireability-15 1623542 m, 10526 m/sec, 6377701 t fired, .
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48 CTL EXCL 155/254 26/32 Diffusion2D-PT-D40N050-CTLFireability-15 1676313 m, 10554 m/sec, 6585295 t fired, .
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48 CTL EXCL 160/254 27/32 Diffusion2D-PT-D40N050-CTLFireability-15 1728568 m, 10451 m/sec, 6791690 t fired, .
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48 CTL EXCL 170/254 29/32 Diffusion2D-PT-D40N050-CTLFireability-15 1837557 m, 11059 m/sec, 7207336 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
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Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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42 CTL EXCL 0/337 1/32 Diffusion2D-PT-D40N050-CTLFireability-11 733 m, 146 m/sec, 3062 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
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42 CTL EXCL 5/337 1/32 Diffusion2D-PT-D40N050-CTLFireability-11 36739 m, 7201 m/sec, 335060 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
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Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
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42 CTL EXCL 10/337 2/32 Diffusion2D-PT-D40N050-CTLFireability-11 76171 m, 7886 m/sec, 680825 t fired, .
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42 CTL EXCL 15/337 3/32 Diffusion2D-PT-D40N050-CTLFireability-11 115320 m, 7829 m/sec, 973517 t fired, .
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42 CTL EXCL 20/337 3/32 Diffusion2D-PT-D40N050-CTLFireability-11 151329 m, 7201 m/sec, 1262733 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
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42 CTL EXCL 25/337 4/32 Diffusion2D-PT-D40N050-CTLFireability-11 194058 m, 8545 m/sec, 1550187 t fired, .
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42 CTL EXCL 30/337 4/32 Diffusion2D-PT-D40N050-CTLFireability-11 231549 m, 7498 m/sec, 1849707 t fired, .
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42 CTL EXCL 35/337 5/32 Diffusion2D-PT-D40N050-CTLFireability-11 272869 m, 8264 m/sec, 2141783 t fired, .
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42 CTL EXCL 40/337 5/32 Diffusion2D-PT-D40N050-CTLFireability-11 315295 m, 8485 m/sec, 2436730 t fired, .
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42 CTL EXCL 45/337 6/32 Diffusion2D-PT-D40N050-CTLFireability-11 356103 m, 8161 m/sec, 2720335 t fired, .
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42 CTL EXCL 50/337 6/32 Diffusion2D-PT-D40N050-CTLFireability-11 395905 m, 7960 m/sec, 3019106 t fired, .
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42 CTL EXCL 60/337 8/32 Diffusion2D-PT-D40N050-CTLFireability-11 474477 m, 7582 m/sec, 3573837 t fired, .
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42 CTL EXCL 65/337 8/32 Diffusion2D-PT-D40N050-CTLFireability-11 513277 m, 7760 m/sec, 3850612 t fired, .
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42 CTL EXCL 70/337 9/32 Diffusion2D-PT-D40N050-CTLFireability-11 549862 m, 7317 m/sec, 4126444 t fired, .
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42 CTL EXCL 75/337 9/32 Diffusion2D-PT-D40N050-CTLFireability-11 590830 m, 8193 m/sec, 4387332 t fired, .
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42 CTL EXCL 80/337 10/32 Diffusion2D-PT-D40N050-CTLFireability-11 629976 m, 7829 m/sec, 4661337 t fired, .
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42 CTL EXCL 85/337 10/32 Diffusion2D-PT-D40N050-CTLFireability-11 669747 m, 7954 m/sec, 4923030 t fired, .
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42 CTL EXCL 90/337 11/32 Diffusion2D-PT-D40N050-CTLFireability-11 710102 m, 8071 m/sec, 5208481 t fired, .
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42 CTL EXCL 95/337 11/32 Diffusion2D-PT-D40N050-CTLFireability-11 752256 m, 8430 m/sec, 5487905 t fired, .
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42 CTL EXCL 100/337 12/32 Diffusion2D-PT-D40N050-CTLFireability-11 794117 m, 8372 m/sec, 5754896 t fired, .
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42 CTL EXCL 105/337 12/32 Diffusion2D-PT-D40N050-CTLFireability-11 834563 m, 8089 m/sec, 6038937 t fired, .
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42 CTL EXCL 110/337 13/32 Diffusion2D-PT-D40N050-CTLFireability-11 875967 m, 8280 m/sec, 6306734 t fired, .
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42 CTL EXCL 115/337 14/32 Diffusion2D-PT-D40N050-CTLFireability-11 915482 m, 7903 m/sec, 6574468 t fired, .
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42 CTL EXCL 120/337 14/32 Diffusion2D-PT-D40N050-CTLFireability-11 957084 m, 8320 m/sec, 6841894 t fired, .
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42 CTL EXCL 135/337 16/32 Diffusion2D-PT-D40N050-CTLFireability-11 1080642 m, 7842 m/sec, 7644413 t fired, .
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42 CTL EXCL 140/337 17/32 Diffusion2D-PT-D40N050-CTLFireability-11 1121861 m, 8243 m/sec, 7923714 t fired, .
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42 CTL EXCL 150/337 18/32 Diffusion2D-PT-D40N050-CTLFireability-11 1199720 m, 7718 m/sec, 8436699 t fired, .
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42 CTL EXCL 155/337 18/32 Diffusion2D-PT-D40N050-CTLFireability-11 1239825 m, 8021 m/sec, 8724001 t fired, .
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42 CTL EXCL 160/337 19/32 Diffusion2D-PT-D40N050-CTLFireability-11 1279390 m, 7913 m/sec, 8974286 t fired, .
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42 CTL EXCL 165/337 20/32 Diffusion2D-PT-D40N050-CTLFireability-11 1322382 m, 8598 m/sec, 9244016 t fired, .
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42 CTL EXCL 170/337 20/32 Diffusion2D-PT-D40N050-CTLFireability-11 1362091 m, 7941 m/sec, 9497825 t fired, .
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42 CTL EXCL 175/337 21/32 Diffusion2D-PT-D40N050-CTLFireability-11 1409314 m, 9444 m/sec, 9778514 t fired, .
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42 CTL EXCL 180/337 21/32 Diffusion2D-PT-D40N050-CTLFireability-11 1443436 m, 6824 m/sec, 10049030 t fired, .
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42 CTL EXCL 185/337 22/32 Diffusion2D-PT-D40N050-CTLFireability-11 1483440 m, 8000 m/sec, 10313441 t fired, .
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42 CTL EXCL 190/337 23/32 Diffusion2D-PT-D40N050-CTLFireability-11 1523767 m, 8065 m/sec, 10582888 t fired, .
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42 CTL EXCL 195/337 24/32 Diffusion2D-PT-D40N050-CTLFireability-11 1563835 m, 8013 m/sec, 10846252 t fired, .
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42 CTL EXCL 205/337 25/32 Diffusion2D-PT-D40N050-CTLFireability-11 1644726 m, 8081 m/sec, 11367648 t fired, .
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42 CTL EXCL 210/337 26/32 Diffusion2D-PT-D40N050-CTLFireability-11 1685375 m, 8129 m/sec, 11632403 t fired, .
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36 CTL EXCL 105/347 20/32 Diffusion2D-PT-D40N050-CTLFireability-09 1338731 m, 12746 m/sec, 6592857 t fired, .
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36 CTL EXCL 110/347 21/32 Diffusion2D-PT-D40N050-CTLFireability-09 1400441 m, 12342 m/sec, 6898779 t fired, .
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36 CTL EXCL 115/347 22/32 Diffusion2D-PT-D40N050-CTLFireability-09 1464042 m, 12720 m/sec, 7213512 t fired, .
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36 CTL EXCL 155/347 31/32 Diffusion2D-PT-D40N050-CTLFireability-09 1952656 m, 12106 m/sec, 9609105 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 90/494 10/32 Diffusion2D-PT-D40N050-CTLFireability-07 681187 m, 7557 m/sec, 5490256 t fired, .
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26 CTL EXCL 95/494 11/32 Diffusion2D-PT-D40N050-CTLFireability-07 719119 m, 7586 m/sec, 5794596 t fired, .
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26 CTL EXCL 100/494 11/32 Diffusion2D-PT-D40N050-CTLFireability-07 757557 m, 7687 m/sec, 6081904 t fired, .
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26 CTL EXCL 105/494 12/32 Diffusion2D-PT-D40N050-CTLFireability-07 797117 m, 7912 m/sec, 6375564 t fired, .
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26 CTL EXCL 115/494 13/32 Diffusion2D-PT-D40N050-CTLFireability-07 873170 m, 7681 m/sec, 6963984 t fired, .
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26 CTL EXCL 120/494 14/32 Diffusion2D-PT-D40N050-CTLFireability-07 911116 m, 7589 m/sec, 7252818 t fired, .
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26 CTL EXCL 125/494 14/32 Diffusion2D-PT-D40N050-CTLFireability-07 950077 m, 7792 m/sec, 7543182 t fired, .
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26 CTL EXCL 130/494 15/32 Diffusion2D-PT-D40N050-CTLFireability-07 988411 m, 7666 m/sec, 7829534 t fired, .
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26 CTL EXCL 140/494 16/32 Diffusion2D-PT-D40N050-CTLFireability-07 1066014 m, 7696 m/sec, 8395508 t fired, .
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lola: FINISHED task # 26 (type EXCL) for Diffusion2D-PT-D40N050-CTLFireability-07
lola: result : true
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Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
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Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 149/2518 27/32 Diffusion2D-PT-D40N050-CTLFireability-00 1721280 m, 14371 m/sec, 8527521 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-03: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-05: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-07: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ true CONJ
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-12: CTL true CTL model checker
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Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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1 CTL EXCL 154/2518 28/32 Diffusion2D-PT-D40N050-CTLFireability-00 1793862 m, 14516 m/sec, 8807497 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-03: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-05: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-07: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ true CONJ
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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1 CTL EXCL 159/2518 30/32 Diffusion2D-PT-D40N050-CTLFireability-00 1868330 m, 14893 m/sec, 9090917 t fired, .
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Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-03: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-05: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-07: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ true CONJ
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 164/2518 31/32 Diffusion2D-PT-D40N050-CTLFireability-00 1937625 m, 13859 m/sec, 9362808 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-03: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-05: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-07: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ true CONJ
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D40N050-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D40N050-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D40N050-CTLFireability-00: CTL unknown AGGR
Diffusion2D-PT-D40N050-CTLFireability-01: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-02: CONJ false state space /EXEF
Diffusion2D-PT-D40N050-CTLFireability-03: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-04: SP ECTL true LTL model checker
Diffusion2D-PT-D40N050-CTLFireability-05: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-06: CTL unknown AGGR
Diffusion2D-PT-D40N050-CTLFireability-07: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-08: CONJ true CONJ
Diffusion2D-PT-D40N050-CTLFireability-09: CTL unknown AGGR
Diffusion2D-PT-D40N050-CTLFireability-10: CTL false CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-11: CTL unknown AGGR
Diffusion2D-PT-D40N050-CTLFireability-12: CTL true CTL model checker
Diffusion2D-PT-D40N050-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D40N050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Diffusion2D-PT-D40N050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819413800226"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D40N050.tgz
mv Diffusion2D-PT-D40N050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;