About the Execution of LoLa+red for Diffusion2D-PT-D05N250
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4041.703 | 130023.00 | 126030.00 | 970.30 | TFFFF?TTFTTTF?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r135-smll-167819413500090.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Diffusion2D-PT-D05N250, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819413500090
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 6.5K Feb 26 03:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 61K Feb 26 03:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 26 03:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 26 03:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 15:57 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:57 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Feb 25 15:57 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:57 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 26 03:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 26 03:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Feb 26 03:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 03:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:57 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:57 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 55K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-00
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-01
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-02
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-03
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-04
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-05
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-06
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-07
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-08
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-09
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-10
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-11
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-12
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-13
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-14
FORMULA_NAME Diffusion2D-PT-D05N250-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678278200384
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Diffusion2D-PT-D05N250
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:23:22] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:23:22] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:23:22] [INFO ] Load time of PNML (sax parser for PT used): 61 ms
[2023-03-08 12:23:22] [INFO ] Transformed 25 places.
[2023-03-08 12:23:22] [INFO ] Transformed 144 transitions.
[2023-03-08 12:23:22] [INFO ] Parsed PT model containing 25 places and 144 transitions and 288 arcs in 167 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 2 formulas.
FORMULA Diffusion2D-PT-D05N250-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Diffusion2D-PT-D05N250-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 21 out of 25 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 16 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
// Phase 1: matrix 144 rows 25 cols
[2023-03-08 12:23:23] [INFO ] Computed 1 place invariants in 11 ms
[2023-03-08 12:23:23] [INFO ] Implicit Places using invariants in 191 ms returned []
[2023-03-08 12:23:23] [INFO ] Invariant cache hit.
[2023-03-08 12:23:23] [INFO ] Implicit Places using invariants and state equation in 123 ms returned []
Implicit Place search using SMT with State Equation took 359 ms to find 0 implicit places.
[2023-03-08 12:23:23] [INFO ] Invariant cache hit.
[2023-03-08 12:23:23] [INFO ] Dead Transitions using invariants and state equation in 132 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 510 ms. Remains : 25/25 places, 144/144 transitions.
Support contains 21 out of 25 places after structural reductions.
[2023-03-08 12:23:23] [INFO ] Flatten gal took : 52 ms
[2023-03-08 12:23:23] [INFO ] Flatten gal took : 16 ms
[2023-03-08 12:23:23] [INFO ] Input system was already deterministic with 144 transitions.
Incomplete random walk after 10042 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=193 ) properties (out of 28) seen :15
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 13) seen :12
Finished Best-First random walk after 72 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=36 )
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 110 edges and 25 vertex of which 22 / 25 are part of one of the 1 SCC in 4 ms
Free SCC test removed 21 places
Ensure Unique test removed 135 transitions
Reduce isomorphic transitions removed 135 transitions.
Applied a total of 1 rules in 10 ms. Remains 4 /25 variables (removed 21) and now considering 9/144 (removed 135) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 4/25 places, 9/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 2 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 11 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 92 edges and 25 vertex of which 21 / 25 are part of one of the 1 SCC in 0 ms
Free SCC test removed 20 places
Ensure Unique test removed 129 transitions
Reduce isomorphic transitions removed 129 transitions.
Applied a total of 1 rules in 2 ms. Remains 5 /25 variables (removed 20) and now considering 15/144 (removed 129) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 5/25 places, 15/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 104 edges and 25 vertex of which 22 / 25 are part of one of the 1 SCC in 0 ms
Free SCC test removed 21 places
Ensure Unique test removed 135 transitions
Reduce isomorphic transitions removed 135 transitions.
Applied a total of 1 rules in 1 ms. Remains 4 /25 variables (removed 21) and now considering 9/144 (removed 135) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 4/25 places, 9/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 82 edges and 25 vertex of which 20 / 25 are part of one of the 1 SCC in 0 ms
Free SCC test removed 19 places
Ensure Unique test removed 127 transitions
Reduce isomorphic transitions removed 127 transitions.
Applied a total of 1 rules in 2 ms. Remains 6 /25 variables (removed 19) and now considering 17/144 (removed 127) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/25 places, 17/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Graph (trivial) has 122 edges and 25 vertex of which 23 / 25 are part of one of the 1 SCC in 1 ms
Free SCC test removed 22 places
Ensure Unique test removed 139 transitions
Reduce isomorphic transitions removed 139 transitions.
Applied a total of 1 rules in 2 ms. Remains 3 /25 variables (removed 22) and now considering 5/144 (removed 139) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 3/25 places, 5/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 144/144 transitions.
Applied a total of 0 rules in 1 ms. Remains 25 /25 variables (removed 0) and now considering 144/144 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 25/25 places, 144/144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Input system was already deterministic with 144 transitions.
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:23:24] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-08 12:23:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 25 places, 144 transitions and 288 arcs took 1 ms.
Total runtime 1805 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Diffusion2D-PT-D05N250
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/360
CTLFireability
FORMULA Diffusion2D-PT-D05N250-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Diffusion2D-PT-D05N250-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678278330407
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/360/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/360/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/360/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 47 (type SKEL/SRCH) for 9 Diffusion2D-PT-D05N250-CTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 47 (type SKEL/SRCH) for Diffusion2D-PT-D05N250-CTLFireability-03
lola: result : true
lola: markings : 250
lola: fired transitions : 249
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 4 (type EXCL) for 3 Diffusion2D-PT-D05N250-CTLFireability-01
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 4 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-01
lola: result : false
lola: markings : 37621
lola: fired transitions : 128351
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 9 Diffusion2D-PT-D05N250-CTLFireability-03
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-03
lola: result : true
lola: markings : 250
lola: fired transitions : 249
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 Diffusion2D-PT-D05N250-CTLFireability-15
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-15
lola: result : true
lola: markings : 74245
lola: fired transitions : 290087
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 Diffusion2D-PT-D05N250-CTLFireability-13
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 4/299 5/32 Diffusion2D-PT-D05N250-CTLFireability-13 1078411 m, 215682 m/sec, 4506774 t fired, .
Time elapsed: 5 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 9/299 9/32 Diffusion2D-PT-D05N250-CTLFireability-13 2167585 m, 217834 m/sec, 9129551 t fired, .
Time elapsed: 10 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 14/299 14/32 Diffusion2D-PT-D05N250-CTLFireability-13 3253770 m, 217237 m/sec, 13728266 t fired, .
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# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 19/299 18/32 Diffusion2D-PT-D05N250-CTLFireability-13 4323827 m, 214011 m/sec, 18263826 t fired, .
Time elapsed: 20 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 55/395 32/32 Diffusion2D-PT-D05N250-CTLFireability-05 7641993 m, 134094 m/sec, 49827982 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 20 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 17 (type EXCL) for 12 Diffusion2D-PT-D05N250-CTLFireability-04
lola: time limit : 437 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-04
lola: result : false
lola: markings : 53019
lola: fired transitions : 152849
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Diffusion2D-PT-D05N250-CTLFireability-00
lola: time limit : 499 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-00
lola: result : true
lola: markings : 75248
lola: fired transitions : 300057
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 Diffusion2D-PT-D05N250-CTLFireability-07
lola: time limit : 583 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-07
lola: result : true
lola: markings : 125002
lola: fired transitions : 654380
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 Diffusion2D-PT-D05N250-CTLFireability-06
lola: time limit : 699 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-06
lola: result : true
lola: markings : 63001
lola: fired transitions : 281129
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 Diffusion2D-PT-D05N250-CTLFireability-14
lola: time limit : 874 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-14
lola: result : false
lola: markings : 251
lola: fired transitions : 506
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 12 Diffusion2D-PT-D05N250-CTLFireability-04
lola: time limit : 1166 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-04
lola: result : false
lola: markings : 31626
lola: fired transitions : 314000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Diffusion2D-PT-D05N250-CTLFireability-02
lola: time limit : 1749 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-00: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ false DISJ
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-14: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/1749 4/32 Diffusion2D-PT-D05N250-CTLFireability-02 759045 m, 151809 m/sec, 5818145 t fired, .
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# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-00: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ false DISJ
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-14: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/1749 7/32 Diffusion2D-PT-D05N250-CTLFireability-02 1642780 m, 176747 m/sec, 12746967 t fired, .
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# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-00: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ false DISJ
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-14: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 14/1749 11/32 Diffusion2D-PT-D05N250-CTLFireability-02 2520956 m, 175635 m/sec, 19504182 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-00: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ false DISJ
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-14: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Diffusion2D-PT-D05N250-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Diffusion2D-PT-D05N250-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Diffusion2D-PT-D05N250-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 19/1749 11/32 Diffusion2D-PT-D05N250-CTLFireability-02 2661462 m, 28101 m/sec, 27230416 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 7 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-02
lola: result : false
lola: markings : 2667126
lola: fired transitions : 34357624
lola: time used : 24.000000
lola: memory pages used : 11
lola: LAUNCH task # 29 (type EXCL) for 28 Diffusion2D-PT-D05N250-CTLFireability-08
lola: time limit : 3475 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for Diffusion2D-PT-D05N250-CTLFireability-08
lola: result : false
lola: markings : 500
lola: fired transitions : 751
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Diffusion2D-PT-D05N250-CTLFireability-00: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-01: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-02: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-03: AXAG false state space /EXEF
Diffusion2D-PT-D05N250-CTLFireability-04: DISJ false DISJ
Diffusion2D-PT-D05N250-CTLFireability-05: CTL unknown AGGR
Diffusion2D-PT-D05N250-CTLFireability-06: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-07: AGEF true tscc_search
Diffusion2D-PT-D05N250-CTLFireability-08: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-10: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-11: CTL true CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-13: CTL unknown AGGR
Diffusion2D-PT-D05N250-CTLFireability-14: CTL false CTL model checker
Diffusion2D-PT-D05N250-CTLFireability-15: CTL true CTL model checker
Time elapsed: 125 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Diffusion2D-PT-D05N250"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Diffusion2D-PT-D05N250, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819413500090"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Diffusion2D-PT-D05N250.tgz
mv Diffusion2D-PT-D05N250 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;