fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r135-smll-167819413300010
Last Updated
May 14, 2023

About the Execution of LoLa+red for Dekker-PT-015

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
680.844 109913.00 120634.00 1234.10 FTFTTFFTFTTFFTTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r135-smll-167819413300010.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Dekker-PT-015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r135-smll-167819413300010
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 7.8K Feb 26 01:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 26 01:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 01:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 26 01:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 15:56 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:56 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 01:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Feb 26 01:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.1K Feb 26 01:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 01:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:56 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:56 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 141K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Dekker-PT-015-CTLFireability-00
FORMULA_NAME Dekker-PT-015-CTLFireability-01
FORMULA_NAME Dekker-PT-015-CTLFireability-02
FORMULA_NAME Dekker-PT-015-CTLFireability-03
FORMULA_NAME Dekker-PT-015-CTLFireability-04
FORMULA_NAME Dekker-PT-015-CTLFireability-05
FORMULA_NAME Dekker-PT-015-CTLFireability-06
FORMULA_NAME Dekker-PT-015-CTLFireability-07
FORMULA_NAME Dekker-PT-015-CTLFireability-08
FORMULA_NAME Dekker-PT-015-CTLFireability-09
FORMULA_NAME Dekker-PT-015-CTLFireability-10
FORMULA_NAME Dekker-PT-015-CTLFireability-11
FORMULA_NAME Dekker-PT-015-CTLFireability-12
FORMULA_NAME Dekker-PT-015-CTLFireability-13
FORMULA_NAME Dekker-PT-015-CTLFireability-14
FORMULA_NAME Dekker-PT-015-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678265269025

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Dekker-PT-015
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 08:47:52] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 08:47:53] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 08:47:53] [INFO ] Load time of PNML (sax parser for PT used): 159 ms
[2023-03-08 08:47:53] [INFO ] Transformed 75 places.
[2023-03-08 08:47:53] [INFO ] Transformed 255 transitions.
[2023-03-08 08:47:53] [INFO ] Found NUPN structural information;
[2023-03-08 08:47:53] [INFO ] Parsed PT model containing 75 places and 255 transitions and 1830 arcs in 333 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Support contains 53 out of 75 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 255/255 transitions.
Applied a total of 0 rules in 31 ms. Remains 75 /75 variables (removed 0) and now considering 255/255 (removed 0) transitions.
[2023-03-08 08:47:53] [INFO ] Flow matrix only has 60 transitions (discarded 195 similar events)
// Phase 1: matrix 60 rows 75 cols
[2023-03-08 08:47:53] [INFO ] Computed 45 place invariants in 13 ms
[2023-03-08 08:47:53] [INFO ] Implicit Places using invariants in 365 ms returned [33, 36, 42, 48, 51, 54, 57, 60, 63, 66, 72]
Discarding 11 places :
Implicit Place search using SMT only with invariants took 428 ms to find 11 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 64/75 places, 255/255 transitions.
Applied a total of 0 rules in 7 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 467 ms. Remains : 64/75 places, 255/255 transitions.
Support contains 53 out of 64 places after structural reductions.
[2023-03-08 08:47:54] [INFO ] Flatten gal took : 89 ms
[2023-03-08 08:47:54] [INFO ] Flatten gal took : 41 ms
[2023-03-08 08:47:54] [INFO ] Input system was already deterministic with 255 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 748 ms. (steps per millisecond=13 ) properties (out of 68) seen :62
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 6) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 08:47:55] [INFO ] Flow matrix only has 60 transitions (discarded 195 similar events)
// Phase 1: matrix 60 rows 64 cols
[2023-03-08 08:47:55] [INFO ] Computed 34 place invariants in 8 ms
[2023-03-08 08:47:55] [INFO ] [Real]Absence check using 30 positive place invariants in 13 ms returned sat
[2023-03-08 08:47:55] [INFO ] [Real]Absence check using 30 positive and 4 generalized place invariants in 2 ms returned sat
[2023-03-08 08:47:55] [INFO ] After 94ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 08:47:55] [INFO ] Flatten gal took : 46 ms
[2023-03-08 08:47:55] [INFO ] Flatten gal took : 39 ms
[2023-03-08 08:47:55] [INFO ] Input system was already deterministic with 255 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 50 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 50 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:55] [INFO ] Flatten gal took : 32 ms
[2023-03-08 08:47:55] [INFO ] Flatten gal took : 32 ms
[2023-03-08 08:47:55] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 19 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 20 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 20 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 15 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 15 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 20 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 14 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 14 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 15 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 16 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 15 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 16 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 17 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 15 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 13 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 15 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 5 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 19 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 14 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 4 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 12 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 11 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 4 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 12 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 3 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 12 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 11 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:56] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:57] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 64/64 places, 255/255 transitions.
Applied a total of 0 rules in 2 ms. Remains 64 /64 variables (removed 0) and now considering 255/255 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 64/64 places, 255/255 transitions.
[2023-03-08 08:47:57] [INFO ] Flatten gal took : 10 ms
[2023-03-08 08:47:57] [INFO ] Flatten gal took : 12 ms
[2023-03-08 08:47:57] [INFO ] Input system was already deterministic with 255 transitions.
[2023-03-08 08:47:57] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:57] [INFO ] Flatten gal took : 13 ms
[2023-03-08 08:47:57] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-08 08:47:57] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 64 places, 255 transitions and 1654 arcs took 3 ms.
Total runtime 4169 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Dekker-PT-015
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA Dekker-PT-015-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Dekker-PT-015-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678265378938

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
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lola: rewrite Frontend/Parser/formula_rewrite.k:328
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lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: RELEASE
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7 CTL EXCL 5/224 1/32 Dekker-PT-015-CTLFireability-02 70441 m, 14088 m/sec, 3618755 t fired, .

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7 CTL EXCL 10/224 1/32 Dekker-PT-015-CTLFireability-02 131074 m, 12126 m/sec, 7633691 t fired, .

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7 CTL EXCL 15/224 1/32 Dekker-PT-015-CTLFireability-02 206374 m, 15060 m/sec, 11925712 t fired, .

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7 CTL EXCL 20/224 2/32 Dekker-PT-015-CTLFireability-02 278528 m, 14430 m/sec, 16652429 t fired, .

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46 CTL EXCL 5/238 1/32 Dekker-PT-015-CTLFireability-15 49193 m, 9838 m/sec, 2766375 t fired, .

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46 CTL EXCL 10/238 1/32 Dekker-PT-015-CTLFireability-15 74985 m, 5158 m/sec, 7771324 t fired, .

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46 CTL EXCL 15/238 1/32 Dekker-PT-015-CTLFireability-15 110954 m, 7193 m/sec, 12195931 t fired, .

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46 CTL EXCL 20/238 1/32 Dekker-PT-015-CTLFireability-15 146436 m, 7096 m/sec, 16459465 t fired, .

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46 CTL EXCL 25/238 1/32 Dekker-PT-015-CTLFireability-15 180257 m, 6764 m/sec, 20688100 t fired, .

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Dekker-PT-015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/238 1/32 Dekker-PT-015-CTLFireability-15 213023 m, 6553 m/sec, 24905550 t fired, .

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Dekker-PT-015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/238 2/32 Dekker-PT-015-CTLFireability-15 245789 m, 6553 m/sec, 29102335 t fired, .

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Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/238 2/32 Dekker-PT-015-CTLFireability-15 278528 m, 6547 m/sec, 33377149 t fired, .

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lola: fired transitions : 34011038
lola: time used : 40.000000
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lola: result : true
lola: markings : 15
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
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lola: result : false
lola: markings : 380
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lola: time used : 0.000000
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lola: result : false
lola: markings : 3
lola: fired transitions : 5
lola: time used : 0.000000
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lola: time limit : 321 sec
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lola: result : true
lola: markings : 1
lola: fired transitions : 2
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lola: markings : 1046
lola: fired transitions : 2324
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 393 sec
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lola: result : false
lola: markings : 3
lola: fired transitions : 9
lola: time used : 0.000000
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lola: time limit : 442 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Dekker-PT-015-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Dekker-PT-015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/442 1/32 Dekker-PT-015-CTLFireability-06 98306 m, 19661 m/sec, 5602881 t fired, .

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Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Dekker-PT-015-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/442 1/32 Dekker-PT-015-CTLFireability-06 196610 m, 19660 m/sec, 11812864 t fired, .

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lola: time used : 14.000000
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Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Dekker-PT-015-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 1/503 1/32 Dekker-PT-015-CTLFireability-04 47287 m, 9457 m/sec, 1014385 t fired, .

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Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Dekker-PT-015-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-01: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
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Dekker-PT-015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 6/503 1/32 Dekker-PT-015-CTLFireability-04 131074 m, 16757 m/sec, 10045153 t fired, .

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Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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Dekker-PT-015-CTLFireability-03: AGEF 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
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Dekker-PT-015-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 11/503 2/32 Dekker-PT-015-CTLFireability-04 244070 m, 22599 m/sec, 19033768 t fired, .

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lola: time used : 13.000000
lola: memory pages used : 2
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lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for Dekker-PT-015-CTLFireability-03
lola: result : true
lola: markings : 10243
lola: fired transitions : 190467
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 Dekker-PT-015-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for Dekker-PT-015-CTLFireability-01
lola: result : true
lola: markings : 30721
lola: fired transitions : 1054722
lola: time used : 1.000000
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lola: time limit : 877 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Dekker-PT-015-CTLFireability-01: AGEF true tscc_search
Dekker-PT-015-CTLFireability-02: CTL false CTL model checker
Dekker-PT-015-CTLFireability-03: AGEF true tscc_search
Dekker-PT-015-CTLFireability-04: CTL true CTL model checker
Dekker-PT-015-CTLFireability-06: CTL false CTL model checker
Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Dekker-PT-015-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 2/877 1/32 Dekker-PT-015-CTLFireability-14 65538 m, 13107 m/sec, 2928796 t fired, .

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Dekker-PT-015-CTLFireability-01: AGEF true tscc_search
Dekker-PT-015-CTLFireability-02: CTL false CTL model checker
Dekker-PT-015-CTLFireability-03: AGEF true tscc_search
Dekker-PT-015-CTLFireability-04: CTL true CTL model checker
Dekker-PT-015-CTLFireability-06: CTL false CTL model checker
Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Dekker-PT-015-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Dekker-PT-015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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43 CTL EXCL 7/877 1/32 Dekker-PT-015-CTLFireability-14 180226 m, 22937 m/sec, 11498198 t fired, .

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lola: FINISHED task # 43 (type EXCL) for Dekker-PT-015-CTLFireability-14
lola: result : true
lola: markings : 278528
lola: fired transitions : 18290575
lola: time used : 11.000000
lola: memory pages used : 2
lola: LAUNCH task # 16 (type EXCL) for 15 Dekker-PT-015-CTLFireability-05
lola: time limit : 1166 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for Dekker-PT-015-CTLFireability-05
lola: result : false
lola: markings : 16535
lola: fired transitions : 189228
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Dekker-PT-015-CTLFireability-00
lola: time limit : 1750 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Dekker-PT-015-CTLFireability-00
lola: result : false
lola: markings : 10532
lola: fired transitions : 85370
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 Dekker-PT-015-CTLFireability-07
lola: time limit : 3500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for Dekker-PT-015-CTLFireability-07
lola: result : true
lola: markings : 43
lola: fired transitions : 110
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Dekker-PT-015-CTLFireability-00: CTL false CTL model checker
Dekker-PT-015-CTLFireability-01: AGEF true tscc_search
Dekker-PT-015-CTLFireability-02: CTL false CTL model checker
Dekker-PT-015-CTLFireability-03: AGEF true tscc_search
Dekker-PT-015-CTLFireability-04: CTL true CTL model checker
Dekker-PT-015-CTLFireability-05: CTL false CTL model checker
Dekker-PT-015-CTLFireability-06: CTL false CTL model checker
Dekker-PT-015-CTLFireability-07: CTL true CTL model checker
Dekker-PT-015-CTLFireability-08: CTL false CTL model checker
Dekker-PT-015-CTLFireability-09: CTL true CTL model checker
Dekker-PT-015-CTLFireability-10: CTL true CTL model checker
Dekker-PT-015-CTLFireability-11: CTL false CTL model checker
Dekker-PT-015-CTLFireability-12: CTL false CTL model checker
Dekker-PT-015-CTLFireability-13: CTL true CTL model checker
Dekker-PT-015-CTLFireability-14: CTL true CTL model checker
Dekker-PT-015-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Dekker-PT-015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Dekker-PT-015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r135-smll-167819413300010"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Dekker-PT-015.tgz
mv Dekker-PT-015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;