About the Execution of LoLA for DoubleLock-PT-p3s3
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5404.035 | 3600000.00 | 11287898.00 | 7753.70 | F?FFT?T?F?T??TF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r134-smll-167819413000562.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DoubleLock-PT-p3s3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-167819413000562
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 6.9K Feb 25 14:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 14:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 25 14:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 14:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:02 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:02 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 14:27 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 14:27 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 14:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 25 14:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:02 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:02 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.4M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p3s3-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678562698209
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p3s3
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DoubleLock-PT-p3s3
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DoubleLock-PT-p3s3-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p3s3-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393232 kB
MemFree: 10808740 kB
After kill :
MemTotal: 16393232 kB
MemFree: 16165396 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 128 transitions removed,68 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 68 (type EXCL) for 17 DoubleLock-PT-p3s3-CTLFireability-03
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 68 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-03
lola: result : true
lola: markings : 90
lola: fired transitions : 90
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 DoubleLock-PT-p3s3-CTLFireability-12
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 70 (type FNDP) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 71 (type EQUN) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: try reading problem file /home/mcc/execution/CTLFireability-71.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 2/179 1/32 DoubleLock-PT-p3s3-CTLFireability-12 105934 m, 21186 m/sec, 328323 t fired, .
70 EF FNDP 2/1789 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6583 t fired, 31 attempts, .
71 EF STEQ 2/1789 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 2/1789 1/5 DoubleLock-PT-p3s3-CTLFireability-07 10982 m, 2196 m/sec, 10993 t fired, .
Time elapsed: 21 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 7/179 3/32 DoubleLock-PT-p3s3-CTLFireability-12 395521 m, 57917 m/sec, 1229261 t fired, .
70 EF FNDP 7/1788 0/5 DoubleLock-PT-p3s3-CTLFireability-07 28309 t fired, 181 attempts, .
71 EF STEQ 7/1788 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 7/1788 1/5 DoubleLock-PT-p3s3-CTLFireability-07 42988 m, 6401 m/sec, 42999 t fired, .
Time elapsed: 26 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 12/179 5/32 DoubleLock-PT-p3s3-CTLFireability-12 686126 m, 58121 m/sec, 2133367 t fired, .
70 EF FNDP 12/1783 0/5 DoubleLock-PT-p3s3-CTLFireability-07 49575 t fired, 371 attempts, .
71 EF STEQ 12/1783 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 12/1783 1/5 DoubleLock-PT-p3s3-CTLFireability-07 75041 m, 6410 m/sec, 75052 t fired, .
Time elapsed: 31 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 17/179 7/32 DoubleLock-PT-p3s3-CTLFireability-12 974846 m, 57744 m/sec, 3031607 t fired, .
70 EF FNDP 17/1778 0/5 DoubleLock-PT-p3s3-CTLFireability-07 70599 t fired, 570 attempts, .
71 EF STEQ 17/1778 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 17/1778 1/5 DoubleLock-PT-p3s3-CTLFireability-07 106998 m, 6391 m/sec, 107009 t fired, .
Time elapsed: 36 secs. Pages in use: 8
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 22/179 9/32 DoubleLock-PT-p3s3-CTLFireability-12 1264689 m, 57968 m/sec, 3933337 t fired, .
70 EF FNDP 22/1773 0/5 DoubleLock-PT-p3s3-CTLFireability-07 91521 t fired, 784 attempts, .
71 EF STEQ 22/1773 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 22/1773 1/5 DoubleLock-PT-p3s3-CTLFireability-07 139005 m, 6401 m/sec, 139016 t fired, .
Time elapsed: 41 secs. Pages in use: 10
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 27/179 11/32 DoubleLock-PT-p3s3-CTLFireability-12 1554746 m, 58011 m/sec, 4835736 t fired, .
70 EF FNDP 27/1768 0/5 DoubleLock-PT-p3s3-CTLFireability-07 112471 t fired, 1009 attempts, .
71 EF STEQ 27/1768 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 27/1768 1/5 DoubleLock-PT-p3s3-CTLFireability-07 171107 m, 6420 m/sec, 171118 t fired, .
Time elapsed: 46 secs. Pages in use: 12
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 32/179 12/32 DoubleLock-PT-p3s3-CTLFireability-12 1843627 m, 57776 m/sec, 5734479 t fired, .
70 EF FNDP 32/1763 0/5 DoubleLock-PT-p3s3-CTLFireability-07 133452 t fired, 1235 attempts, .
71 EF STEQ 32/1763 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 32/1763 2/5 DoubleLock-PT-p3s3-CTLFireability-07 203214 m, 6421 m/sec, 203225 t fired, .
Time elapsed: 51 secs. Pages in use: 14
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 37/179 14/32 DoubleLock-PT-p3s3-CTLFireability-12 2132479 m, 57770 m/sec, 6633129 t fired, .
70 EF FNDP 37/1758 0/5 DoubleLock-PT-p3s3-CTLFireability-07 154427 t fired, 1453 attempts, .
71 EF STEQ 37/1758 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 37/1758 2/5 DoubleLock-PT-p3s3-CTLFireability-07 235324 m, 6422 m/sec, 235335 t fired, .
Time elapsed: 56 secs. Pages in use: 16
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 42/179 16/32 DoubleLock-PT-p3s3-CTLFireability-12 2421036 m, 57711 m/sec, 7530862 t fired, .
70 EF FNDP 42/1753 0/5 DoubleLock-PT-p3s3-CTLFireability-07 175451 t fired, 1676 attempts, .
71 EF STEQ 42/1753 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 42/1753 2/5 DoubleLock-PT-p3s3-CTLFireability-07 267460 m, 6427 m/sec, 267471 t fired, .
Time elapsed: 61 secs. Pages in use: 18
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 47/179 18/32 DoubleLock-PT-p3s3-CTLFireability-12 2709313 m, 57655 m/sec, 8427725 t fired, .
70 EF FNDP 47/1748 0/5 DoubleLock-PT-p3s3-CTLFireability-07 196281 t fired, 1917 attempts, .
71 EF STEQ 47/1748 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 47/1748 2/5 DoubleLock-PT-p3s3-CTLFireability-07 299437 m, 6395 m/sec, 299448 t fired, .
Time elapsed: 66 secs. Pages in use: 20
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 52/179 20/32 DoubleLock-PT-p3s3-CTLFireability-12 2996349 m, 57407 m/sec, 9320723 t fired, .
70 EF FNDP 52/1743 0/5 DoubleLock-PT-p3s3-CTLFireability-07 217291 t fired, 2149 attempts, .
71 EF STEQ 52/1743 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 52/1743 2/5 DoubleLock-PT-p3s3-CTLFireability-07 331583 m, 6429 m/sec, 331594 t fired, .
Time elapsed: 71 secs. Pages in use: 22
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 57/179 22/32 DoubleLock-PT-p3s3-CTLFireability-12 3283306 m, 57391 m/sec, 10213482 t fired, .
70 EF FNDP 57/1738 0/5 DoubleLock-PT-p3s3-CTLFireability-07 238378 t fired, 2380 attempts, .
71 EF STEQ 57/1738 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 57/1738 3/5 DoubleLock-PT-p3s3-CTLFireability-07 363749 m, 6433 m/sec, 363760 t fired, .
Time elapsed: 76 secs. Pages in use: 25
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 62/179 24/32 DoubleLock-PT-p3s3-CTLFireability-12 3570046 m, 57348 m/sec, 11105559 t fired, .
70 EF FNDP 62/1733 0/5 DoubleLock-PT-p3s3-CTLFireability-07 259394 t fired, 2622 attempts, .
71 EF STEQ 62/1733 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 62/1733 3/5 DoubleLock-PT-p3s3-CTLFireability-07 395931 m, 6436 m/sec, 395942 t fired, .
Time elapsed: 81 secs. Pages in use: 27
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 67/179 25/32 DoubleLock-PT-p3s3-CTLFireability-12 3854290 m, 56848 m/sec, 11989875 t fired, .
70 EF FNDP 67/1728 0/5 DoubleLock-PT-p3s3-CTLFireability-07 280280 t fired, 2873 attempts, .
71 EF STEQ 67/1728 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 67/1728 3/5 DoubleLock-PT-p3s3-CTLFireability-07 427739 m, 6361 m/sec, 427750 t fired, .
Time elapsed: 86 secs. Pages in use: 28
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 72/179 27/32 DoubleLock-PT-p3s3-CTLFireability-12 4136485 m, 56439 m/sec, 12867815 t fired, .
70 EF FNDP 72/1723 0/5 DoubleLock-PT-p3s3-CTLFireability-07 301263 t fired, 3123 attempts, .
71 EF STEQ 72/1723 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 72/1723 3/5 DoubleLock-PT-p3s3-CTLFireability-07 459661 m, 6384 m/sec, 459673 t fired, .
Time elapsed: 91 secs. Pages in use: 30
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 77/179 29/32 DoubleLock-PT-p3s3-CTLFireability-12 4418337 m, 56370 m/sec, 13744689 t fired, .
70 EF FNDP 77/1718 0/5 DoubleLock-PT-p3s3-CTLFireability-07 322166 t fired, 3371 attempts, .
71 EF STEQ 77/1718 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 77/1718 3/5 DoubleLock-PT-p3s3-CTLFireability-07 491618 m, 6391 m/sec, 491629 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 82/179 31/32 DoubleLock-PT-p3s3-CTLFireability-12 4700466 m, 56425 m/sec, 14622421 t fired, .
70 EF FNDP 82/1713 0/5 DoubleLock-PT-p3s3-CTLFireability-07 343032 t fired, 3622 attempts, .
71 EF STEQ 82/1713 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 82/1713 3/5 DoubleLock-PT-p3s3-CTLFireability-07 523720 m, 6420 m/sec, 523731 t fired, .
Time elapsed: 101 secs. Pages in use: 34
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 57 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 87/1708 0/5 DoubleLock-PT-p3s3-CTLFireability-07 364066 t fired, 3872 attempts, .
71 EF STEQ 87/1708 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 87/1708 4/5 DoubleLock-PT-p3s3-CTLFireability-07 555750 m, 6406 m/sec, 555761 t fired, .
Time elapsed: 106 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 66 (type EXCL) for 65 DoubleLock-PT-p3s3-CTLFireability-15
lola: time limit : 183 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 5/183 5/32 DoubleLock-PT-p3s3-CTLFireability-15 663166 m, 132633 m/sec, 663267 t fired, .
70 EF FNDP 92/1703 0/5 DoubleLock-PT-p3s3-CTLFireability-07 385137 t fired, 4132 attempts, .
71 EF STEQ 92/1703 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 92/1703 4/5 DoubleLock-PT-p3s3-CTLFireability-07 588047 m, 6459 m/sec, 588058 t fired, .
Time elapsed: 111 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 10/183 9/32 DoubleLock-PT-p3s3-CTLFireability-15 1322752 m, 131917 m/sec, 1322853 t fired, .
70 EF FNDP 97/1698 0/5 DoubleLock-PT-p3s3-CTLFireability-07 406219 t fired, 4389 attempts, .
71 EF STEQ 97/1698 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 97/1698 4/5 DoubleLock-PT-p3s3-CTLFireability-07 620272 m, 6445 m/sec, 620283 t fired, .
Time elapsed: 116 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 15/183 13/32 DoubleLock-PT-p3s3-CTLFireability-15 1979010 m, 131251 m/sec, 1979112 t fired, .
70 EF FNDP 102/1693 0/5 DoubleLock-PT-p3s3-CTLFireability-07 427111 t fired, 4644 attempts, .
71 EF STEQ 102/1693 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 102/1693 4/5 DoubleLock-PT-p3s3-CTLFireability-07 652279 m, 6401 m/sec, 652290 t fired, .
Time elapsed: 121 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 20/183 18/32 DoubleLock-PT-p3s3-CTLFireability-15 2625323 m, 129262 m/sec, 2625424 t fired, .
70 EF FNDP 107/1688 0/5 DoubleLock-PT-p3s3-CTLFireability-07 447928 t fired, 4906 attempts, .
71 EF STEQ 107/1688 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 107/1688 4/5 DoubleLock-PT-p3s3-CTLFireability-07 684365 m, 6417 m/sec, 684376 t fired, .
Time elapsed: 126 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 25/183 22/32 DoubleLock-PT-p3s3-CTLFireability-15 3269631 m, 128861 m/sec, 3269733 t fired, .
70 EF FNDP 112/1683 0/5 DoubleLock-PT-p3s3-CTLFireability-07 468852 t fired, 5163 attempts, .
71 EF STEQ 112/1683 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 112/1683 5/5 DoubleLock-PT-p3s3-CTLFireability-07 716367 m, 6400 m/sec, 716378 t fired, .
Time elapsed: 131 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 30/183 26/32 DoubleLock-PT-p3s3-CTLFireability-15 3913098 m, 128693 m/sec, 3913199 t fired, .
70 EF FNDP 117/1678 0/5 DoubleLock-PT-p3s3-CTLFireability-07 489739 t fired, 5423 attempts, .
71 EF STEQ 117/1678 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 117/1678 5/5 DoubleLock-PT-p3s3-CTLFireability-07 748301 m, 6386 m/sec, 748312 t fired, .
Time elapsed: 136 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 35/183 30/32 DoubleLock-PT-p3s3-CTLFireability-15 4552333 m, 127847 m/sec, 4552434 t fired, .
70 EF FNDP 122/1673 0/5 DoubleLock-PT-p3s3-CTLFireability-07 510634 t fired, 5682 attempts, .
71 EF STEQ 122/1673 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 122/1673 5/5 DoubleLock-PT-p3s3-CTLFireability-07 780277 m, 6395 m/sec, 780288 t fired, .
Time elapsed: 141 secs. Pages in use: 36
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 66 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 127/1668 0/5 DoubleLock-PT-p3s3-CTLFireability-07 531453 t fired, 5946 attempts, .
71 EF STEQ 127/1668 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 127/1668 5/5 DoubleLock-PT-p3s3-CTLFireability-07 812352 m, 6415 m/sec, 812363 t fired, .
Time elapsed: 146 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 DoubleLock-PT-p3s3-CTLFireability-11
lola: time limit : 191 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 3 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/191 5/32 DoubleLock-PT-p3s3-CTLFireability-11 655428 m, 131085 m/sec, 655532 t fired, .
70 EF FNDP 132/1663 0/5 DoubleLock-PT-p3s3-CTLFireability-07 552440 t fired, 6220 attempts, .
71 EF STEQ 132/1663 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
73 EF SRCH 132/1663 5/5 DoubleLock-PT-p3s3-CTLFireability-07 844732 m, 6476 m/sec, 844743 t fired, .
Time elapsed: 151 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 73 (type SRCH) for DoubleLock-PT-p3s3-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 6 0 0 3 0 0 0
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/191 9/32 DoubleLock-PT-p3s3-CTLFireability-11 1300811 m, 129076 m/sec, 1300915 t fired, .
70 EF FNDP 137/1658 0/5 DoubleLock-PT-p3s3-CTLFireability-07 573377 t fired, 6483 attempts, .
71 EF STEQ 137/1658 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 156 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 75 (type FNDP) for 3 DoubleLock-PT-p3s3-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type FNDP) for DoubleLock-PT-p3s3-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 15/215 13/32 DoubleLock-PT-p3s3-CTLFireability-11 1942325 m, 128302 m/sec, 1942429 t fired, .
70 EF FNDP 142/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 594056 t fired, 6749 attempts, .
71 EF STEQ 142/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 161 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 20/215 17/32 DoubleLock-PT-p3s3-CTLFireability-11 2581799 m, 127894 m/sec, 2581903 t fired, .
70 EF FNDP 147/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 614724 t fired, 7013 attempts, .
71 EF STEQ 147/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 166 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 25/215 21/32 DoubleLock-PT-p3s3-CTLFireability-11 3219515 m, 127543 m/sec, 3219620 t fired, .
70 EF FNDP 152/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 635416 t fired, 7282 attempts, .
71 EF STEQ 152/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 171 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 30/215 26/32 DoubleLock-PT-p3s3-CTLFireability-11 3855588 m, 127214 m/sec, 3855692 t fired, .
70 EF FNDP 157/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 656114 t fired, 7555 attempts, .
71 EF STEQ 157/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 176 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 35/215 30/32 DoubleLock-PT-p3s3-CTLFireability-11 4488883 m, 126659 m/sec, 4488987 t fired, .
70 EF FNDP 162/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 676945 t fired, 7818 attempts, .
71 EF STEQ 162/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 181 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 3 2 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 167/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 697675 t fired, 8088 attempts, .
71 EF STEQ 167/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 186 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 40 DoubleLock-PT-p3s3-CTLFireability-08
lola: time limit : 227 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-08
lola: result : false
lola: markings : 34
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 DoubleLock-PT-p3s3-CTLFireability-06
lola: time limit : 262 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-06
lola: result : true
lola: markings : 42
lola: fired transitions : 84
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 DoubleLock-PT-p3s3-CTLFireability-04
lola: time limit : 284 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-04
lola: result : true
lola: markings : 34
lola: fired transitions : 102
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 14 DoubleLock-PT-p3s3-CTLFireability-02
lola: time limit : 310 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-02
lola: result : false
lola: markings : 33
lola: fired transitions : 69
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 341 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 172/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 718372 t fired, 8368 attempts, .
71 EF STEQ 172/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 5/341 1/32 DoubleLock-PT-p3s3-CTLFireability-07 39296 m, 7859 m/sec, 39328 t fired, .
Time elapsed: 191 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 177/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 739186 t fired, 8647 attempts, .
71 EF STEQ 177/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 10/341 1/32 DoubleLock-PT-p3s3-CTLFireability-07 79203 m, 7981 m/sec, 79235 t fired, .
Time elapsed: 196 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 182/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 760009 t fired, 8919 attempts, .
71 EF STEQ 182/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 15/341 1/32 DoubleLock-PT-p3s3-CTLFireability-07 119085 m, 7976 m/sec, 119117 t fired, .
Time elapsed: 201 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 187/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 781103 t fired, 9209 attempts, .
71 EF STEQ 187/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 20/341 1/32 DoubleLock-PT-p3s3-CTLFireability-07 159168 m, 8016 m/sec, 159200 t fired, .
Time elapsed: 206 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 192/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 802048 t fired, 9484 attempts, .
71 EF STEQ 192/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 25/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 199418 m, 8050 m/sec, 199450 t fired, .
Time elapsed: 211 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 197/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 822902 t fired, 9763 attempts, .
71 EF STEQ 197/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 30/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 239766 m, 8069 m/sec, 239798 t fired, .
Time elapsed: 216 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 202/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 843760 t fired, 10037 attempts, .
71 EF STEQ 202/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 35/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 279947 m, 8036 m/sec, 279979 t fired, .
Time elapsed: 221 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 207/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 864488 t fired, 10318 attempts, .
71 EF STEQ 207/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 40/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 320136 m, 8037 m/sec, 320168 t fired, .
Time elapsed: 226 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 212/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 885270 t fired, 10592 attempts, .
71 EF STEQ 212/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 45/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 360001 m, 7973 m/sec, 360033 t fired, .
Time elapsed: 231 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 217/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 906054 t fired, 10867 attempts, .
71 EF STEQ 217/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 50/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 400367 m, 8073 m/sec, 400399 t fired, .
Time elapsed: 236 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 222/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 926884 t fired, 11154 attempts, .
71 EF STEQ 222/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 55/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 440721 m, 8070 m/sec, 440753 t fired, .
Time elapsed: 241 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 227/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 947713 t fired, 11438 attempts, .
71 EF STEQ 227/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 60/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 480980 m, 8051 m/sec, 481012 t fired, .
Time elapsed: 246 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 232/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 968395 t fired, 11727 attempts, .
71 EF STEQ 232/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 65/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 521018 m, 8007 m/sec, 521050 t fired, .
Time elapsed: 251 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 237/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 989236 t fired, 12005 attempts, .
71 EF STEQ 237/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 70/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 561350 m, 8066 m/sec, 561382 t fired, .
Time elapsed: 256 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 242/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1010068 t fired, 12293 attempts, .
71 EF STEQ 242/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 75/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 601783 m, 8086 m/sec, 601815 t fired, .
Time elapsed: 261 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 247/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1030901 t fired, 12584 attempts, .
71 EF STEQ 247/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 80/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 642172 m, 8077 m/sec, 642204 t fired, .
Time elapsed: 266 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 252/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1051612 t fired, 12873 attempts, .
71 EF STEQ 252/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 85/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 682527 m, 8071 m/sec, 682559 t fired, .
Time elapsed: 271 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 257/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1072379 t fired, 13164 attempts, .
71 EF STEQ 257/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 90/341 5/32 DoubleLock-PT-p3s3-CTLFireability-07 722706 m, 8035 m/sec, 722738 t fired, .
Time elapsed: 276 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 262/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1093178 t fired, 13451 attempts, .
71 EF STEQ 262/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 95/341 5/32 DoubleLock-PT-p3s3-CTLFireability-07 762926 m, 8044 m/sec, 762958 t fired, .
Time elapsed: 281 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 267/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1113999 t fired, 13739 attempts, .
71 EF STEQ 267/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 100/341 5/32 DoubleLock-PT-p3s3-CTLFireability-07 803118 m, 8038 m/sec, 803150 t fired, .
Time elapsed: 286 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 272/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1134700 t fired, 14032 attempts, .
71 EF STEQ 272/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 105/341 5/32 DoubleLock-PT-p3s3-CTLFireability-07 843198 m, 8016 m/sec, 843230 t fired, .
Time elapsed: 291 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 277/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1155439 t fired, 14325 attempts, .
71 EF STEQ 277/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 110/341 6/32 DoubleLock-PT-p3s3-CTLFireability-07 883056 m, 7971 m/sec, 883088 t fired, .
Time elapsed: 296 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 282/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1176119 t fired, 14618 attempts, .
71 EF STEQ 282/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 115/341 6/32 DoubleLock-PT-p3s3-CTLFireability-07 923041 m, 7997 m/sec, 923073 t fired, .
Time elapsed: 301 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 287/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1197020 t fired, 14913 attempts, .
71 EF STEQ 287/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 120/341 6/32 DoubleLock-PT-p3s3-CTLFireability-07 963181 m, 8028 m/sec, 963213 t fired, .
Time elapsed: 306 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 292/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1217832 t fired, 15202 attempts, .
71 EF STEQ 292/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 125/341 6/32 DoubleLock-PT-p3s3-CTLFireability-07 1003460 m, 8055 m/sec, 1003492 t fired, .
Time elapsed: 311 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 297/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1238583 t fired, 15493 attempts, .
71 EF STEQ 297/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 130/341 6/32 DoubleLock-PT-p3s3-CTLFireability-07 1043685 m, 8045 m/sec, 1043717 t fired, .
Time elapsed: 316 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 302/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1259309 t fired, 15791 attempts, .
71 EF STEQ 302/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 135/341 7/32 DoubleLock-PT-p3s3-CTLFireability-07 1083866 m, 8036 m/sec, 1083898 t fired, .
Time elapsed: 321 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 307/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1280109 t fired, 16088 attempts, .
71 EF STEQ 307/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 140/341 7/32 DoubleLock-PT-p3s3-CTLFireability-07 1124013 m, 8029 m/sec, 1124045 t fired, .
Time elapsed: 326 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 312/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1300941 t fired, 16376 attempts, .
71 EF STEQ 312/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 145/341 7/32 DoubleLock-PT-p3s3-CTLFireability-07 1164218 m, 8041 m/sec, 1164250 t fired, .
Time elapsed: 331 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 317/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1321794 t fired, 16666 attempts, .
71 EF STEQ 317/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 150/341 7/32 DoubleLock-PT-p3s3-CTLFireability-07 1204478 m, 8052 m/sec, 1204510 t fired, .
Time elapsed: 336 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 322/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1342587 t fired, 16959 attempts, .
71 EF STEQ 322/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 155/341 8/32 DoubleLock-PT-p3s3-CTLFireability-07 1244719 m, 8048 m/sec, 1244751 t fired, .
Time elapsed: 341 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 327/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1363216 t fired, 17254 attempts, .
71 EF STEQ 327/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 160/341 8/32 DoubleLock-PT-p3s3-CTLFireability-07 1284834 m, 8023 m/sec, 1284866 t fired, .
Time elapsed: 346 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 332/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1383893 t fired, 17548 attempts, .
71 EF STEQ 332/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 165/341 8/32 DoubleLock-PT-p3s3-CTLFireability-07 1325094 m, 8052 m/sec, 1325126 t fired, .
Time elapsed: 351 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 337/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1404506 t fired, 17841 attempts, .
71 EF STEQ 337/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 170/341 8/32 DoubleLock-PT-p3s3-CTLFireability-07 1365473 m, 8075 m/sec, 1365505 t fired, .
Time elapsed: 356 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 342/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1425292 t fired, 18137 attempts, .
71 EF STEQ 342/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 175/341 9/32 DoubleLock-PT-p3s3-CTLFireability-07 1405825 m, 8070 m/sec, 1405857 t fired, .
Time elapsed: 361 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 347/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1446071 t fired, 18430 attempts, .
71 EF STEQ 347/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 180/341 9/32 DoubleLock-PT-p3s3-CTLFireability-07 1446219 m, 8078 m/sec, 1446251 t fired, .
Time elapsed: 366 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 352/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1466813 t fired, 18723 attempts, .
71 EF STEQ 352/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 185/341 9/32 DoubleLock-PT-p3s3-CTLFireability-07 1486633 m, 8082 m/sec, 1486665 t fired, .
Time elapsed: 371 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 357/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1487537 t fired, 19017 attempts, .
71 EF STEQ 357/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 190/341 9/32 DoubleLock-PT-p3s3-CTLFireability-07 1527029 m, 8079 m/sec, 1527061 t fired, .
Time elapsed: 376 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 362/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1508313 t fired, 19324 attempts, .
71 EF STEQ 362/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 195/341 9/32 DoubleLock-PT-p3s3-CTLFireability-07 1567497 m, 8093 m/sec, 1567529 t fired, .
Time elapsed: 381 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 367/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1529094 t fired, 19623 attempts, .
71 EF STEQ 367/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 200/341 10/32 DoubleLock-PT-p3s3-CTLFireability-07 1607839 m, 8068 m/sec, 1607871 t fired, .
Time elapsed: 386 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 372/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1549798 t fired, 19931 attempts, .
71 EF STEQ 372/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 205/341 10/32 DoubleLock-PT-p3s3-CTLFireability-07 1648218 m, 8075 m/sec, 1648250 t fired, .
Time elapsed: 391 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 377/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1570527 t fired, 20240 attempts, .
71 EF STEQ 377/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 210/341 10/32 DoubleLock-PT-p3s3-CTLFireability-07 1688670 m, 8090 m/sec, 1688702 t fired, .
Time elapsed: 396 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 382/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1591253 t fired, 20546 attempts, .
71 EF STEQ 382/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 215/341 10/32 DoubleLock-PT-p3s3-CTLFireability-07 1729077 m, 8081 m/sec, 1729109 t fired, .
Time elapsed: 401 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 387/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1611995 t fired, 20861 attempts, .
71 EF STEQ 387/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 220/341 11/32 DoubleLock-PT-p3s3-CTLFireability-07 1769575 m, 8099 m/sec, 1769607 t fired, .
Time elapsed: 406 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 392/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1632775 t fired, 21167 attempts, .
71 EF STEQ 392/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 225/341 11/32 DoubleLock-PT-p3s3-CTLFireability-07 1810150 m, 8115 m/sec, 1810182 t fired, .
Time elapsed: 411 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 397/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1653426 t fired, 21471 attempts, .
71 EF STEQ 397/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 230/341 11/32 DoubleLock-PT-p3s3-CTLFireability-07 1850904 m, 8150 m/sec, 1850936 t fired, .
Time elapsed: 416 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 402/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1673952 t fired, 21777 attempts, .
71 EF STEQ 402/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 235/341 11/32 DoubleLock-PT-p3s3-CTLFireability-07 1891708 m, 8160 m/sec, 1891740 t fired, .
Time elapsed: 421 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 407/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1694641 t fired, 22074 attempts, .
71 EF STEQ 407/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 240/341 12/32 DoubleLock-PT-p3s3-CTLFireability-07 1932601 m, 8178 m/sec, 1932633 t fired, .
Time elapsed: 426 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 412/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1715328 t fired, 22381 attempts, .
71 EF STEQ 412/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 245/341 12/32 DoubleLock-PT-p3s3-CTLFireability-07 1973511 m, 8182 m/sec, 1973543 t fired, .
Time elapsed: 431 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 417/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1736025 t fired, 22674 attempts, .
71 EF STEQ 417/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 250/341 12/32 DoubleLock-PT-p3s3-CTLFireability-07 2014433 m, 8184 m/sec, 2014465 t fired, .
Time elapsed: 436 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 422/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1756707 t fired, 22982 attempts, .
71 EF STEQ 422/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 255/341 12/32 DoubleLock-PT-p3s3-CTLFireability-07 2055210 m, 8155 m/sec, 2055242 t fired, .
Time elapsed: 441 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 427/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1777386 t fired, 23288 attempts, .
71 EF STEQ 427/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 260/341 12/32 DoubleLock-PT-p3s3-CTLFireability-07 2096037 m, 8165 m/sec, 2096069 t fired, .
Time elapsed: 446 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 432/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1798052 t fired, 23590 attempts, .
71 EF STEQ 432/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 265/341 13/32 DoubleLock-PT-p3s3-CTLFireability-07 2136898 m, 8172 m/sec, 2136930 t fired, .
Time elapsed: 451 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 437/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1818681 t fired, 23896 attempts, .
71 EF STEQ 437/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 270/341 13/32 DoubleLock-PT-p3s3-CTLFireability-07 2177757 m, 8171 m/sec, 2177789 t fired, .
Time elapsed: 456 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 442/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1839345 t fired, 24204 attempts, .
71 EF STEQ 442/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 275/341 13/32 DoubleLock-PT-p3s3-CTLFireability-07 2218673 m, 8183 m/sec, 2218705 t fired, .
Time elapsed: 461 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 447/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1860102 t fired, 24512 attempts, .
71 EF STEQ 447/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 280/341 13/32 DoubleLock-PT-p3s3-CTLFireability-07 2259564 m, 8178 m/sec, 2259596 t fired, .
Time elapsed: 466 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 452/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1880752 t fired, 24822 attempts, .
71 EF STEQ 452/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 285/341 14/32 DoubleLock-PT-p3s3-CTLFireability-07 2300384 m, 8164 m/sec, 2300416 t fired, .
Time elapsed: 471 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 457/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1901442 t fired, 25128 attempts, .
71 EF STEQ 457/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 290/341 14/32 DoubleLock-PT-p3s3-CTLFireability-07 2341291 m, 8181 m/sec, 2341323 t fired, .
Time elapsed: 476 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 462/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1922179 t fired, 25439 attempts, .
71 EF STEQ 462/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 295/341 14/32 DoubleLock-PT-p3s3-CTLFireability-07 2382126 m, 8167 m/sec, 2382158 t fired, .
Time elapsed: 481 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 467/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1942930 t fired, 25745 attempts, .
71 EF STEQ 467/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 300/341 14/32 DoubleLock-PT-p3s3-CTLFireability-07 2422945 m, 8163 m/sec, 2422977 t fired, .
Time elapsed: 486 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 472/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1963509 t fired, 26068 attempts, .
71 EF STEQ 472/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 305/341 15/32 DoubleLock-PT-p3s3-CTLFireability-07 2463850 m, 8181 m/sec, 2463882 t fired, .
Time elapsed: 491 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 477/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 1984199 t fired, 26383 attempts, .
71 EF STEQ 477/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 310/341 15/32 DoubleLock-PT-p3s3-CTLFireability-07 2504817 m, 8193 m/sec, 2504849 t fired, .
Time elapsed: 496 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 482/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2005032 t fired, 26681 attempts, .
71 EF STEQ 482/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 315/341 15/32 DoubleLock-PT-p3s3-CTLFireability-07 2545773 m, 8191 m/sec, 2545805 t fired, .
Time elapsed: 501 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 487/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2025806 t fired, 26997 attempts, .
71 EF STEQ 487/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 320/341 15/32 DoubleLock-PT-p3s3-CTLFireability-07 2586706 m, 8186 m/sec, 2586739 t fired, .
Time elapsed: 506 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 492/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2046573 t fired, 27310 attempts, .
71 EF STEQ 492/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 325/341 16/32 DoubleLock-PT-p3s3-CTLFireability-07 2627599 m, 8178 m/sec, 2627631 t fired, .
Time elapsed: 511 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 497/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2067409 t fired, 27621 attempts, .
71 EF STEQ 497/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 330/341 16/32 DoubleLock-PT-p3s3-CTLFireability-07 2668489 m, 8178 m/sec, 2668521 t fired, .
Time elapsed: 516 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 502/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2088193 t fired, 27925 attempts, .
71 EF STEQ 502/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 335/341 16/32 DoubleLock-PT-p3s3-CTLFireability-07 2709401 m, 8182 m/sec, 2709433 t fired, .
Time elapsed: 521 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 3 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 507/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2108832 t fired, 28235 attempts, .
71 EF STEQ 507/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 340/341 16/32 DoubleLock-PT-p3s3-CTLFireability-07 2750444 m, 8208 m/sec, 2750476 t fired, .
Time elapsed: 526 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 72 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-07 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 2 2 0 3 1 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 512/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2129787 t fired, 28553 attempts, .
71 EF STEQ 512/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 531 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 74 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 341 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 72 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 3069 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 517/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2150607 t fired, 28864 attempts, .
71 EF STEQ 517/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 5/3069 1/5 DoubleLock-PT-p3s3-CTLFireability-07 39657 m, -542157 m/sec, 39689 t fired, .
74 EFEG EXCL 5/341 1/32 DoubleLock-PT-p3s3-CTLFireability-07 7523 m, 1504 m/sec, 7522 t fired, .
Time elapsed: 536 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 522/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2171416 t fired, 29172 attempts, .
71 EF STEQ 522/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 10/3069 1/5 DoubleLock-PT-p3s3-CTLFireability-07 79960 m, 8060 m/sec, 79992 t fired, .
74 EFEG EXCL 10/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 15125 m, 1520 m/sec, 15124 t fired, .
Time elapsed: 541 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 527/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2192199 t fired, 29488 attempts, .
71 EF STEQ 527/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 15/3069 1/5 DoubleLock-PT-p3s3-CTLFireability-07 120255 m, 8059 m/sec, 120287 t fired, .
74 EFEG EXCL 15/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 22729 m, 1520 m/sec, 22728 t fired, .
Time elapsed: 546 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 532/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2213005 t fired, 29805 attempts, .
71 EF STEQ 532/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 20/3069 1/5 DoubleLock-PT-p3s3-CTLFireability-07 160602 m, 8069 m/sec, 160634 t fired, .
74 EFEG EXCL 20/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 30346 m, 1523 m/sec, 30345 t fired, .
Time elapsed: 551 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 537/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2233743 t fired, 30123 attempts, .
71 EF STEQ 537/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 25/3069 2/5 DoubleLock-PT-p3s3-CTLFireability-07 200873 m, 8054 m/sec, 200905 t fired, .
74 EFEG EXCL 25/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 37961 m, 1523 m/sec, 37960 t fired, .
Time elapsed: 556 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 542/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2254466 t fired, 30440 attempts, .
71 EF STEQ 542/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 30/3069 2/5 DoubleLock-PT-p3s3-CTLFireability-07 241108 m, 8047 m/sec, 241140 t fired, .
74 EFEG EXCL 30/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 45574 m, 1522 m/sec, 45573 t fired, .
Time elapsed: 561 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 547/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2275103 t fired, 30768 attempts, .
71 EF STEQ 547/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 35/3069 2/5 DoubleLock-PT-p3s3-CTLFireability-07 281298 m, 8038 m/sec, 281330 t fired, .
74 EFEG EXCL 35/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 53193 m, 1523 m/sec, 53192 t fired, .
Time elapsed: 566 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 552/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2295787 t fired, 31083 attempts, .
71 EF STEQ 552/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 40/3069 2/5 DoubleLock-PT-p3s3-CTLFireability-07 321461 m, 8032 m/sec, 321493 t fired, .
74 EFEG EXCL 40/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 60770 m, 1515 m/sec, 60769 t fired, .
Time elapsed: 571 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 557/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2316476 t fired, 31408 attempts, .
71 EF STEQ 557/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 45/3069 3/5 DoubleLock-PT-p3s3-CTLFireability-07 361569 m, 8021 m/sec, 361601 t fired, .
74 EFEG EXCL 45/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 68317 m, 1509 m/sec, 68316 t fired, .
Time elapsed: 576 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 562/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2337252 t fired, 31726 attempts, .
71 EF STEQ 562/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 50/3069 3/5 DoubleLock-PT-p3s3-CTLFireability-07 401864 m, 8059 m/sec, 401896 t fired, .
74 EFEG EXCL 50/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 75931 m, 1522 m/sec, 75930 t fired, .
Time elapsed: 581 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 567/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2358008 t fired, 32051 attempts, .
71 EF STEQ 567/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 55/3069 3/5 DoubleLock-PT-p3s3-CTLFireability-07 442117 m, 8050 m/sec, 442149 t fired, .
74 EFEG EXCL 55/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 83489 m, 1511 m/sec, 83488 t fired, .
Time elapsed: 586 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 572/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2378801 t fired, 32373 attempts, .
71 EF STEQ 572/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 60/3069 3/5 DoubleLock-PT-p3s3-CTLFireability-07 482335 m, 8043 m/sec, 482367 t fired, .
74 EFEG EXCL 60/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 91050 m, 1512 m/sec, 91049 t fired, .
Time elapsed: 591 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 577/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2399620 t fired, 32691 attempts, .
71 EF STEQ 577/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 65/3069 3/5 DoubleLock-PT-p3s3-CTLFireability-07 522663 m, 8065 m/sec, 522695 t fired, .
74 EFEG EXCL 65/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 98607 m, 1511 m/sec, 98606 t fired, .
Time elapsed: 596 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 582/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2420343 t fired, 33012 attempts, .
71 EF STEQ 582/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 70/3069 4/5 DoubleLock-PT-p3s3-CTLFireability-07 562755 m, 8018 m/sec, 562787 t fired, .
74 EFEG EXCL 70/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 106157 m, 1510 m/sec, 106156 t fired, .
Time elapsed: 601 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 587/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2441125 t fired, 33329 attempts, .
71 EF STEQ 587/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 75/3069 4/5 DoubleLock-PT-p3s3-CTLFireability-07 602927 m, 8034 m/sec, 602959 t fired, .
74 EFEG EXCL 75/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 113747 m, 1518 m/sec, 113746 t fired, .
Time elapsed: 606 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 592/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2461915 t fired, 33657 attempts, .
71 EF STEQ 592/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 80/3069 4/5 DoubleLock-PT-p3s3-CTLFireability-07 643265 m, 8067 m/sec, 643297 t fired, .
74 EFEG EXCL 80/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 121321 m, 1514 m/sec, 121320 t fired, .
Time elapsed: 611 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 597/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2482785 t fired, 33974 attempts, .
71 EF STEQ 597/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 85/3069 4/5 DoubleLock-PT-p3s3-CTLFireability-07 683501 m, 8047 m/sec, 683533 t fired, .
74 EFEG EXCL 85/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 128890 m, 1513 m/sec, 128889 t fired, .
Time elapsed: 616 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 602/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2503641 t fired, 34287 attempts, .
71 EF STEQ 602/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 90/3069 5/5 DoubleLock-PT-p3s3-CTLFireability-07 723765 m, 8052 m/sec, 723797 t fired, .
74 EFEG EXCL 90/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 136477 m, 1517 m/sec, 136476 t fired, .
Time elapsed: 621 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 607/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2524408 t fired, 34607 attempts, .
71 EF STEQ 607/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 95/3069 5/5 DoubleLock-PT-p3s3-CTLFireability-07 764005 m, 8048 m/sec, 764037 t fired, .
74 EFEG EXCL 95/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 144070 m, 1518 m/sec, 144069 t fired, .
Time elapsed: 626 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 612/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2545201 t fired, 34923 attempts, .
71 EF STEQ 612/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 100/3069 5/5 DoubleLock-PT-p3s3-CTLFireability-07 804266 m, 8052 m/sec, 804299 t fired, .
74 EFEG EXCL 100/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 151650 m, 1516 m/sec, 151649 t fired, .
Time elapsed: 631 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 4 0 3 0 1 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 617/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2566053 t fired, 35248 attempts, .
71 EF STEQ 617/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
72 EF EXCL 105/3069 5/5 DoubleLock-PT-p3s3-CTLFireability-07 844677 m, 8082 m/sec, 844709 t fired, .
74 EFEG EXCL 105/306 1/32 DoubleLock-PT-p3s3-CTLFireability-07 159207 m, 1511 m/sec, 159206 t fired, .
Time elapsed: 636 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 72 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 622/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2586989 t fired, 35569 attempts, .
71 EF STEQ 622/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 110/306 2/32 DoubleLock-PT-p3s3-CTLFireability-07 166747 m, 1508 m/sec, 166746 t fired, .
Time elapsed: 641 secs. Pages in use: 37
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 627/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2608015 t fired, 35899 attempts, .
71 EF STEQ 627/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 115/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 174310 m, 1512 m/sec, 174309 t fired, .
Time elapsed: 646 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 632/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2629035 t fired, 36236 attempts, .
71 EF STEQ 632/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 120/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 181863 m, 1510 m/sec, 181862 t fired, .
Time elapsed: 651 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 637/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2650060 t fired, 36562 attempts, .
71 EF STEQ 637/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 125/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 189421 m, 1511 m/sec, 189420 t fired, .
Time elapsed: 656 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 642/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2671105 t fired, 36880 attempts, .
71 EF STEQ 642/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 130/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 196978 m, 1511 m/sec, 196977 t fired, .
Time elapsed: 661 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 647/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2692179 t fired, 37211 attempts, .
71 EF STEQ 647/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 135/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 204557 m, 1515 m/sec, 204556 t fired, .
Time elapsed: 666 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 652/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2713245 t fired, 37537 attempts, .
71 EF STEQ 652/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 140/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 212135 m, 1515 m/sec, 212134 t fired, .
Time elapsed: 671 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 657/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2734341 t fired, 37855 attempts, .
71 EF STEQ 657/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 145/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 219713 m, 1515 m/sec, 219712 t fired, .
Time elapsed: 676 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 662/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2755427 t fired, 38184 attempts, .
71 EF STEQ 662/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 150/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 227247 m, 1506 m/sec, 227246 t fired, .
Time elapsed: 681 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 667/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2776503 t fired, 38509 attempts, .
71 EF STEQ 667/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 155/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 234793 m, 1509 m/sec, 234792 t fired, .
Time elapsed: 686 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 672/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2797523 t fired, 38841 attempts, .
71 EF STEQ 672/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 160/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 242330 m, 1507 m/sec, 242329 t fired, .
Time elapsed: 691 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 677/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2818581 t fired, 39166 attempts, .
71 EF STEQ 677/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 165/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 249883 m, 1510 m/sec, 249882 t fired, .
Time elapsed: 696 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 682/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2839646 t fired, 39497 attempts, .
71 EF STEQ 682/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 170/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 257442 m, 1511 m/sec, 257441 t fired, .
Time elapsed: 701 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 687/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2860705 t fired, 39833 attempts, .
71 EF STEQ 687/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 175/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 264989 m, 1509 m/sec, 264988 t fired, .
Time elapsed: 706 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 692/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2881849 t fired, 40156 attempts, .
71 EF STEQ 692/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 180/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 272542 m, 1510 m/sec, 272541 t fired, .
Time elapsed: 711 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 697/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2902760 t fired, 40482 attempts, .
71 EF STEQ 697/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 185/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 280090 m, 1509 m/sec, 280089 t fired, .
Time elapsed: 716 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 702/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2923668 t fired, 40808 attempts, .
71 EF STEQ 702/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 190/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 287662 m, 1514 m/sec, 287661 t fired, .
Time elapsed: 721 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 707/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2944691 t fired, 41143 attempts, .
71 EF STEQ 707/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 195/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 295226 m, 1512 m/sec, 295225 t fired, .
Time elapsed: 726 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 712/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2965788 t fired, 41478 attempts, .
71 EF STEQ 712/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 200/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 302766 m, 1508 m/sec, 302765 t fired, .
Time elapsed: 731 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 717/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 2986860 t fired, 41804 attempts, .
71 EF STEQ 717/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 205/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 310317 m, 1510 m/sec, 310316 t fired, .
Time elapsed: 736 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 722/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3007959 t fired, 42130 attempts, .
71 EF STEQ 722/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 210/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 317882 m, 1513 m/sec, 317881 t fired, .
Time elapsed: 741 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 727/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3028866 t fired, 42459 attempts, .
71 EF STEQ 727/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 215/341 2/32 DoubleLock-PT-p3s3-CTLFireability-07 325509 m, 1525 m/sec, 325508 t fired, .
Time elapsed: 746 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 732/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3049800 t fired, 42785 attempts, .
71 EF STEQ 732/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 220/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 333137 m, 1525 m/sec, 333136 t fired, .
Time elapsed: 751 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 737/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3070717 t fired, 43108 attempts, .
71 EF STEQ 737/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 225/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 340766 m, 1525 m/sec, 340765 t fired, .
Time elapsed: 756 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 742/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3091725 t fired, 43442 attempts, .
71 EF STEQ 742/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 230/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 348401 m, 1527 m/sec, 348400 t fired, .
Time elapsed: 761 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 747/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3112841 t fired, 43771 attempts, .
71 EF STEQ 747/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 235/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 356038 m, 1527 m/sec, 356037 t fired, .
Time elapsed: 766 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 752/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3133863 t fired, 44099 attempts, .
71 EF STEQ 752/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 240/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 363673 m, 1527 m/sec, 363672 t fired, .
Time elapsed: 771 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 757/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3154803 t fired, 44436 attempts, .
71 EF STEQ 757/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 245/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 371286 m, 1522 m/sec, 371285 t fired, .
Time elapsed: 776 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 762/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3175669 t fired, 44761 attempts, .
71 EF STEQ 762/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 250/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 378903 m, 1523 m/sec, 378902 t fired, .
Time elapsed: 781 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 767/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3196532 t fired, 45080 attempts, .
71 EF STEQ 767/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 255/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 386514 m, 1522 m/sec, 386513 t fired, .
Time elapsed: 786 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 772/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3217582 t fired, 45410 attempts, .
71 EF STEQ 772/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 260/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 394050 m, 1507 m/sec, 394049 t fired, .
Time elapsed: 791 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 777/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3238651 t fired, 45751 attempts, .
71 EF STEQ 777/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 265/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 401610 m, 1512 m/sec, 401609 t fired, .
Time elapsed: 796 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 782/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3259732 t fired, 46094 attempts, .
71 EF STEQ 782/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 270/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 409163 m, 1510 m/sec, 409162 t fired, .
Time elapsed: 801 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 787/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3280800 t fired, 46420 attempts, .
71 EF STEQ 787/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 275/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 416726 m, 1512 m/sec, 416725 t fired, .
Time elapsed: 806 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 792/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3301875 t fired, 46759 attempts, .
71 EF STEQ 792/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 280/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 424281 m, 1511 m/sec, 424280 t fired, .
Time elapsed: 811 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 797/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3322969 t fired, 47084 attempts, .
71 EF STEQ 797/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 285/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 431841 m, 1512 m/sec, 431840 t fired, .
Time elapsed: 816 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 802/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3344092 t fired, 47417 attempts, .
71 EF STEQ 802/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 290/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 439402 m, 1512 m/sec, 439401 t fired, .
Time elapsed: 821 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 807/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3365187 t fired, 47754 attempts, .
71 EF STEQ 807/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 295/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 446958 m, 1511 m/sec, 446957 t fired, .
Time elapsed: 826 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 812/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3386332 t fired, 48084 attempts, .
71 EF STEQ 812/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 300/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 454513 m, 1511 m/sec, 454512 t fired, .
Time elapsed: 831 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 817/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3407445 t fired, 48410 attempts, .
71 EF STEQ 817/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 305/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 462063 m, 1510 m/sec, 462062 t fired, .
Time elapsed: 836 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 822/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3428455 t fired, 48748 attempts, .
71 EF STEQ 822/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 310/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 469606 m, 1508 m/sec, 469605 t fired, .
Time elapsed: 841 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 827/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3449522 t fired, 49076 attempts, .
71 EF STEQ 827/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 315/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 477141 m, 1507 m/sec, 477140 t fired, .
Time elapsed: 846 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 832/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3470639 t fired, 49400 attempts, .
71 EF STEQ 832/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 320/341 3/32 DoubleLock-PT-p3s3-CTLFireability-07 484694 m, 1510 m/sec, 484693 t fired, .
Time elapsed: 851 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 837/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3491741 t fired, 49728 attempts, .
71 EF STEQ 837/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 325/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 492259 m, 1513 m/sec, 492258 t fired, .
Time elapsed: 856 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 842/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3512703 t fired, 50058 attempts, .
71 EF STEQ 842/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 330/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 499873 m, 1522 m/sec, 499872 t fired, .
Time elapsed: 861 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 847/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3533553 t fired, 50390 attempts, .
71 EF STEQ 847/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 335/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 507457 m, 1516 m/sec, 507456 t fired, .
Time elapsed: 866 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 852/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3554465 t fired, 50718 attempts, .
71 EF STEQ 852/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 340/341 4/32 DoubleLock-PT-p3s3-CTLFireability-07 515037 m, 1516 m/sec, 515036 t fired, .
Time elapsed: 871 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 74 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-07 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 2 0 3 1 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-14: EG 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 857/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3575435 t fired, 51046 attempts, .
71 EF STEQ 857/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 876 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 63 (type EXCL) for 62 DoubleLock-PT-p3s3-CTLFireability-14
lola: time limit : 340 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 74 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 2724 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-14
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 862/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3596375 t fired, 51371 attempts, .
71 EF STEQ 862/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 5/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 7474 m, -101512 m/sec, 7473 t fired, .
Time elapsed: 881 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 867/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3617263 t fired, 51712 attempts, .
71 EF STEQ 867/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 10/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 14991 m, 1503 m/sec, 14990 t fired, .
Time elapsed: 886 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 872/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3638169 t fired, 52045 attempts, .
71 EF STEQ 872/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 15/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 22514 m, 1504 m/sec, 22513 t fired, .
Time elapsed: 891 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 877/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3659117 t fired, 52370 attempts, .
71 EF STEQ 877/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 20/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 30051 m, 1507 m/sec, 30050 t fired, .
Time elapsed: 896 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 882/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3680118 t fired, 52702 attempts, .
71 EF STEQ 882/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 25/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 37579 m, 1505 m/sec, 37578 t fired, .
Time elapsed: 901 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 887/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3701037 t fired, 53038 attempts, .
71 EF STEQ 887/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 30/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 45131 m, 1510 m/sec, 45130 t fired, .
Time elapsed: 906 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 892/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3722063 t fired, 53370 attempts, .
71 EF STEQ 892/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 35/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 52693 m, 1512 m/sec, 52692 t fired, .
Time elapsed: 911 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 897/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3743071 t fired, 53705 attempts, .
71 EF STEQ 897/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 40/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 60241 m, 1509 m/sec, 60240 t fired, .
Time elapsed: 916 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 902/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3763980 t fired, 54029 attempts, .
71 EF STEQ 902/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 45/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 67794 m, 1510 m/sec, 67793 t fired, .
Time elapsed: 921 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 907/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3784722 t fired, 54362 attempts, .
71 EF STEQ 907/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 50/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 75358 m, 1512 m/sec, 75357 t fired, .
Time elapsed: 926 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 912/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3805472 t fired, 54689 attempts, .
71 EF STEQ 912/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 55/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 82933 m, 1515 m/sec, 82932 t fired, .
Time elapsed: 931 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 917/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3826251 t fired, 55021 attempts, .
71 EF STEQ 917/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 60/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 90518 m, 1517 m/sec, 90517 t fired, .
Time elapsed: 936 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 922/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3847119 t fired, 55352 attempts, .
71 EF STEQ 922/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 65/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 98099 m, 1516 m/sec, 98098 t fired, .
Time elapsed: 941 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 927/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3868029 t fired, 55681 attempts, .
71 EF STEQ 927/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 70/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 105667 m, 1513 m/sec, 105666 t fired, .
Time elapsed: 946 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 932/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3888926 t fired, 56011 attempts, .
71 EF STEQ 932/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 75/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 113241 m, 1514 m/sec, 113240 t fired, .
Time elapsed: 951 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 937/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3909769 t fired, 56342 attempts, .
71 EF STEQ 937/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 80/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 120997 m, 1551 m/sec, 120996 t fired, .
Time elapsed: 956 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 942/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3930850 t fired, 56679 attempts, .
71 EF STEQ 942/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 85/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 128569 m, 1514 m/sec, 128568 t fired, .
Time elapsed: 961 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 947/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3951978 t fired, 57013 attempts, .
71 EF STEQ 947/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 90/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 136134 m, 1513 m/sec, 136133 t fired, .
Time elapsed: 966 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 952/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3973082 t fired, 57349 attempts, .
71 EF STEQ 952/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 95/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 143705 m, 1514 m/sec, 143704 t fired, .
Time elapsed: 971 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 957/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 3994144 t fired, 57684 attempts, .
71 EF STEQ 957/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 100/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 151203 m, 1499 m/sec, 151202 t fired, .
Time elapsed: 976 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 962/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4015246 t fired, 58016 attempts, .
71 EF STEQ 962/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 105/340 1/5 DoubleLock-PT-p3s3-CTLFireability-07 158663 m, 1492 m/sec, 158662 t fired, .
Time elapsed: 981 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 967/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4036282 t fired, 58350 attempts, .
71 EF STEQ 967/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 110/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 166130 m, 1493 m/sec, 166129 t fired, .
Time elapsed: 986 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 972/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4057381 t fired, 58689 attempts, .
71 EF STEQ 972/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 115/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 173623 m, 1498 m/sec, 173622 t fired, .
Time elapsed: 991 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 977/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4078368 t fired, 59030 attempts, .
71 EF STEQ 977/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 120/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 181101 m, 1495 m/sec, 181100 t fired, .
Time elapsed: 996 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 982/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4099413 t fired, 59371 attempts, .
71 EF STEQ 982/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 125/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 188546 m, 1489 m/sec, 188545 t fired, .
Time elapsed: 1001 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 987/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4120443 t fired, 59712 attempts, .
71 EF STEQ 987/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 130/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 196021 m, 1495 m/sec, 196020 t fired, .
Time elapsed: 1006 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 992/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4141457 t fired, 60053 attempts, .
71 EF STEQ 992/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 135/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 203478 m, 1491 m/sec, 203477 t fired, .
Time elapsed: 1011 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 997/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4162438 t fired, 60393 attempts, .
71 EF STEQ 997/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 140/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 210953 m, 1495 m/sec, 210952 t fired, .
Time elapsed: 1016 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1002/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4183482 t fired, 60730 attempts, .
71 EF STEQ 1002/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 145/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 218409 m, 1491 m/sec, 218408 t fired, .
Time elapsed: 1021 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1007/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4204549 t fired, 61068 attempts, .
71 EF STEQ 1007/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 150/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 225854 m, 1489 m/sec, 225853 t fired, .
Time elapsed: 1026 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1012/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4225583 t fired, 61403 attempts, .
71 EF STEQ 1012/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 155/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 233298 m, 1488 m/sec, 233297 t fired, .
Time elapsed: 1031 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1017/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4246584 t fired, 61750 attempts, .
71 EF STEQ 1017/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 160/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 240742 m, 1488 m/sec, 240741 t fired, .
Time elapsed: 1036 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1022/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4267667 t fired, 62088 attempts, .
71 EF STEQ 1022/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 165/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 248183 m, 1488 m/sec, 248182 t fired, .
Time elapsed: 1041 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1027/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4288765 t fired, 62435 attempts, .
71 EF STEQ 1027/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 170/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 255619 m, 1487 m/sec, 255618 t fired, .
Time elapsed: 1046 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1032/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4309860 t fired, 62780 attempts, .
71 EF STEQ 1032/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 175/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 263053 m, 1486 m/sec, 263052 t fired, .
Time elapsed: 1051 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1037/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4330738 t fired, 63105 attempts, .
71 EF STEQ 1037/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 180/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 270571 m, 1503 m/sec, 270570 t fired, .
Time elapsed: 1056 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1042/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4351548 t fired, 63440 attempts, .
71 EF STEQ 1042/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 185/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 278161 m, 1518 m/sec, 278160 t fired, .
Time elapsed: 1061 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1047/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4372348 t fired, 63764 attempts, .
71 EF STEQ 1047/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 190/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 285751 m, 1518 m/sec, 285750 t fired, .
Time elapsed: 1066 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1052/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4393154 t fired, 64096 attempts, .
71 EF STEQ 1052/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 195/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 293338 m, 1517 m/sec, 293337 t fired, .
Time elapsed: 1071 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1057/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4413916 t fired, 64418 attempts, .
71 EF STEQ 1057/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 200/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 300934 m, 1519 m/sec, 300933 t fired, .
Time elapsed: 1076 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1062/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4434541 t fired, 64753 attempts, .
71 EF STEQ 1062/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 205/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 308522 m, 1517 m/sec, 308521 t fired, .
Time elapsed: 1081 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1067/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4455294 t fired, 65076 attempts, .
71 EF STEQ 1067/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 210/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 316113 m, 1518 m/sec, 316112 t fired, .
Time elapsed: 1086 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1072/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4476112 t fired, 65392 attempts, .
71 EF STEQ 1072/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 215/340 2/5 DoubleLock-PT-p3s3-CTLFireability-07 323681 m, 1513 m/sec, 323680 t fired, .
Time elapsed: 1091 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1077/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4496890 t fired, 65731 attempts, .
71 EF STEQ 1077/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 220/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 331185 m, 1500 m/sec, 331184 t fired, .
Time elapsed: 1096 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1082/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4517727 t fired, 66059 attempts, .
71 EF STEQ 1082/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 225/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 338689 m, 1500 m/sec, 338688 t fired, .
Time elapsed: 1101 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1087/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4538497 t fired, 66398 attempts, .
71 EF STEQ 1087/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 230/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 346199 m, 1502 m/sec, 346198 t fired, .
Time elapsed: 1106 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1092/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4559362 t fired, 66743 attempts, .
71 EF STEQ 1092/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 235/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 353705 m, 1501 m/sec, 353704 t fired, .
Time elapsed: 1111 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1097/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4580245 t fired, 67072 attempts, .
71 EF STEQ 1097/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 240/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 361206 m, 1500 m/sec, 361205 t fired, .
Time elapsed: 1116 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1102/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4601140 t fired, 67407 attempts, .
71 EF STEQ 1102/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 245/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 368679 m, 1494 m/sec, 368678 t fired, .
Time elapsed: 1121 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1107/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4622046 t fired, 67735 attempts, .
71 EF STEQ 1107/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 250/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 376167 m, 1497 m/sec, 376166 t fired, .
Time elapsed: 1126 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1112/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4643179 t fired, 68071 attempts, .
71 EF STEQ 1112/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 255/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 383621 m, 1490 m/sec, 383620 t fired, .
Time elapsed: 1131 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1117/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4664289 t fired, 68401 attempts, .
71 EF STEQ 1117/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 260/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 391070 m, 1489 m/sec, 391069 t fired, .
Time elapsed: 1136 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1122/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4685374 t fired, 68734 attempts, .
71 EF STEQ 1122/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 265/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 398521 m, 1490 m/sec, 398520 t fired, .
Time elapsed: 1141 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1127/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4706492 t fired, 69069 attempts, .
71 EF STEQ 1127/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 270/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 405966 m, 1489 m/sec, 405965 t fired, .
Time elapsed: 1146 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1132/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4727577 t fired, 69404 attempts, .
71 EF STEQ 1132/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 275/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 413409 m, 1488 m/sec, 413408 t fired, .
Time elapsed: 1151 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1137/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4748604 t fired, 69745 attempts, .
71 EF STEQ 1137/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 280/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 420851 m, 1488 m/sec, 420850 t fired, .
Time elapsed: 1156 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1142/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4769736 t fired, 70076 attempts, .
71 EF STEQ 1142/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 285/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 428294 m, 1488 m/sec, 428293 t fired, .
Time elapsed: 1161 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1147/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4790836 t fired, 70411 attempts, .
71 EF STEQ 1147/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 290/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 435737 m, 1488 m/sec, 435736 t fired, .
Time elapsed: 1166 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1152/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4811962 t fired, 70745 attempts, .
71 EF STEQ 1152/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 295/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 443177 m, 1488 m/sec, 443176 t fired, .
Time elapsed: 1171 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1157/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4833053 t fired, 71078 attempts, .
71 EF STEQ 1157/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 300/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 450595 m, 1483 m/sec, 450594 t fired, .
Time elapsed: 1176 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1162/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4854029 t fired, 71425 attempts, .
71 EF STEQ 1162/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 305/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 458023 m, 1485 m/sec, 458022 t fired, .
Time elapsed: 1181 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1167/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4875107 t fired, 71772 attempts, .
71 EF STEQ 1167/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 310/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 465454 m, 1486 m/sec, 465453 t fired, .
Time elapsed: 1186 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1172/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4896210 t fired, 72107 attempts, .
71 EF STEQ 1172/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 315/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 472870 m, 1483 m/sec, 472869 t fired, .
Time elapsed: 1191 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1177/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4917369 t fired, 72441 attempts, .
71 EF STEQ 1177/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 320/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 480297 m, 1485 m/sec, 480296 t fired, .
Time elapsed: 1196 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1182/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4938412 t fired, 72773 attempts, .
71 EF STEQ 1182/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 325/340 3/5 DoubleLock-PT-p3s3-CTLFireability-07 487707 m, 1482 m/sec, 487706 t fired, .
Time elapsed: 1201 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1187/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4959469 t fired, 73116 attempts, .
71 EF STEQ 1187/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 330/340 4/5 DoubleLock-PT-p3s3-CTLFireability-07 495141 m, 1486 m/sec, 495140 t fired, .
Time elapsed: 1206 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1192/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 4980392 t fired, 73457 attempts, .
71 EF STEQ 1192/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 335/340 4/5 DoubleLock-PT-p3s3-CTLFireability-07 502606 m, 1493 m/sec, 502605 t fired, .
Time elapsed: 1211 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1197/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5001343 t fired, 73792 attempts, .
71 EF STEQ 1197/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 340/340 4/5 DoubleLock-PT-p3s3-CTLFireability-07 510146 m, 1508 m/sec, 510145 t fired, .
Time elapsed: 1216 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 74 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-07 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 2 0 3 1 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1202/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5022066 t fired, 74135 attempts, .
71 EF STEQ 1202/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 1221 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 59 DoubleLock-PT-p3s3-CTLFireability-13
lola: time limit : 339 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 74 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 2379 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-13
lola: result : true
lola: markings : 34
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1207/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5043136 t fired, 74482 attempts, .
71 EF STEQ 1207/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 5/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 7006 m, -100628 m/sec, 7005 t fired, .
Time elapsed: 1226 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1212/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5064276 t fired, 74818 attempts, .
71 EF STEQ 1212/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 10/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 14034 m, 1405 m/sec, 14033 t fired, .
Time elapsed: 1231 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1217/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5085400 t fired, 75156 attempts, .
71 EF STEQ 1217/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 15/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 21089 m, 1411 m/sec, 21088 t fired, .
Time elapsed: 1236 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1222/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5106535 t fired, 75499 attempts, .
71 EF STEQ 1222/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 20/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 28141 m, 1410 m/sec, 28140 t fired, .
Time elapsed: 1241 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1227/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5127635 t fired, 75844 attempts, .
71 EF STEQ 1227/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 25/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 35187 m, 1409 m/sec, 35186 t fired, .
Time elapsed: 1246 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1232/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5148705 t fired, 76181 attempts, .
71 EF STEQ 1232/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 30/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 42226 m, 1407 m/sec, 42225 t fired, .
Time elapsed: 1251 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1237/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5169817 t fired, 76522 attempts, .
71 EF STEQ 1237/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 35/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 49291 m, 1413 m/sec, 49290 t fired, .
Time elapsed: 1256 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1242/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5190896 t fired, 76865 attempts, .
71 EF STEQ 1242/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 40/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 56345 m, 1410 m/sec, 56344 t fired, .
Time elapsed: 1261 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1247/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5212063 t fired, 77193 attempts, .
71 EF STEQ 1247/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 45/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 63403 m, 1411 m/sec, 63402 t fired, .
Time elapsed: 1266 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1252/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5233229 t fired, 77528 attempts, .
71 EF STEQ 1252/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 50/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 70463 m, 1412 m/sec, 70462 t fired, .
Time elapsed: 1271 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1257/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5254430 t fired, 77864 attempts, .
71 EF STEQ 1257/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 55/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 77522 m, 1411 m/sec, 77521 t fired, .
Time elapsed: 1276 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1262/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5275461 t fired, 78199 attempts, .
71 EF STEQ 1262/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 60/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 84569 m, 1409 m/sec, 84568 t fired, .
Time elapsed: 1281 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1267/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5296491 t fired, 78546 attempts, .
71 EF STEQ 1267/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 65/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 91610 m, 1408 m/sec, 91609 t fired, .
Time elapsed: 1286 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1272/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5317551 t fired, 78882 attempts, .
71 EF STEQ 1272/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 70/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 98653 m, 1408 m/sec, 98652 t fired, .
Time elapsed: 1291 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1277/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5338598 t fired, 79217 attempts, .
71 EF STEQ 1277/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 75/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 105698 m, 1409 m/sec, 105697 t fired, .
Time elapsed: 1296 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1282/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5359632 t fired, 79564 attempts, .
71 EF STEQ 1282/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 80/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 112755 m, 1411 m/sec, 112754 t fired, .
Time elapsed: 1301 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1287/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5380688 t fired, 79900 attempts, .
71 EF STEQ 1287/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 85/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 119798 m, 1408 m/sec, 119797 t fired, .
Time elapsed: 1306 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1292/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5401798 t fired, 80234 attempts, .
71 EF STEQ 1292/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 90/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 126859 m, 1412 m/sec, 126858 t fired, .
Time elapsed: 1311 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1297/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5422763 t fired, 80576 attempts, .
71 EF STEQ 1297/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 95/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 133898 m, 1407 m/sec, 133897 t fired, .
Time elapsed: 1316 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1302/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5443819 t fired, 80922 attempts, .
71 EF STEQ 1302/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 100/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 140915 m, 1403 m/sec, 140914 t fired, .
Time elapsed: 1321 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1307/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5464833 t fired, 81267 attempts, .
71 EF STEQ 1307/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 105/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 147962 m, 1409 m/sec, 147961 t fired, .
Time elapsed: 1326 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1312/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5485871 t fired, 81604 attempts, .
71 EF STEQ 1312/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 110/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 154997 m, 1407 m/sec, 154996 t fired, .
Time elapsed: 1331 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1317/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5506883 t fired, 81950 attempts, .
71 EF STEQ 1317/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 115/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 162043 m, 1409 m/sec, 162042 t fired, .
Time elapsed: 1336 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1322/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5527932 t fired, 82285 attempts, .
71 EF STEQ 1322/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 120/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 169093 m, 1410 m/sec, 169092 t fired, .
Time elapsed: 1341 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1328/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5549084 t fired, 82624 attempts, .
71 EF STEQ 1328/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 126/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 176149 m, 1411 m/sec, 176148 t fired, .
Time elapsed: 1347 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1333/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5570139 t fired, 82966 attempts, .
71 EF STEQ 1333/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 131/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 183191 m, 1408 m/sec, 183190 t fired, .
Time elapsed: 1352 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1338/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5591236 t fired, 83298 attempts, .
71 EF STEQ 1338/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 136/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 190243 m, 1410 m/sec, 190242 t fired, .
Time elapsed: 1357 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1343/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5612329 t fired, 83634 attempts, .
71 EF STEQ 1343/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 141/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 197290 m, 1409 m/sec, 197289 t fired, .
Time elapsed: 1362 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1348/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5633472 t fired, 83962 attempts, .
71 EF STEQ 1348/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 146/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 204330 m, 1408 m/sec, 204329 t fired, .
Time elapsed: 1367 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1353/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5654543 t fired, 84304 attempts, .
71 EF STEQ 1353/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 151/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 211358 m, 1405 m/sec, 211357 t fired, .
Time elapsed: 1372 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1358/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5675601 t fired, 84637 attempts, .
71 EF STEQ 1358/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 156/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 218413 m, 1411 m/sec, 218412 t fired, .
Time elapsed: 1377 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1363/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5696615 t fired, 84971 attempts, .
71 EF STEQ 1363/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 161/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 225425 m, 1402 m/sec, 225424 t fired, .
Time elapsed: 1382 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1368/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5717712 t fired, 85311 attempts, .
71 EF STEQ 1368/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 166/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 232446 m, 1404 m/sec, 232445 t fired, .
Time elapsed: 1387 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1373/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5738736 t fired, 85637 attempts, .
71 EF STEQ 1373/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 171/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 239465 m, 1403 m/sec, 239464 t fired, .
Time elapsed: 1392 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1378/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5759875 t fired, 85975 attempts, .
71 EF STEQ 1378/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 176/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 246506 m, 1408 m/sec, 246505 t fired, .
Time elapsed: 1397 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1383/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5781031 t fired, 86311 attempts, .
71 EF STEQ 1383/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 181/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 253579 m, 1414 m/sec, 253578 t fired, .
Time elapsed: 1402 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1388/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5802258 t fired, 86648 attempts, .
71 EF STEQ 1388/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 186/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 260635 m, 1411 m/sec, 260634 t fired, .
Time elapsed: 1407 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1393/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5823470 t fired, 86976 attempts, .
71 EF STEQ 1393/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 191/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 267655 m, 1404 m/sec, 267654 t fired, .
Time elapsed: 1412 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1398/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5844670 t fired, 87308 attempts, .
71 EF STEQ 1398/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 196/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 274662 m, 1401 m/sec, 274661 t fired, .
Time elapsed: 1417 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1403/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5865905 t fired, 87645 attempts, .
71 EF STEQ 1403/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 201/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 281659 m, 1399 m/sec, 281658 t fired, .
Time elapsed: 1422 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1408/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5886942 t fired, 87989 attempts, .
71 EF STEQ 1408/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 206/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 288641 m, 1396 m/sec, 288640 t fired, .
Time elapsed: 1427 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1413/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5908074 t fired, 88316 attempts, .
71 EF STEQ 1413/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 211/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 295625 m, 1396 m/sec, 295624 t fired, .
Time elapsed: 1432 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1418/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5929265 t fired, 88651 attempts, .
71 EF STEQ 1418/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 216/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 302622 m, 1399 m/sec, 302621 t fired, .
Time elapsed: 1437 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1423/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5950446 t fired, 88988 attempts, .
71 EF STEQ 1423/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 221/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 309737 m, 1423 m/sec, 309736 t fired, .
Time elapsed: 1442 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1428/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5971399 t fired, 89326 attempts, .
71 EF STEQ 1428/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 226/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 316839 m, 1420 m/sec, 316838 t fired, .
Time elapsed: 1447 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1433/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 5992338 t fired, 89677 attempts, .
71 EF STEQ 1433/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 231/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 323898 m, 1411 m/sec, 323897 t fired, .
Time elapsed: 1452 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1438/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6013407 t fired, 90014 attempts, .
71 EF STEQ 1438/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 236/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 330950 m, 1410 m/sec, 330949 t fired, .
Time elapsed: 1457 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1443/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6034618 t fired, 90346 attempts, .
71 EF STEQ 1443/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 241/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 338002 m, 1410 m/sec, 338001 t fired, .
Time elapsed: 1462 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1448/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6055730 t fired, 90684 attempts, .
71 EF STEQ 1448/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 246/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 345051 m, 1409 m/sec, 345050 t fired, .
Time elapsed: 1467 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1453/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6076764 t fired, 91014 attempts, .
71 EF STEQ 1453/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 251/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 352107 m, 1411 m/sec, 352106 t fired, .
Time elapsed: 1472 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1458/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6097850 t fired, 91343 attempts, .
71 EF STEQ 1458/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 256/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 359127 m, 1404 m/sec, 359126 t fired, .
Time elapsed: 1477 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1463/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6119124 t fired, 91676 attempts, .
71 EF STEQ 1463/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 261/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 366185 m, 1411 m/sec, 366184 t fired, .
Time elapsed: 1482 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1468/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6140209 t fired, 91999 attempts, .
71 EF STEQ 1468/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 266/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 373230 m, 1409 m/sec, 373229 t fired, .
Time elapsed: 1487 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1473/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6161176 t fired, 92334 attempts, .
71 EF STEQ 1473/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 271/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 380247 m, 1403 m/sec, 380246 t fired, .
Time elapsed: 1492 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1478/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6182005 t fired, 92668 attempts, .
71 EF STEQ 1478/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 276/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 387297 m, 1410 m/sec, 387296 t fired, .
Time elapsed: 1497 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1483/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6203128 t fired, 93000 attempts, .
71 EF STEQ 1483/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 281/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 394327 m, 1406 m/sec, 394326 t fired, .
Time elapsed: 1502 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1488/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6224255 t fired, 93337 attempts, .
71 EF STEQ 1488/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 286/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 401367 m, 1408 m/sec, 401366 t fired, .
Time elapsed: 1507 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1493/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6245229 t fired, 93673 attempts, .
71 EF STEQ 1493/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 291/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 408383 m, 1403 m/sec, 408382 t fired, .
Time elapsed: 1512 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1498/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6266171 t fired, 94009 attempts, .
71 EF STEQ 1498/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 296/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 415395 m, 1402 m/sec, 415394 t fired, .
Time elapsed: 1517 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1503/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6287160 t fired, 94339 attempts, .
71 EF STEQ 1503/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 301/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 422415 m, 1404 m/sec, 422414 t fired, .
Time elapsed: 1522 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1508/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6307545 t fired, 94665 attempts, .
71 EF STEQ 1508/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 306/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 429221 m, 1361 m/sec, 429220 t fired, .
Time elapsed: 1527 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1513/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6328651 t fired, 95000 attempts, .
71 EF STEQ 1513/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 311/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 436239 m, 1403 m/sec, 436238 t fired, .
Time elapsed: 1532 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1518/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6349761 t fired, 95333 attempts, .
71 EF STEQ 1518/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 316/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 443279 m, 1408 m/sec, 443278 t fired, .
Time elapsed: 1537 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1523/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6370858 t fired, 95672 attempts, .
71 EF STEQ 1523/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 321/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 450294 m, 1403 m/sec, 450293 t fired, .
Time elapsed: 1542 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1528/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6391925 t fired, 96010 attempts, .
71 EF STEQ 1528/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 326/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 457295 m, 1400 m/sec, 457294 t fired, .
Time elapsed: 1547 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1533/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6413006 t fired, 96336 attempts, .
71 EF STEQ 1533/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 331/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 464317 m, 1404 m/sec, 464316 t fired, .
Time elapsed: 1552 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1538/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6434082 t fired, 96664 attempts, .
71 EF STEQ 1538/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 336/339 3/5 DoubleLock-PT-p3s3-CTLFireability-07 471341 m, 1404 m/sec, 471340 t fired, .
Time elapsed: 1557 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 74 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-07 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 2 0 3 1 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1543/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6455080 t fired, 96997 attempts, .
71 EF STEQ 1543/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
Time elapsed: 1562 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p3s3-CTLFireability-00
lola: time limit : 339 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 74 (type EXCL) for 29 DoubleLock-PT-p3s3-CTLFireability-07
lola: time limit : 2038 sec
lola: memory limit: 5 pages
lola: FINISHED task # 1 (type EXCL) for DoubleLock-PT-p3s3-CTLFireability-00
lola: result : false
lola: markings : 34
lola: fired transitions : 68
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1548/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6476110 t fired, 97326 attempts, .
71 EF STEQ 1548/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 5/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 7474 m, -92773 m/sec, 7473 t fired, .
Time elapsed: 1567 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1553/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6497109 t fired, 97665 attempts, .
71 EF STEQ 1553/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 10/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 14993 m, 1503 m/sec, 14992 t fired, .
Time elapsed: 1572 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1558/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6518238 t fired, 97999 attempts, .
71 EF STEQ 1558/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 15/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 22514 m, 1504 m/sec, 22513 t fired, .
Time elapsed: 1577 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1563/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6539407 t fired, 98332 attempts, .
71 EF STEQ 1563/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 20/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 30054 m, 1508 m/sec, 30053 t fired, .
Time elapsed: 1582 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1568/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6560404 t fired, 98669 attempts, .
71 EF STEQ 1568/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 25/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 37575 m, 1504 m/sec, 37574 t fired, .
Time elapsed: 1587 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1573/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6581357 t fired, 99005 attempts, .
71 EF STEQ 1573/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 30/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 45110 m, 1507 m/sec, 45109 t fired, .
Time elapsed: 1592 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1578/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6602516 t fired, 99336 attempts, .
71 EF STEQ 1578/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 35/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 52643 m, 1506 m/sec, 52642 t fired, .
Time elapsed: 1597 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1583/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6623606 t fired, 99674 attempts, .
71 EF STEQ 1583/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 40/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 60181 m, 1507 m/sec, 60180 t fired, .
Time elapsed: 1602 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1588/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6644616 t fired, 100016 attempts, .
71 EF STEQ 1588/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 45/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 67723 m, 1508 m/sec, 67722 t fired, .
Time elapsed: 1607 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1593/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6665651 t fired, 100352 attempts, .
71 EF STEQ 1593/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 50/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 75262 m, 1507 m/sec, 75261 t fired, .
Time elapsed: 1612 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1598/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6686803 t fired, 100690 attempts, .
71 EF STEQ 1598/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 55/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 82795 m, 1506 m/sec, 82794 t fired, .
Time elapsed: 1617 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1603/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6707951 t fired, 101026 attempts, .
71 EF STEQ 1603/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 60/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 90331 m, 1507 m/sec, 90330 t fired, .
Time elapsed: 1622 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1608/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6729011 t fired, 101370 attempts, .
71 EF STEQ 1608/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 65/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 97857 m, 1505 m/sec, 97856 t fired, .
Time elapsed: 1627 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1613/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6750100 t fired, 101703 attempts, .
71 EF STEQ 1613/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 70/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 105389 m, 1506 m/sec, 105388 t fired, .
Time elapsed: 1632 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1618/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6771141 t fired, 102033 attempts, .
71 EF STEQ 1618/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 75/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 112874 m, 1497 m/sec, 112873 t fired, .
Time elapsed: 1637 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1623/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6792258 t fired, 102359 attempts, .
71 EF STEQ 1623/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 80/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 120379 m, 1501 m/sec, 120378 t fired, .
Time elapsed: 1642 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1628/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6813408 t fired, 102716 attempts, .
71 EF STEQ 1628/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 85/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 127865 m, 1497 m/sec, 127864 t fired, .
Time elapsed: 1647 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1633/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6834602 t fired, 103050 attempts, .
71 EF STEQ 1633/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 90/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 135351 m, 1497 m/sec, 135350 t fired, .
Time elapsed: 1652 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1638/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6855756 t fired, 103389 attempts, .
71 EF STEQ 1638/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 95/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 142843 m, 1498 m/sec, 142842 t fired, .
Time elapsed: 1657 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1643/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6876946 t fired, 103707 attempts, .
71 EF STEQ 1643/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 100/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 150357 m, 1502 m/sec, 150356 t fired, .
Time elapsed: 1662 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1648/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6898146 t fired, 104048 attempts, .
71 EF STEQ 1648/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 105/339 1/5 DoubleLock-PT-p3s3-CTLFireability-07 157906 m, 1509 m/sec, 157905 t fired, .
Time elapsed: 1667 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1653/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6919426 t fired, 104381 attempts, .
71 EF STEQ 1653/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 110/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 165465 m, 1511 m/sec, 165464 t fired, .
Time elapsed: 1672 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1658/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6940689 t fired, 104702 attempts, .
71 EF STEQ 1658/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 115/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 173018 m, 1510 m/sec, 173017 t fired, .
Time elapsed: 1677 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1663/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6961935 t fired, 105028 attempts, .
71 EF STEQ 1663/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 120/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 180563 m, 1509 m/sec, 180562 t fired, .
Time elapsed: 1682 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1668/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 6983085 t fired, 105357 attempts, .
71 EF STEQ 1668/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 125/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 188094 m, 1506 m/sec, 188093 t fired, .
Time elapsed: 1687 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1673/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7004167 t fired, 105701 attempts, .
71 EF STEQ 1673/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 130/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 195618 m, 1504 m/sec, 195617 t fired, .
Time elapsed: 1692 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1678/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7025268 t fired, 106032 attempts, .
71 EF STEQ 1678/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 135/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 203129 m, 1502 m/sec, 203128 t fired, .
Time elapsed: 1697 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1683/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7046399 t fired, 106370 attempts, .
71 EF STEQ 1683/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 140/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 210638 m, 1501 m/sec, 210637 t fired, .
Time elapsed: 1702 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1688/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7067509 t fired, 106704 attempts, .
71 EF STEQ 1688/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 145/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 218151 m, 1502 m/sec, 218150 t fired, .
Time elapsed: 1707 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1693/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7088626 t fired, 107048 attempts, .
71 EF STEQ 1693/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 150/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 225663 m, 1502 m/sec, 225662 t fired, .
Time elapsed: 1712 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1698/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7109716 t fired, 107382 attempts, .
71 EF STEQ 1698/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 155/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 233181 m, 1503 m/sec, 233180 t fired, .
Time elapsed: 1717 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1703/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7130868 t fired, 107715 attempts, .
71 EF STEQ 1703/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 160/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 240695 m, 1502 m/sec, 240694 t fired, .
Time elapsed: 1722 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1708/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7152036 t fired, 108045 attempts, .
71 EF STEQ 1708/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 165/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 248211 m, 1503 m/sec, 248210 t fired, .
Time elapsed: 1727 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1713/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7173122 t fired, 108381 attempts, .
71 EF STEQ 1713/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 170/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 255726 m, 1503 m/sec, 255725 t fired, .
Time elapsed: 1732 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1718/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7194212 t fired, 108713 attempts, .
71 EF STEQ 1718/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 175/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 263253 m, 1505 m/sec, 263252 t fired, .
Time elapsed: 1737 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1723/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7215362 t fired, 109045 attempts, .
71 EF STEQ 1723/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 180/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 270774 m, 1504 m/sec, 270773 t fired, .
Time elapsed: 1742 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1728/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7236474 t fired, 109379 attempts, .
71 EF STEQ 1728/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 185/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 278282 m, 1501 m/sec, 278281 t fired, .
Time elapsed: 1747 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1733/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7257557 t fired, 109720 attempts, .
71 EF STEQ 1733/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 190/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 285803 m, 1504 m/sec, 285802 t fired, .
Time elapsed: 1752 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1738/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7278713 t fired, 110045 attempts, .
71 EF STEQ 1738/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 195/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 293335 m, 1506 m/sec, 293334 t fired, .
Time elapsed: 1757 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p3s3-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 EF FNDP 1743/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 7299851 t fired, 110365 attempts, .
71 EF STEQ 1743/3581 0/5 DoubleLock-PT-p3s3-CTLFireability-07 sara is running.
74 EFEG EXCL 200/339 2/5 DoubleLock-PT-p3s3-CTLFireability-07 300806 m, 1494 m/sec, 300805 t fired, .
Time elapsed: 1762 secs. Pages in use: 37
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p3s3-CTLFireability-00: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-02: CTL false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-03: F false state space / EG
DoubleLock-PT-p3s3-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-06: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-08: CONJ false CTL model checker
DoubleLock-PT-p3s3-CTLFireability-13: CTL true CTL model checker
DoubleLock-PT-p3s3-CTLFireability-14: EG false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p3s3-CTLFireability-01: CONJ 0 1 0 0 4 0 0 4
DoubleLock-PT-p3s3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p3s3-CTLFireability-07: CONJ 0 1 3 0 3 0 2 0
DoubleLock-PT-p3s3-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p3s3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p3s3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-167819413000562"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p3s3.tgz
mv DoubleLock-PT-p3s3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;