About the Execution of LoLA for DoubleLock-PT-p2s2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4393.252 | 3600000.00 | 1110717.00 | 10960.10 | ?TF?TF?FFTF??F?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r134-smll-167819412900538.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DoubleLock-PT-p2s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-167819412900538
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.3K Feb 25 14:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 14:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 14:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.0K Feb 25 14:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 67K Feb 25 14:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 14:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 14:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 813K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p2s2-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678529800838
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p2s2
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DoubleLock-PT-p2s2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DoubleLock-PT-p2s2-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 11819680 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16166632 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 64 transitions removed,36 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 47 (type CNST) for 46 DoubleLock-PT-p2s2-CTLFireability-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 47 (type CNST) for DoubleLock-PT-p2s2-CTLFireability-10
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 26 (type CNST) for 25 DoubleLock-PT-p2s2-CTLFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 26 (type CNST) for DoubleLock-PT-p2s2-CTLFireability-07
lola: result : false
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 64 (type EXCL) for 10 DoubleLock-PT-p2s2-CTLFireability-02
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 64 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-02
lola: result : true
lola: markings : 150
lola: fired transitions : 149
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 61 DoubleLock-PT-p2s2-CTLFireability-15
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-15
lola: result : true
lola: markings : 111
lola: fired transitions : 111
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 DoubleLock-PT-p2s2-CTLFireability-14
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 66 (type FNDP) for 28 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 28 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 80 (type SRCH) for 28 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: try reading problem file /home/mcc/execution/CTLFireability-67.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 4/224 3/32 DoubleLock-PT-p2s2-CTLFireability-14 438965 m, 87793 m/sec, 438964 t fired, .
66 EF FNDP 4/899 0/5 DoubleLock-PT-p2s2-CTLFireability-08 25284 t fired, 399 attempts, .
67 EF STEQ 4/899 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 4/899 1/5 DoubleLock-PT-p2s2-CTLFireability-08 31974 m, 6394 m/sec, 37373 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 9/224 7/32 DoubleLock-PT-p2s2-CTLFireability-14 1114410 m, 135089 m/sec, 1114410 t fired, .
66 EF FNDP 9/895 0/5 DoubleLock-PT-p2s2-CTLFireability-08 65805 t fired, 1043 attempts, .
67 EF STEQ 9/895 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 9/895 1/5 DoubleLock-PT-p2s2-CTLFireability-08 87805 m, 11166 m/sec, 102621 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 14/224 13/32 DoubleLock-PT-p2s2-CTLFireability-14 2003942 m, 177906 m/sec, 2003941 t fired, .
66 EF FNDP 14/890 0/5 DoubleLock-PT-p2s2-CTLFireability-08 117402 t fired, 1894 attempts, .
67 EF STEQ 14/890 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 14/890 1/5 DoubleLock-PT-p2s2-CTLFireability-08 147071 m, 11853 m/sec, 171884 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 19/224 17/32 DoubleLock-PT-p2s2-CTLFireability-14 2728509 m, 144913 m/sec, 2728509 t fired, .
66 EF FNDP 19/885 0/5 DoubleLock-PT-p2s2-CTLFireability-08 162262 t fired, 2645 attempts, .
67 EF STEQ 19/885 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 19/885 2/5 DoubleLock-PT-p2s2-CTLFireability-08 205781 m, 11742 m/sec, 240496 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 24/224 21/32 DoubleLock-PT-p2s2-CTLFireability-14 3335980 m, 121494 m/sec, 3335980 t fired, .
66 EF FNDP 24/880 0/5 DoubleLock-PT-p2s2-CTLFireability-08 191517 t fired, 3138 attempts, .
67 EF STEQ 24/880 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 24/880 2/5 DoubleLock-PT-p2s2-CTLFireability-08 263723 m, 11588 m/sec, 308211 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 29/224 24/32 DoubleLock-PT-p2s2-CTLFireability-14 3857091 m, 104222 m/sec, 3857090 t fired, .
66 EF FNDP 29/875 0/5 DoubleLock-PT-p2s2-CTLFireability-08 230299 t fired, 3805 attempts, .
67 EF STEQ 29/875 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 29/875 2/5 DoubleLock-PT-p2s2-CTLFireability-08 322554 m, 11766 m/sec, 376967 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 34/224 27/32 DoubleLock-PT-p2s2-CTLFireability-14 4308589 m, 90299 m/sec, 4308589 t fired, .
66 EF FNDP 34/870 0/5 DoubleLock-PT-p2s2-CTLFireability-08 265544 t fired, 4404 attempts, .
67 EF STEQ 34/870 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 34/870 3/5 DoubleLock-PT-p2s2-CTLFireability-08 381622 m, 11813 m/sec, 445998 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
59 CTL EXCL 39/224 31/32 DoubleLock-PT-p2s2-CTLFireability-14 4881168 m, 114515 m/sec, 4881168 t fired, .
66 EF FNDP 39/865 0/5 DoubleLock-PT-p2s2-CTLFireability-08 308763 t fired, 5175 attempts, .
67 EF STEQ 39/865 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 39/865 3/5 DoubleLock-PT-p2s2-CTLFireability-08 440110 m, 11697 m/sec, 514350 t fired, .
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lola: CANCELED task # 59 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 44/860 0/5 DoubleLock-PT-p2s2-CTLFireability-08 358478 t fired, 6041 attempts, .
67 EF STEQ 44/860 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 44/860 3/5 DoubleLock-PT-p2s2-CTLFireability-08 497320 m, 11442 m/sec, 581210 t fired, .
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lola: LAUNCH task # 56 (type EXCL) for 55 DoubleLock-PT-p2s2-CTLFireability-13
lola: time limit : 236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-13
lola: result : false
lola: markings : 115
lola: fired transitions : 115
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 52 DoubleLock-PT-p2s2-CTLFireability-12
lola: time limit : 253 sec
lola: memory limit: 32 pages
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/253 4/32 DoubleLock-PT-p2s2-CTLFireability-12 486468 m, 97293 m/sec, 486473 t fired, .
66 EF FNDP 49/855 0/5 DoubleLock-PT-p2s2-CTLFireability-08 410421 t fired, 6955 attempts, .
67 EF STEQ 49/855 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 49/855 3/5 DoubleLock-PT-p2s2-CTLFireability-08 530456 m, 6627 m/sec, 619935 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 10/253 9/32 DoubleLock-PT-p2s2-CTLFireability-12 1299439 m, 162594 m/sec, 1299445 t fired, .
66 EF FNDP 54/850 0/5 DoubleLock-PT-p2s2-CTLFireability-08 450938 t fired, 7660 attempts, .
67 EF STEQ 54/850 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 54/850 4/5 DoubleLock-PT-p2s2-CTLFireability-08 580269 m, 9962 m/sec, 678152 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 15/253 11/32 DoubleLock-PT-p2s2-CTLFireability-12 1752799 m, 90672 m/sec, 1752805 t fired, .
66 EF FNDP 59/845 0/5 DoubleLock-PT-p2s2-CTLFireability-08 504096 t fired, 8597 attempts, .
67 EF STEQ 59/845 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 59/845 4/5 DoubleLock-PT-p2s2-CTLFireability-08 636936 m, 11333 m/sec, 744376 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 20/253 15/32 DoubleLock-PT-p2s2-CTLFireability-12 2295609 m, 108562 m/sec, 2295614 t fired, .
66 EF FNDP 64/840 0/5 DoubleLock-PT-p2s2-CTLFireability-08 534386 t fired, 9125 attempts, .
67 EF STEQ 64/840 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 64/840 4/5 DoubleLock-PT-p2s2-CTLFireability-08 690295 m, 10671 m/sec, 806735 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 25/253 18/32 DoubleLock-PT-p2s2-CTLFireability-12 2866884 m, 114255 m/sec, 2866889 t fired, .
66 EF FNDP 69/835 0/5 DoubleLock-PT-p2s2-CTLFireability-08 574570 t fired, 9830 attempts, .
67 EF STEQ 69/835 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 69/835 4/5 DoubleLock-PT-p2s2-CTLFireability-08 729823 m, 7905 m/sec, 852930 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 30/253 21/32 DoubleLock-PT-p2s2-CTLFireability-12 3294825 m, 85588 m/sec, 3294830 t fired, .
66 EF FNDP 74/830 0/5 DoubleLock-PT-p2s2-CTLFireability-08 625833 t fired, 10742 attempts, .
67 EF STEQ 74/830 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 74/830 5/5 DoubleLock-PT-p2s2-CTLFireability-08 775740 m, 9183 m/sec, 906594 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 35/253 25/32 DoubleLock-PT-p2s2-CTLFireability-12 3893541 m, 119743 m/sec, 3893546 t fired, .
66 EF FNDP 79/825 0/5 DoubleLock-PT-p2s2-CTLFireability-08 659938 t fired, 11339 attempts, .
67 EF STEQ 79/825 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 79/825 5/5 DoubleLock-PT-p2s2-CTLFireability-08 824151 m, 9682 m/sec, 963169 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 40/253 28/32 DoubleLock-PT-p2s2-CTLFireability-12 4394555 m, 100202 m/sec, 4394560 t fired, .
66 EF FNDP 84/820 0/5 DoubleLock-PT-p2s2-CTLFireability-08 712143 t fired, 12276 attempts, .
67 EF STEQ 84/820 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 84/820 5/5 DoubleLock-PT-p2s2-CTLFireability-08 881032 m, 11376 m/sec, 1029645 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 3 0 4 0 0 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 45/253 32/32 DoubleLock-PT-p2s2-CTLFireability-12 5083661 m, 137821 m/sec, 5083666 t fired, .
66 EF FNDP 89/815 0/5 DoubleLock-PT-p2s2-CTLFireability-08 749079 t fired, 12947 attempts, .
67 EF STEQ 89/815 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
80 EF SRCH 89/815 5/5 DoubleLock-PT-p2s2-CTLFireability-08 928091 m, 9411 m/sec, 1084642 t fired, .
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lola: CANCELED task # 53 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-12 (memory limit exceeded)
lola: CANCELED task # 80 (type SRCH) for DoubleLock-PT-p2s2-CTLFireability-08 (memory limit exceeded)
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 5 0 0 2 0 0 0
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 4 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 94/810 0/5 DoubleLock-PT-p2s2-CTLFireability-08 801240 t fired, 13885 attempts, .
67 EF STEQ 94/810 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
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lola: LAUNCH task # 50 (type EXCL) for 49 DoubleLock-PT-p2s2-CTLFireability-11
lola: time limit : 269 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 76 (type FNDP) for 3 DoubleLock-PT-p2s2-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-01
lola: result : true
lola: fired transitions : 26
lola: tried executions : 1
lola: time used : 0.000000
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lola: LAUNCH task # 71 (type FNDP) for 43 DoubleLock-PT-p2s2-CTLFireability-09
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lola: memory limit: 5 pages
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/292 2/32 DoubleLock-PT-p2s2-CTLFireability-11 296702 m, 59340 m/sec, 593404 t fired, .
66 EF FNDP 99/1705 0/5 DoubleLock-PT-p2s2-CTLFireability-08 850401 t fired, 14784 attempts, .
67 EF STEQ 99/1105 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 5/1168 0/5 DoubleLock-PT-p2s2-CTLFireability-09 36050 t fired, 531 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/292 5/32 DoubleLock-PT-p2s2-CTLFireability-11 715003 m, 83660 m/sec, 1430007 t fired, .
66 EF FNDP 104/1700 0/5 DoubleLock-PT-p2s2-CTLFireability-08 882855 t fired, 15370 attempts, .
67 EF STEQ 104/1100 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 10/1163 0/5 DoubleLock-PT-p2s2-CTLFireability-09 68187 t fired, 1005 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/292 8/32 DoubleLock-PT-p2s2-CTLFireability-11 1230409 m, 103081 m/sec, 2460818 t fired, .
66 EF FNDP 109/1695 0/5 DoubleLock-PT-p2s2-CTLFireability-08 910316 t fired, 15873 attempts, .
67 EF STEQ 109/1095 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 15/1158 0/5 DoubleLock-PT-p2s2-CTLFireability-09 95465 t fired, 1406 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/292 11/32 DoubleLock-PT-p2s2-CTLFireability-11 1731064 m, 100131 m/sec, 3462129 t fired, .
66 EF FNDP 114/1690 0/5 DoubleLock-PT-p2s2-CTLFireability-08 956541 t fired, 16722 attempts, .
67 EF STEQ 114/1090 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 20/1153 0/5 DoubleLock-PT-p2s2-CTLFireability-09 122725 t fired, 1812 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/292 13/32 DoubleLock-PT-p2s2-CTLFireability-11 2007104 m, 55208 m/sec, 4014209 t fired, .
66 EF FNDP 119/1685 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1008656 t fired, 17671 attempts, .
67 EF STEQ 119/1085 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 25/1148 0/5 DoubleLock-PT-p2s2-CTLFireability-09 154562 t fired, 2301 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 30/292 15/32 DoubleLock-PT-p2s2-CTLFireability-11 2342954 m, 67170 m/sec, 4685909 t fired, .
66 EF FNDP 124/1680 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1050959 t fired, 18438 attempts, .
67 EF STEQ 124/1080 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 30/1143 0/5 DoubleLock-PT-p2s2-CTLFireability-09 181308 t fired, 2703 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 35/292 18/32 DoubleLock-PT-p2s2-CTLFireability-11 2771468 m, 85702 m/sec, 5542936 t fired, .
66 EF FNDP 129/1675 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1080640 t fired, 18972 attempts, .
67 EF STEQ 129/1075 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 35/1138 0/5 DoubleLock-PT-p2s2-CTLFireability-09 211905 t fired, 3176 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 40/292 21/32 DoubleLock-PT-p2s2-CTLFireability-11 3288813 m, 103469 m/sec, 6577626 t fired, .
66 EF FNDP 134/1670 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1116624 t fired, 19639 attempts, .
67 EF STEQ 134/1070 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 40/1133 0/5 DoubleLock-PT-p2s2-CTLFireability-09 240677 t fired, 3628 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 45/292 24/32 DoubleLock-PT-p2s2-CTLFireability-11 3803013 m, 102840 m/sec, 7606027 t fired, .
66 EF FNDP 139/1665 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1150882 t fired, 20252 attempts, .
67 EF STEQ 139/1065 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 45/1128 0/5 DoubleLock-PT-p2s2-CTLFireability-09 272271 t fired, 4115 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 50/292 27/32 DoubleLock-PT-p2s2-CTLFireability-11 4318178 m, 103033 m/sec, 8636356 t fired, .
66 EF FNDP 144/1660 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1182040 t fired, 20827 attempts, .
67 EF STEQ 144/1060 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 50/1123 0/5 DoubleLock-PT-p2s2-CTLFireability-09 308448 t fired, 4675 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 55/292 30/32 DoubleLock-PT-p2s2-CTLFireability-11 4833104 m, 102985 m/sec, 9666208 t fired, .
66 EF FNDP 149/1655 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1212804 t fired, 21370 attempts, .
67 EF STEQ 149/1055 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 55/1118 0/5 DoubleLock-PT-p2s2-CTLFireability-09 348017 t fired, 5307 attempts, .
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lola: CANCELED task # 50 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-11 (memory limit exceeded)
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DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 7 2 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-09: EF 0 3 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 154/1650 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1256755 t fired, 22184 attempts, .
67 EF STEQ 154/1050 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
71 EF FNDP 60/1113 0/5 DoubleLock-PT-p2s2-CTLFireability-09 377161 t fired, 5775 attempts, .
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lola: LAUNCH task # 41 (type EXCL) for 28 DoubleLock-PT-p2s2-CTLFireability-08
lola: time limit : 313 sec
lola: memory limit: 32 pages
lola: FINISHED task # 71 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-09
lola: result : true
lola: fired transitions : 402434
lola: tried executions : 6175
lola: time used : 63.000000
lola: memory pages used : 0
lola: LAUNCH task # 72 (type FNDP) for 28 DoubleLock-PT-p2s2-CTLFireability-08
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lola: memory limit: 5 pages
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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41 CTL EXCL 5/344 3/32 DoubleLock-PT-p2s2-CTLFireability-08 400519 m, 80103 m/sec, 400518 t fired, .
66 EF FNDP 159/3441 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1309760 t fired, 23158 attempts, .
67 EF STEQ 159/1642 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 2/1720 0/5 DoubleLock-PT-p2s2-CTLFireability-08 20412 t fired, 349 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/344 6/32 DoubleLock-PT-p2s2-CTLFireability-08 825875 m, 85071 m/sec, 825875 t fired, .
66 EF FNDP 164/3439 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1362498 t fired, 24124 attempts, .
67 EF STEQ 164/1640 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 7/1718 0/5 DoubleLock-PT-p2s2-CTLFireability-08 59973 t fired, 1008 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/344 8/32 DoubleLock-PT-p2s2-CTLFireability-08 1231054 m, 81035 m/sec, 1231054 t fired, .
66 EF FNDP 169/3434 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1415237 t fired, 25091 attempts, .
67 EF STEQ 169/1635 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 12/1713 0/5 DoubleLock-PT-p2s2-CTLFireability-08 88609 t fired, 1493 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/344 11/32 DoubleLock-PT-p2s2-CTLFireability-08 1722552 m, 98299 m/sec, 1722552 t fired, .
66 EF FNDP 174/3429 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1467915 t fired, 26049 attempts, .
67 EF STEQ 174/1630 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 17/1708 0/5 DoubleLock-PT-p2s2-CTLFireability-08 117111 t fired, 1993 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/344 13/32 DoubleLock-PT-p2s2-CTLFireability-08 2054398 m, 66369 m/sec, 2054397 t fired, .
66 EF FNDP 179/3424 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1520858 t fired, 27030 attempts, .
67 EF STEQ 179/1625 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 22/1703 0/5 DoubleLock-PT-p2s2-CTLFireability-08 163493 t fired, 2811 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/344 16/32 DoubleLock-PT-p2s2-CTLFireability-08 2586567 m, 106433 m/sec, 2586566 t fired, .
66 EF FNDP 184/3419 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1573402 t fired, 27996 attempts, .
67 EF STEQ 184/1620 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 27/1698 0/5 DoubleLock-PT-p2s2-CTLFireability-08 196163 t fired, 3411 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/344 18/32 DoubleLock-PT-p2s2-CTLFireability-08 2908409 m, 64368 m/sec, 2908409 t fired, .
66 EF FNDP 189/3414 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1626369 t fired, 28954 attempts, .
67 EF STEQ 189/1615 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 32/1693 0/5 DoubleLock-PT-p2s2-CTLFireability-08 245489 t fired, 4305 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/344 21/32 DoubleLock-PT-p2s2-CTLFireability-08 3293716 m, 77061 m/sec, 3293716 t fired, .
66 EF FNDP 194/3409 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1679220 t fired, 29928 attempts, .
67 EF STEQ 194/1610 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 37/1688 0/5 DoubleLock-PT-p2s2-CTLFireability-08 280353 t fired, 4937 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/344 23/32 DoubleLock-PT-p2s2-CTLFireability-08 3719731 m, 85203 m/sec, 3719731 t fired, .
66 EF FNDP 199/3404 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1731919 t fired, 30899 attempts, .
67 EF STEQ 199/1605 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 42/1683 0/5 DoubleLock-PT-p2s2-CTLFireability-08 308788 t fired, 5461 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 50/344 25/32 DoubleLock-PT-p2s2-CTLFireability-08 4040509 m, 64155 m/sec, 4040508 t fired, .
66 EF FNDP 204/3399 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1784485 t fired, 31858 attempts, .
67 EF STEQ 204/1600 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 47/1678 0/5 DoubleLock-PT-p2s2-CTLFireability-08 333706 t fired, 5916 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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41 CTL EXCL 55/344 27/32 DoubleLock-PT-p2s2-CTLFireability-08 4363448 m, 64587 m/sec, 4363447 t fired, .
66 EF FNDP 209/3394 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1837132 t fired, 32836 attempts, .
67 EF STEQ 209/1595 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 52/1673 0/5 DoubleLock-PT-p2s2-CTLFireability-08 358945 t fired, 6383 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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41 CTL EXCL 60/344 30/32 DoubleLock-PT-p2s2-CTLFireability-08 4739993 m, 75309 m/sec, 4739992 t fired, .
66 EF FNDP 214/3389 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1890064 t fired, 33819 attempts, .
67 EF STEQ 214/1590 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 57/1668 0/5 DoubleLock-PT-p2s2-CTLFireability-08 401124 t fired, 7160 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 4 0 4 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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41 CTL EXCL 65/344 32/32 DoubleLock-PT-p2s2-CTLFireability-08 5074380 m, 66877 m/sec, 5074379 t fired, .
66 EF FNDP 219/3384 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1942894 t fired, 34788 attempts, .
67 EF STEQ 219/1585 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 62/1663 0/5 DoubleLock-PT-p2s2-CTLFireability-08 454069 t fired, 8148 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 3 0 4 0 2 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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66 EF FNDP 224/3379 0/5 DoubleLock-PT-p2s2-CTLFireability-08 1995652 t fired, 35750 attempts, .
67 EF STEQ 224/1580 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 67/1658 0/5 DoubleLock-PT-p2s2-CTLFireability-08 506613 t fired, 9133 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 3 0 4 0 2 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/374 3/32 DoubleLock-PT-p2s2-CTLFireability-06 364330 m, 72866 m/sec, 364330 t fired, .
66 EF FNDP 229/3374 0/5 DoubleLock-PT-p2s2-CTLFireability-08 2048445 t fired, 36713 attempts, .
67 EF STEQ 229/1575 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 72/1653 0/5 DoubleLock-PT-p2s2-CTLFireability-08 559662 t fired, 10121 attempts, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-01: CONJ 0 1 0 0 3 0 0 3
DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-08: CONJ 0 5 3 0 4 0 2 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/374 5/32 DoubleLock-PT-p2s2-CTLFireability-06 728147 m, 72763 m/sec, 728147 t fired, .
66 EF FNDP 234/3369 0/5 DoubleLock-PT-p2s2-CTLFireability-08 2101601 t fired, 37682 attempts, .
67 EF STEQ 234/1570 0/5 DoubleLock-PT-p2s2-CTLFireability-08 sara is running.
72 EF FNDP 77/1648 0/5 DoubleLock-PT-p2s2-CTLFireability-08 612980 t fired, 11121 attempts, .
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lola: FINISHED task # 72 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-08
lola: result : true
lola: fired transitions : 658665
lola: tried executions : 11986
lola: time used : 81.000000
lola: memory pages used : 0
lola: CANCELED task # 66 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-08 (obsolete)
lola: CANCELED task # 67 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-08 (obsolete)
lola: FINISHED task # 66 (type FNDP) for DoubleLock-PT-p2s2-CTLFireability-08
lola: result : unknown
lola: fired transitions : 2147043
lola: tried executions : 38520
lola: time used : 238.000000
lola: memory pages used : 0
lola: FINISHED task # 67 (type EQUN) for DoubleLock-PT-p2s2-CTLFireability-08
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/562 8/32 DoubleLock-PT-p2s2-CTLFireability-06 1137938 m, 81958 m/sec, 1137938 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 20/562 12/32 DoubleLock-PT-p2s2-CTLFireability-06 1832099 m, 138832 m/sec, 1832099 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 25/562 16/32 DoubleLock-PT-p2s2-CTLFireability-06 2520195 m, 137619 m/sec, 2520195 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 30/562 20/32 DoubleLock-PT-p2s2-CTLFireability-06 3190168 m, 133994 m/sec, 3190169 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 35/562 24/32 DoubleLock-PT-p2s2-CTLFireability-06 3868455 m, 135657 m/sec, 3868455 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 40/562 29/32 DoubleLock-PT-p2s2-CTLFireability-06 4546922 m, 135693 m/sec, 4546922 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 20 (type EXCL) for 19 DoubleLock-PT-p2s2-CTLFireability-05
lola: time limit : 665 sec
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lola: FINISHED task # 20 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-05
lola: result : false
lola: markings : 111
lola: fired transitions : 554
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lola: LAUNCH task # 17 (type EXCL) for 16 DoubleLock-PT-p2s2-CTLFireability-04
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lola: FINISHED task # 17 (type EXCL) for DoubleLock-PT-p2s2-CTLFireability-04
lola: result : true
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lola: memory limit: 32 pages
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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14 CTL EXCL 5/1109 5/32 DoubleLock-PT-p2s2-CTLFireability-03 676553 m, 135310 m/sec, 1353106 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
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14 CTL EXCL 10/1109 9/32 DoubleLock-PT-p2s2-CTLFireability-03 1365524 m, 137794 m/sec, 2731047 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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14 CTL EXCL 15/1109 13/32 DoubleLock-PT-p2s2-CTLFireability-03 2036873 m, 134269 m/sec, 4073745 t fired, .
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DoubleLock-PT-p2s2-CTLFireability-04: CTL true CTL model checker
DoubleLock-PT-p2s2-CTLFireability-05: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-07: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
DoubleLock-PT-p2s2-CTLFireability-13: CTL false CTL model checker
DoubleLock-PT-p2s2-CTLFireability-15: CTL true CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p2s2-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p2s2-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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DoubleLock-PT-p2s2-CTLFireability-02: AXAF false state space /EXEG
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DoubleLock-PT-p2s2-CTLFireability-05: CTL false CTL model checker
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DoubleLock-PT-p2s2-CTLFireability-08: CONJ false findpath
DoubleLock-PT-p2s2-CTLFireability-09: EF true findpath
DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
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DoubleLock-PT-p2s2-CTLFireability-10: INITIAL false preprocessing
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p2s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p2s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-167819412900538"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p2s2.tgz
mv DoubleLock-PT-p2s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;