About the Execution of LoLA for DoubleLock-PT-p1s1
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
10841.399 | 3600000.00 | 3993720.00 | 9888.10 | TTT?F???F?T?T?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r134-smll-167819412800506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DoubleLock-PT-p1s1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-167819412800506
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 5.5K Feb 25 14:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 14:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 14:24 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 14:24 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 14:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 113K Feb 25 14:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 14:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Feb 25 14:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 93K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s1-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678484821963
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleLock-PT-p1s1
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DoubleLock-PT-p1s1
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DoubleLock-PT-p1s1-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 5372824 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16168744 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 8 transitions removed,8 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 7 (type EXCL) for 6 DoubleLock-PT-p1s1-CTLFireability-02
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-02
lola: result : true
lola: markings : 26
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 DoubleLock-PT-p1s1-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 23 (type EXCL) for 18 DoubleLock-PT-p1s1-CTLFireability-06
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 1 (type CNST) for DoubleLock-PT-p1s1-CTLFireability-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 23 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-06
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 DoubleLock-PT-p1s1-CTLFireability-09
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 80 (type FNDP) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SRCH) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 29 (type CNST) for 28 DoubleLock-PT-p1s1-CTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 29 (type CNST) for DoubleLock-PT-p1s1-CTLFireability-08
lola: result : false
lola: FINISHED task # 85 (type SRCH) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : true
lola: markings : 29
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 80 (type FNDP) for DoubleLock-PT-p1s1-CTLFireability-11 (obsolete)
lola: CANCELED task # 81 (type EQUN) for DoubleLock-PT-p1s1-CTLFireability-11 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 80 (type FNDP) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : unknown
lola: fired transitions : 16
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: try reading problem file /home/mcc/execution/CTLFireability-81.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/200 2/32 DoubleLock-PT-p1s1-CTLFireability-09 468886 m, 93777 m/sec, 2263536 t fired, .
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/200 5/32 DoubleLock-PT-p1s1-CTLFireability-09 962990 m, 98820 m/sec, 4648914 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/200 6/32 DoubleLock-PT-p1s1-CTLFireability-09 1410025 m, 89407 m/sec, 6807018 t fired, .
Time elapsed: 15 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/200 8/32 DoubleLock-PT-p1s1-CTLFireability-09 1887278 m, 95450 m/sec, 9110981 t fired, .
Time elapsed: 20 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/200 10/32 DoubleLock-PT-p1s1-CTLFireability-09 2345138 m, 91572 m/sec, 11321351 t fired, .
Time elapsed: 25 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/200 12/32 DoubleLock-PT-p1s1-CTLFireability-09 2817944 m, 94561 m/sec, 13603816 t fired, .
Time elapsed: 30 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/200 14/32 DoubleLock-PT-p1s1-CTLFireability-09 3293285 m, 95068 m/sec, 15898600 t fired, .
Time elapsed: 35 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/200 16/32 DoubleLock-PT-p1s1-CTLFireability-09 3766971 m, 94737 m/sec, 18185352 t fired, .
Time elapsed: 40 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/200 18/32 DoubleLock-PT-p1s1-CTLFireability-09 4248775 m, 96360 m/sec, 20511276 t fired, .
Time elapsed: 45 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/200 20/32 DoubleLock-PT-p1s1-CTLFireability-09 4725577 m, 95360 m/sec, 22813135 t fired, .
Time elapsed: 50 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 55/200 22/32 DoubleLock-PT-p1s1-CTLFireability-09 5198177 m, 94520 m/sec, 25094594 t fired, .
Time elapsed: 55 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/200 24/32 DoubleLock-PT-p1s1-CTLFireability-09 5666326 m, 93629 m/sec, 27354652 t fired, .
Time elapsed: 60 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 65/200 26/32 DoubleLock-PT-p1s1-CTLFireability-09 6134096 m, 93554 m/sec, 29612878 t fired, .
Time elapsed: 65 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 70/200 28/32 DoubleLock-PT-p1s1-CTLFireability-09 6597632 m, 92707 m/sec, 31850587 t fired, .
Time elapsed: 70 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 75/200 30/32 DoubleLock-PT-p1s1-CTLFireability-09 7063546 m, 93182 m/sec, 34099863 t fired, .
Time elapsed: 75 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 80/200 32/32 DoubleLock-PT-p1s1-CTLFireability-09 7522297 m, 91750 m/sec, 36314522 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 78 (type EXCL) for 77 DoubleLock-PT-p1s1-CTLFireability-15
lola: time limit : 206 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 5/206 9/32 DoubleLock-PT-p1s1-CTLFireability-15 2022510 m, 404502 m/sec, 2322135 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 10/206 17/32 DoubleLock-PT-p1s1-CTLFireability-15 4021271 m, 399752 m/sec, 4617011 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
sara: warning, failure of lp_solve (at job 7769)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 15/206 26/32 DoubleLock-PT-p1s1-CTLFireability-15 6010805 m, 397906 m/sec, 6901289 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 78 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 3 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 75 (type EXCL) for 66 DoubleLock-PT-p1s1-CTLFireability-14
lola: time limit : 218 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 CTL EXCL 5/218 7/32 DoubleLock-PT-p1s1-CTLFireability-14 1620054 m, 324010 m/sec, 1860060 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 CTL EXCL 10/218 14/32 DoubleLock-PT-p1s1-CTLFireability-14 3102136 m, 296416 m/sec, 3561709 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 CTL EXCL 15/218 20/32 DoubleLock-PT-p1s1-CTLFireability-14 4582287 m, 296030 m/sec, 5261141 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 CTL EXCL 20/218 26/32 DoubleLock-PT-p1s1-CTLFireability-14 6045125 m, 292567 m/sec, 6940694 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 CTL EXCL 25/218 32/32 DoubleLock-PT-p1s1-CTLFireability-14 7502951 m, 291565 m/sec, 8614497 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 75 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 64 (type EXCL) for 63 DoubleLock-PT-p1s1-CTLFireability-13
lola: time limit : 231 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 5/231 4/32 DoubleLock-PT-p1s1-CTLFireability-13 887873 m, 177574 m/sec, 1019406 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 10/231 8/32 DoubleLock-PT-p1s1-CTLFireability-13 1789625 m, 180350 m/sec, 2054750 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 15/231 12/32 DoubleLock-PT-p1s1-CTLFireability-13 2673771 m, 176829 m/sec, 3069880 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 20/231 15/32 DoubleLock-PT-p1s1-CTLFireability-13 3549638 m, 175173 m/sec, 4075507 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 25/231 19/32 DoubleLock-PT-p1s1-CTLFireability-13 4425462 m, 175164 m/sec, 5081084 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 30/231 23/32 DoubleLock-PT-p1s1-CTLFireability-13 5300244 m, 174956 m/sec, 6085461 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 35/231 26/32 DoubleLock-PT-p1s1-CTLFireability-13 6158035 m, 171558 m/sec, 7070332 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 40/231 30/32 DoubleLock-PT-p1s1-CTLFireability-13 7025376 m, 173468 m/sec, 8066169 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 64 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 61 (type EXCL) for 60 DoubleLock-PT-p1s1-CTLFireability-12
lola: time limit : 244 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-12
lola: result : true
lola: markings : 72
lola: fired transitions : 73
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 34 DoubleLock-PT-p1s1-CTLFireability-10
lola: time limit : 263 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 34 DoubleLock-PT-p1s1-CTLFireability-10
lola: time limit : 285 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-10
lola: result : true
lola: markings : 26
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 DoubleLock-PT-p1s1-CTLFireability-05
lola: time limit : 310 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/310 10/32 DoubleLock-PT-p1s1-CTLFireability-05 2244998 m, 448999 m/sec, 2577590 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/310 19/32 DoubleLock-PT-p1s1-CTLFireability-05 4306461 m, 412292 m/sec, 4944453 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/310 27/32 DoubleLock-PT-p1s1-CTLFireability-05 6330930 m, 404893 m/sec, 7268843 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 DoubleLock-PT-p1s1-CTLFireability-03
lola: time limit : 340 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/340 9/32 DoubleLock-PT-p1s1-CTLFireability-03 1949341 m, 389868 m/sec, 2445169 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/340 17/32 DoubleLock-PT-p1s1-CTLFireability-03 3841997 m, 378531 m/sec, 4818664 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/340 24/32 DoubleLock-PT-p1s1-CTLFireability-03 5702734 m, 372147 m/sec, 7151980 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/340 32/32 DoubleLock-PT-p1s1-CTLFireability-03 7511150 m, 361683 m/sec, 9419941 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 2 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 88 (type EXCL) for 66 DoubleLock-PT-p1s1-CTLFireability-14
lola: time limit : 375 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 1 1 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
88 EFAGEF EXCL 5/375 9/32 DoubleLock-PT-p1s1-CTLFireability-14 2255096 m, 451019 m/sec, 2589181 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 1 1 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
88 EFAGEF EXCL 10/375 18/32 DoubleLock-PT-p1s1-CTLFireability-14 4594368 m, 467854 m/sec, 5275011 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 1 1 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
88 EFAGEF EXCL 15/375 27/32 DoubleLock-PT-p1s1-CTLFireability-14 6856842 m, 452494 m/sec, 7872667 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 88 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-04: AGAF 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 1 0 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 3 0 0 7 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-14: CONJ 0 1 0 0 3 0 2 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 87 (type EXCL) for 12 DoubleLock-PT-p1s1-CTLFireability-04
lola: time limit : 419 sec
lola: memory limit: 32 pages
lola: FINISHED task # 87 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-04
lola: result : true
lola: markings : 39
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 86 (type EXCL) for 66 DoubleLock-PT-p1s1-CTLFireability-14
lola: time limit : 479 sec
lola: memory limit: 32 pages
lola: FINISHED task # 86 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-14
lola: result : true
lola: markings : 27
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 83 (type EXCL) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 559 sec
lola: memory limit: 32 pages
lola: FINISHED task # 83 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : true
lola: markings : 29
lola: fired transitions : 28
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 82 (type EXCL) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 671 sec
lola: memory limit: 32 pages
lola: FINISHED task # 82 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-11
lola: result : true
lola: markings : 27
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DoubleLock-PT-p1s1-CTLFireability-01
lola: time limit : 838 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-01
lola: result : true
lola: markings : 27
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 18 DoubleLock-PT-p1s1-CTLFireability-06
lola: time limit : 1118 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 5/1118 3/32 DoubleLock-PT-p1s1-CTLFireability-06 617695 m, 123539 m/sec, 3179979 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 10/1118 6/32 DoubleLock-PT-p1s1-CTLFireability-06 1212564 m, 118973 m/sec, 6242440 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 15/1118 8/32 DoubleLock-PT-p1s1-CTLFireability-06 1796516 m, 116790 m/sec, 9248724 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 20/1118 10/32 DoubleLock-PT-p1s1-CTLFireability-06 2338559 m, 108408 m/sec, 12039221 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 25/1118 12/32 DoubleLock-PT-p1s1-CTLFireability-06 2850713 m, 102430 m/sec, 14675884 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 30/1118 15/32 DoubleLock-PT-p1s1-CTLFireability-06 3387636 m, 107384 m/sec, 17440040 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 35/1118 17/32 DoubleLock-PT-p1s1-CTLFireability-06 3934515 m, 109375 m/sec, 20255460 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 40/1118 19/32 DoubleLock-PT-p1s1-CTLFireability-06 4482043 m, 109505 m/sec, 23074183 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 45/1118 22/32 DoubleLock-PT-p1s1-CTLFireability-06 5022106 m, 108012 m/sec, 25854541 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 50/1118 24/32 DoubleLock-PT-p1s1-CTLFireability-06 5584255 m, 112429 m/sec, 28748549 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 55/1118 26/32 DoubleLock-PT-p1s1-CTLFireability-06 6140257 m, 111200 m/sec, 31610947 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 60/1118 29/32 DoubleLock-PT-p1s1-CTLFireability-06 6698554 m, 111659 m/sec, 34485104 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 1 0 3 0 0 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 65/1118 31/32 DoubleLock-PT-p1s1-CTLFireability-06 7257159 m, 111721 m/sec, 37360921 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 21 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 1 0 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 58 (type EXCL) for 41 DoubleLock-PT-p1s1-CTLFireability-11
lola: time limit : 1642 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 1 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 5/1642 9/32 DoubleLock-PT-p1s1-CTLFireability-11 2006323 m, 401264 m/sec, 2303633 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 1 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 10/1642 17/32 DoubleLock-PT-p1s1-CTLFireability-11 3980102 m, 394755 m/sec, 4569824 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 1 0 9 0 0 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 15/1642 25/32 DoubleLock-PT-p1s1-CTLFireability-11 5915984 m, 387176 m/sec, 6792503 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 58 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 DoubleLock-PT-p1s1-CTLFireability-07
lola: time limit : 3265 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/3265 4/32 DoubleLock-PT-p1s1-CTLFireability-07 759717 m, 151943 m/sec, 2335418 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/3265 7/32 DoubleLock-PT-p1s1-CTLFireability-07 1521854 m, 152427 m/sec, 4678284 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/3265 10/32 DoubleLock-PT-p1s1-CTLFireability-07 2291648 m, 153958 m/sec, 7044688 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/3265 13/32 DoubleLock-PT-p1s1-CTLFireability-07 3049585 m, 151587 m/sec, 9374615 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/3265 16/32 DoubleLock-PT-p1s1-CTLFireability-07 3806584 m, 151399 m/sec, 11701709 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/3265 20/32 DoubleLock-PT-p1s1-CTLFireability-07 4557724 m, 150228 m/sec, 14010751 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/3265 23/32 DoubleLock-PT-p1s1-CTLFireability-07 5265216 m, 141498 m/sec, 16185654 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/3265 26/32 DoubleLock-PT-p1s1-CTLFireability-07 6005086 m, 147974 m/sec, 18460045 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/3265 29/32 DoubleLock-PT-p1s1-CTLFireability-07 6744759 m, 147934 m/sec, 20733880 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 50/3265 32/32 DoubleLock-PT-p1s1-CTLFireability-07 7455131 m, 142074 m/sec, 22917618 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for DoubleLock-PT-p1s1-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 555 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 560 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 565 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 585 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 590 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 595 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 600 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 605 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 610 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 615 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 620 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 625 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 630 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 635 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 640 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 645 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 650 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 655 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 660 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 665 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 670 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 675 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 680 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 685 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 690 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 695 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 700 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 705 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 710 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 715 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 720 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 725 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 730 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 735 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 740 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 745 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 750 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 755 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 760 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 765 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 770 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 775 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 780 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 785 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 790 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 795 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 800 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 805 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 810 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 815 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 820 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 825 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 830 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 835 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 840 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 845 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 850 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 855 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 860 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 865 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 870 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 875 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 880 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 885 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 890 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 895 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 900 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 905 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 910 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 915 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 920 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 925 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 930 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 935 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 940 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 945 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 950 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 955 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 960 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 965 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 970 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 975 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 980 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 985 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 990 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 995 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1000 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1005 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1010 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1015 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1020 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1025 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1030 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1035 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1040 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1045 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1050 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1055 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1060 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1065 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1070 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1075 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1080 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1085 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1090 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1095 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1100 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1105 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1110 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1115 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1120 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1125 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1130 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1135 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1140 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1145 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1150 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1155 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1160 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1165 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1170 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1175 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1180 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1185 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1190 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1195 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1200 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1205 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1210 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1215 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1220 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1225 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1230 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1235 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1240 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1245 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1250 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1255 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1260 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1265 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1270 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1275 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1280 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1285 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1290 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1295 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1300 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1305 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1310 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1315 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1320 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1325 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1330 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1335 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1340 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1345 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1350 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1355 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1360 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1365 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1370 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1375 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1380 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1385 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1390 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1395 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1400 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1405 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1410 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1415 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1420 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1425 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1430 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1435 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1440 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1445 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1450 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1455 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1460 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1465 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1470 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1475 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1480 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1485 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1490 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1495 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1500 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1505 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1510 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1515 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1520 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1525 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1530 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1535 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1540 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1545 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1550 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1555 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1560 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1565 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1570 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1575 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1580 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1585 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1590 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1595 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1600 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1605 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1610 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1615 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1620 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1625 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1630 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1635 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1640 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1645 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1650 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1655 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1660 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1665 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1670 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1675 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1680 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1685 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1690 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1695 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1700 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1705 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1710 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1715 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1720 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1725 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1730 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1735 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1740 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1745 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1750 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1755 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1760 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1765 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1770 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1775 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1780 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1785 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1790 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1795 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1800 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1805 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1810 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1815 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1820 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1825 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1830 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1835 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1840 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1845 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1850 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1855 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1860 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1865 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1870 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1875 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1880 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1885 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1890 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1895 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1900 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1905 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1910 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1915 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1920 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1925 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1930 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1935 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1940 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1945 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1950 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1955 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1960 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1965 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1970 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1975 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1980 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1985 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1990 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1995 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2000 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2005 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2010 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2015 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2020 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2025 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2030 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2035 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2040 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2045 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2050 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2055 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-11: DISJ 0 0 0 0 9 0 1 3
DoubleLock-PT-p1s1-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2060 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleLock-PT-p1s1-CTLFireability-00: INITIAL true preprocessing
DoubleLock-PT-p1s1-CTLFireability-01: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-02: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-04: AGAF false state space /EFEG
DoubleLock-PT-p1s1-CTLFireability-08: INITIAL false preprocessing
DoubleLock-PT-p1s1-CTLFireability-10: DISJ true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-12: CTL true CTL model checker
DoubleLock-PT-p1s1-CTLFireability-14: CONJ false state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleLock-PT-p1s1-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleLock-PT-p1s1-CTLFireability-06: DISJ 0 0 0 0 3 0 1 0
DoubleLock-PT-p1s1-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-167819412800506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s1.tgz
mv DoubleLock-PT-p1s1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;