About the Execution of LoLA for DoubleExponent-PT-200
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 10119.275 | 3600000.00 | 4956226.00 | 9800.60 | F??F??????????F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r134-smll-167819412800498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DoubleExponent-PT-200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r134-smll-167819412800498
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.9M
-rw-r--r-- 1 mcc users 7.3K Feb 26 13:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 13:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 13:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 13:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 26 13:32 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 26 13:32 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 13:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Feb 26 13:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.5M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-00
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-01
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-02
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-03
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-04
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-05
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-06
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-07
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-08
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-09
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-10
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-11
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-12
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-13
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-14
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678471881732
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DoubleExponent-PT-200
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DoubleExponent-PT-200
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DoubleExponent-PT-200-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleExponent-PT-200-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleExponent-PT-200-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 6137432 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16161784 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 185 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 190 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 195 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 200 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 205 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 210 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 215 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 220 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 225 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 230 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 235 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 240 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 245 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 250 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 5.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: LAUNCH task # 6 (type EXCL) for 3 DoubleExponent-PT-200-CTLFireability-01
lola: time limit : 152 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 1 1 0 4 0 0 0
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 4/152 1/32 DoubleExponent-PT-200-CTLFireability-01 20557 m, 4111 m/sec, 20558 t fired, .
Time elapsed: 255 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: Created skeleton in 7.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 3 DoubleExponent-PT-200-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 3 DoubleExponent-PT-200-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SRCH) for 3 DoubleExponent-PT-200-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 70 (type SRCH) for DoubleExponent-PT-200-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 66 (type FNDP) for 33 DoubleExponent-PT-200-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type FNDP) for DoubleExponent-PT-200-CTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 65 (type EQUN) for DoubleExponent-PT-200-CTLFireability-01 (obsolete)
lola: LAUNCH task # 68 (type EQUN) for 33 DoubleExponent-PT-200-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 33 DoubleExponent-PT-200-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 71 (type SRCH) for DoubleExponent-PT-200-CTLFireability-07
lola: result : unknown
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-65.sara.
sara: try reading problem file /home/mcc/execution/CTLFireability-68.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 9/186 2/32 DoubleExponent-PT-200-CTLFireability-01 47780 m, 5444 m/sec, 47781 t fired, .
66 EF FNDP 2/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 10342 t fired, 1029 attempts, .
68 EF STEQ 1/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 260 secs. Pages in use: 3
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 14/186 3/32 DoubleExponent-PT-200-CTLFireability-01 71273 m, 4698 m/sec, 71273 t fired, .
66 EF FNDP 7/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 64671 t fired, 6600 attempts, .
68 EF STEQ 6/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 265 secs. Pages in use: 3
# running tasks: 3 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 19/197 4/32 DoubleExponent-PT-200-CTLFireability-01 98512 m, 5447 m/sec, 98512 t fired, .
66 EF FNDP 12/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 122112 t fired, 12468 attempts, .
68 EF STEQ 11/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 270 secs. Pages in use: 4
# running tasks: 3 of 4 Visible: 16
lola: Created skeleton in 5.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 25/209 7/32 DoubleExponent-PT-200-CTLFireability-01 182264 m, 16750 m/sec, 182265 t fired, .
66 EF FNDP 18/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 299764 t fired, 30641 attempts, .
68 EF STEQ 17/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 276 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 30/209 11/32 DoubleExponent-PT-200-CTLFireability-01 280423 m, 19631 m/sec, 280424 t fired, .
66 EF FNDP 23/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 509987 t fired, 52200 attempts, .
68 EF STEQ 22/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 281 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 35/209 15/32 DoubleExponent-PT-200-CTLFireability-01 387055 m, 21326 m/sec, 387056 t fired, .
66 EF FNDP 28/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 727777 t fired, 74520 attempts, .
68 EF STEQ 27/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 286 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 40/209 19/32 DoubleExponent-PT-200-CTLFireability-01 493734 m, 21335 m/sec, 493735 t fired, .
66 EF FNDP 33/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 946327 t fired, 96845 attempts, .
68 EF STEQ 32/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 291 secs. Pages in use: 19
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 45/209 24/32 DoubleExponent-PT-200-CTLFireability-01 600081 m, 21269 m/sec, 600082 t fired, .
66 EF FNDP 38/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 1165027 t fired, 119213 attempts, .
68 EF STEQ 37/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 296 secs. Pages in use: 24
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 50/209 28/32 DoubleExponent-PT-200-CTLFireability-01 706360 m, 21255 m/sec, 706361 t fired, .
66 EF FNDP 43/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 1383704 t fired, 141511 attempts, .
68 EF STEQ 42/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 301 secs. Pages in use: 28
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 1 0 6 0 0 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 55/209 32/32 DoubleExponent-PT-200-CTLFireability-01 812724 m, 21272 m/sec, 812725 t fired, .
66 EF FNDP 48/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 1601202 t fired, 163820 attempts, .
68 EF STEQ 47/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 306 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 6 (type EXCL) for DoubleExponent-PT-200-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 53/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 1819620 t fired, 186110 attempts, .
68 EF STEQ 52/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 311 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 58 (type EXCL) for 57 DoubleExponent-PT-200-CTLFireability-15
lola: time limit : 219 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 5/219 2/32 DoubleExponent-PT-200-CTLFireability-15 36305 m, 7261 m/sec, 72610 t fired, .
66 EF FNDP 58/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 2036640 t fired, 208265 attempts, .
68 EF STEQ 57/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 10/219 4/32 DoubleExponent-PT-200-CTLFireability-15 72739 m, 7286 m/sec, 145477 t fired, .
66 EF FNDP 63/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 2255713 t fired, 230688 attempts, .
68 EF STEQ 62/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 321 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
sara: warning, failure of lp_solve (at job 165)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 2 0 2 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 15/219 5/32 DoubleExponent-PT-200-CTLFireability-15 109232 m, 7298 m/sec, 218463 t fired, .
66 EF FNDP 68/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 2475145 t fired, 253184 attempts, .
68 EF STEQ 67/3341 0/5 DoubleExponent-PT-200-CTLFireability-07 sara is running.
Time elapsed: 326 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: FINISHED task # 68 (type EQUN) for DoubleExponent-PT-200-CTLFireability-07
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 20/219 7/32 DoubleExponent-PT-200-CTLFireability-15 146242 m, 7402 m/sec, 292484 t fired, .
66 EF FNDP 73/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 2695364 t fired, 275720 attempts, .
Time elapsed: 331 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 25/219 8/32 DoubleExponent-PT-200-CTLFireability-15 183088 m, 7369 m/sec, 366175 t fired, .
66 EF FNDP 78/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 2915150 t fired, 298339 attempts, .
Time elapsed: 336 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 30/219 10/32 DoubleExponent-PT-200-CTLFireability-15 220121 m, 7406 m/sec, 440241 t fired, .
66 EF FNDP 83/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 3136324 t fired, 321082 attempts, .
Time elapsed: 341 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 35/219 11/32 DoubleExponent-PT-200-CTLFireability-15 256755 m, 7326 m/sec, 513510 t fired, .
66 EF FNDP 88/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 3357874 t fired, 343849 attempts, .
Time elapsed: 346 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 40/219 13/32 DoubleExponent-PT-200-CTLFireability-15 294094 m, 7467 m/sec, 588187 t fired, .
66 EF FNDP 93/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 3579302 t fired, 366553 attempts, .
Time elapsed: 351 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 45/219 14/32 DoubleExponent-PT-200-CTLFireability-15 330663 m, 7313 m/sec, 661326 t fired, .
66 EF FNDP 98/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 3798855 t fired, 389040 attempts, .
Time elapsed: 356 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 50/219 16/32 DoubleExponent-PT-200-CTLFireability-15 367279 m, 7323 m/sec, 734558 t fired, .
66 EF FNDP 103/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 4019557 t fired, 411651 attempts, .
Time elapsed: 361 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 55/219 17/32 DoubleExponent-PT-200-CTLFireability-15 404210 m, 7386 m/sec, 808419 t fired, .
66 EF FNDP 108/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 4239867 t fired, 434210 attempts, .
Time elapsed: 366 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 60/219 19/32 DoubleExponent-PT-200-CTLFireability-15 440578 m, 7273 m/sec, 881156 t fired, .
66 EF FNDP 113/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 4458147 t fired, 456630 attempts, .
Time elapsed: 371 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 65/219 20/32 DoubleExponent-PT-200-CTLFireability-15 476986 m, 7281 m/sec, 953971 t fired, .
66 EF FNDP 118/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 4678456 t fired, 479156 attempts, .
Time elapsed: 376 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 70/219 22/32 DoubleExponent-PT-200-CTLFireability-15 513278 m, 7258 m/sec, 1026556 t fired, .
66 EF FNDP 123/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 4898947 t fired, 501797 attempts, .
Time elapsed: 381 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 6 0 1 4
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 75/219 23/32 DoubleExponent-PT-200-CTLFireability-15 549831 m, 7310 m/sec, 1099661 t fired, .
66 EF FNDP 128/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 5120679 t fired, 524385 attempts, .
Time elapsed: 386 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: FINISHED task # 65 (type EQUN) for DoubleExponent-PT-200-CTLFireability-01
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 80/219 25/32 DoubleExponent-PT-200-CTLFireability-15 587717 m, 7577 m/sec, 1175434 t fired, .
66 EF FNDP 133/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 5346120 t fired, 547538 attempts, .
Time elapsed: 391 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 85/219 27/32 DoubleExponent-PT-200-CTLFireability-15 626331 m, 7722 m/sec, 1252661 t fired, .
66 EF FNDP 138/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 5577032 t fired, 571213 attempts, .
Time elapsed: 396 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 90/219 28/32 DoubleExponent-PT-200-CTLFireability-15 664845 m, 7702 m/sec, 1329690 t fired, .
66 EF FNDP 143/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 5803876 t fired, 594460 attempts, .
Time elapsed: 401 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 95/219 30/32 DoubleExponent-PT-200-CTLFireability-15 703448 m, 7720 m/sec, 1406895 t fired, .
66 EF FNDP 148/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 6033114 t fired, 617960 attempts, .
Time elapsed: 406 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 100/219 31/32 DoubleExponent-PT-200-CTLFireability-15 741970 m, 7704 m/sec, 1483940 t fired, .
66 EF FNDP 153/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 6263484 t fired, 641493 attempts, .
Time elapsed: 411 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 58 (type EXCL) for DoubleExponent-PT-200-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 158/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 6493514 t fired, 665034 attempts, .
Time elapsed: 416 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 55 (type EXCL) for 54 DoubleExponent-PT-200-CTLFireability-14
lola: time limit : 227 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for DoubleExponent-PT-200-CTLFireability-14
lola: result : false
lola: markings : 25
lola: fired transitions : 49
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 DoubleExponent-PT-200-CTLFireability-13
lola: time limit : 244 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/244 4/32 DoubleExponent-PT-200-CTLFireability-13 75390 m, 15078 m/sec, 75390 t fired, .
66 EF FNDP 163/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 6722568 t fired, 688633 attempts, .
Time elapsed: 421 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 10/244 7/32 DoubleExponent-PT-200-CTLFireability-13 150826 m, 15087 m/sec, 150827 t fired, .
66 EF FNDP 168/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 6951543 t fired, 712083 attempts, .
Time elapsed: 426 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 15/244 10/32 DoubleExponent-PT-200-CTLFireability-13 226461 m, 15127 m/sec, 226462 t fired, .
66 EF FNDP 173/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 7181252 t fired, 735625 attempts, .
Time elapsed: 431 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 20/244 13/32 DoubleExponent-PT-200-CTLFireability-13 301831 m, 15074 m/sec, 301831 t fired, .
66 EF FNDP 178/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 7410586 t fired, 759090 attempts, .
Time elapsed: 436 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 25/244 16/32 DoubleExponent-PT-200-CTLFireability-13 377295 m, 15092 m/sec, 377296 t fired, .
66 EF FNDP 183/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 7639913 t fired, 782601 attempts, .
Time elapsed: 441 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 30/244 19/32 DoubleExponent-PT-200-CTLFireability-13 452705 m, 15082 m/sec, 452706 t fired, .
66 EF FNDP 188/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 7869166 t fired, 806213 attempts, .
Time elapsed: 446 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 35/244 23/32 DoubleExponent-PT-200-CTLFireability-13 528195 m, 15098 m/sec, 528196 t fired, .
66 EF FNDP 193/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 8098426 t fired, 829773 attempts, .
Time elapsed: 451 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 40/244 26/32 DoubleExponent-PT-200-CTLFireability-13 603736 m, 15108 m/sec, 603737 t fired, .
66 EF FNDP 198/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 8327706 t fired, 853430 attempts, .
Time elapsed: 456 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 45/244 29/32 DoubleExponent-PT-200-CTLFireability-13 679328 m, 15118 m/sec, 679329 t fired, .
66 EF FNDP 203/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 8557644 t fired, 876923 attempts, .
Time elapsed: 461 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 50/244 32/32 DoubleExponent-PT-200-CTLFireability-13 754714 m, 15077 m/sec, 754714 t fired, .
66 EF FNDP 208/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 8787003 t fired, 900375 attempts, .
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for DoubleExponent-PT-200-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 213/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 9017503 t fired, 923966 attempts, .
Time elapsed: 471 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 49 (type EXCL) for 48 DoubleExponent-PT-200-CTLFireability-12
lola: time limit : 260 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/260 4/32 DoubleExponent-PT-200-CTLFireability-12 75513 m, 15102 m/sec, 75513 t fired, .
66 EF FNDP 218/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 9246512 t fired, 947443 attempts, .
Time elapsed: 476 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 10/260 7/32 DoubleExponent-PT-200-CTLFireability-12 151166 m, 15130 m/sec, 151166 t fired, .
66 EF FNDP 223/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 9475652 t fired, 970920 attempts, .
Time elapsed: 481 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 15/260 10/32 DoubleExponent-PT-200-CTLFireability-12 226797 m, 15126 m/sec, 226797 t fired, .
66 EF FNDP 228/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 9704589 t fired, 994394 attempts, .
Time elapsed: 486 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 20/260 13/32 DoubleExponent-PT-200-CTLFireability-12 302199 m, 15080 m/sec, 302199 t fired, .
66 EF FNDP 233/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 9933873 t fired, 1017977 attempts, .
Time elapsed: 491 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 25/260 16/32 DoubleExponent-PT-200-CTLFireability-12 377629 m, 15086 m/sec, 377629 t fired, .
66 EF FNDP 238/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 10163166 t fired, 1041435 attempts, .
Time elapsed: 496 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 30/260 19/32 DoubleExponent-PT-200-CTLFireability-12 453061 m, 15086 m/sec, 453061 t fired, .
66 EF FNDP 243/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 10392890 t fired, 1064926 attempts, .
Time elapsed: 501 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 35/260 23/32 DoubleExponent-PT-200-CTLFireability-12 528591 m, 15106 m/sec, 528591 t fired, .
66 EF FNDP 248/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 10622567 t fired, 1088569 attempts, .
Time elapsed: 506 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 40/260 26/32 DoubleExponent-PT-200-CTLFireability-12 604028 m, 15087 m/sec, 604028 t fired, .
66 EF FNDP 253/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 10852306 t fired, 1112147 attempts, .
Time elapsed: 511 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 45/260 29/32 DoubleExponent-PT-200-CTLFireability-12 679502 m, 15094 m/sec, 679502 t fired, .
66 EF FNDP 258/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 11081873 t fired, 1135782 attempts, .
Time elapsed: 516 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 50/260 32/32 DoubleExponent-PT-200-CTLFireability-12 754905 m, 15080 m/sec, 754905 t fired, .
66 EF FNDP 263/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 11311379 t fired, 1159341 attempts, .
Time elapsed: 521 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 49 (type EXCL) for DoubleExponent-PT-200-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 268/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 11541735 t fired, 1183074 attempts, .
Time elapsed: 526 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 DoubleExponent-PT-200-CTLFireability-11
lola: time limit : 279 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/279 4/32 DoubleExponent-PT-200-CTLFireability-11 75471 m, 15094 m/sec, 75473 t fired, .
66 EF FNDP 273/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 11771041 t fired, 1206545 attempts, .
Time elapsed: 531 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/279 7/32 DoubleExponent-PT-200-CTLFireability-11 151087 m, 15123 m/sec, 151089 t fired, .
66 EF FNDP 278/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 12000389 t fired, 1230058 attempts, .
Time elapsed: 536 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/279 10/32 DoubleExponent-PT-200-CTLFireability-11 226654 m, 15113 m/sec, 226656 t fired, .
66 EF FNDP 283/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 12230249 t fired, 1253619 attempts, .
Time elapsed: 541 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/279 13/32 DoubleExponent-PT-200-CTLFireability-11 302224 m, 15114 m/sec, 302226 t fired, .
66 EF FNDP 288/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 12460382 t fired, 1277119 attempts, .
Time elapsed: 546 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/279 16/32 DoubleExponent-PT-200-CTLFireability-11 377683 m, 15091 m/sec, 377685 t fired, .
66 EF FNDP 293/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 12690424 t fired, 1300669 attempts, .
Time elapsed: 551 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/279 19/32 DoubleExponent-PT-200-CTLFireability-11 453202 m, 15103 m/sec, 453204 t fired, .
66 EF FNDP 298/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 12920376 t fired, 1324230 attempts, .
Time elapsed: 556 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 35/279 23/32 DoubleExponent-PT-200-CTLFireability-11 528639 m, 15087 m/sec, 528641 t fired, .
66 EF FNDP 303/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 13150245 t fired, 1347764 attempts, .
Time elapsed: 561 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 40/279 26/32 DoubleExponent-PT-200-CTLFireability-11 604074 m, 15087 m/sec, 604076 t fired, .
66 EF FNDP 308/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 13380204 t fired, 1371191 attempts, .
Time elapsed: 566 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 45/279 29/32 DoubleExponent-PT-200-CTLFireability-11 679442 m, 15073 m/sec, 679444 t fired, .
66 EF FNDP 313/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 13609708 t fired, 1394764 attempts, .
Time elapsed: 571 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 50/279 32/32 DoubleExponent-PT-200-CTLFireability-11 754870 m, 15085 m/sec, 754872 t fired, .
66 EF FNDP 318/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 13839484 t fired, 1418244 attempts, .
Time elapsed: 576 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for DoubleExponent-PT-200-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 323/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 14069848 t fired, 1441751 attempts, .
Time elapsed: 581 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 43 (type EXCL) for 42 DoubleExponent-PT-200-CTLFireability-10
lola: time limit : 301 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/301 4/32 DoubleExponent-PT-200-CTLFireability-10 75349 m, 15069 m/sec, 75350 t fired, .
66 EF FNDP 328/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 14298575 t fired, 1465327 attempts, .
Time elapsed: 586 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/301 7/32 DoubleExponent-PT-200-CTLFireability-10 150711 m, 15072 m/sec, 150712 t fired, .
66 EF FNDP 333/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 14527904 t fired, 1488986 attempts, .
Time elapsed: 591 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/301 10/32 DoubleExponent-PT-200-CTLFireability-10 226291 m, 15116 m/sec, 226292 t fired, .
66 EF FNDP 338/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 14757853 t fired, 1512456 attempts, .
Time elapsed: 596 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/301 13/32 DoubleExponent-PT-200-CTLFireability-10 301573 m, 15056 m/sec, 301574 t fired, .
66 EF FNDP 343/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 14987079 t fired, 1536093 attempts, .
Time elapsed: 601 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/301 16/32 DoubleExponent-PT-200-CTLFireability-10 376994 m, 15084 m/sec, 376995 t fired, .
66 EF FNDP 348/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 15216938 t fired, 1559656 attempts, .
Time elapsed: 606 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/301 19/32 DoubleExponent-PT-200-CTLFireability-10 452222 m, 15045 m/sec, 452222 t fired, .
66 EF FNDP 353/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 15447297 t fired, 1583184 attempts, .
Time elapsed: 611 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/301 23/32 DoubleExponent-PT-200-CTLFireability-10 527425 m, 15040 m/sec, 527426 t fired, .
66 EF FNDP 358/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 15677250 t fired, 1606715 attempts, .
Time elapsed: 616 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/301 26/32 DoubleExponent-PT-200-CTLFireability-10 602630 m, 15041 m/sec, 602631 t fired, .
66 EF FNDP 363/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 15907122 t fired, 1630322 attempts, .
Time elapsed: 621 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/301 29/32 DoubleExponent-PT-200-CTLFireability-10 677914 m, 15056 m/sec, 677915 t fired, .
66 EF FNDP 368/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 16137275 t fired, 1653862 attempts, .
Time elapsed: 626 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/301 32/32 DoubleExponent-PT-200-CTLFireability-10 753279 m, 15073 m/sec, 753280 t fired, .
66 EF FNDP 373/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 16367202 t fired, 1677596 attempts, .
Time elapsed: 631 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for DoubleExponent-PT-200-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 378/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 16597405 t fired, 1701189 attempts, .
Time elapsed: 636 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 DoubleExponent-PT-200-CTLFireability-08
lola: time limit : 329 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/329 4/32 DoubleExponent-PT-200-CTLFireability-08 75611 m, 15122 m/sec, 75611 t fired, .
66 EF FNDP 383/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 16826781 t fired, 1724825 attempts, .
Time elapsed: 641 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/329 7/32 DoubleExponent-PT-200-CTLFireability-08 151396 m, 15157 m/sec, 151396 t fired, .
66 EF FNDP 388/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 17055729 t fired, 1748445 attempts, .
Time elapsed: 646 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/329 10/32 DoubleExponent-PT-200-CTLFireability-08 227197 m, 15160 m/sec, 227197 t fired, .
66 EF FNDP 393/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 17285336 t fired, 1771926 attempts, .
Time elapsed: 651 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/329 13/32 DoubleExponent-PT-200-CTLFireability-08 302876 m, 15135 m/sec, 302876 t fired, .
66 EF FNDP 398/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 17515056 t fired, 1795417 attempts, .
Time elapsed: 656 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/329 16/32 DoubleExponent-PT-200-CTLFireability-08 378535 m, 15131 m/sec, 378534 t fired, .
66 EF FNDP 403/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 17744843 t fired, 1818892 attempts, .
Time elapsed: 661 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/329 19/32 DoubleExponent-PT-200-CTLFireability-08 454154 m, 15123 m/sec, 454154 t fired, .
66 EF FNDP 408/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 17974222 t fired, 1842531 attempts, .
Time elapsed: 666 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/329 23/32 DoubleExponent-PT-200-CTLFireability-08 529704 m, 15110 m/sec, 529704 t fired, .
66 EF FNDP 413/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 18203662 t fired, 1865989 attempts, .
Time elapsed: 671 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 40/329 26/32 DoubleExponent-PT-200-CTLFireability-08 605327 m, 15124 m/sec, 605327 t fired, .
66 EF FNDP 418/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 18433410 t fired, 1889396 attempts, .
Time elapsed: 676 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 45/329 29/32 DoubleExponent-PT-200-CTLFireability-08 680977 m, 15130 m/sec, 680977 t fired, .
66 EF FNDP 423/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 18662677 t fired, 1912976 attempts, .
Time elapsed: 681 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 50/329 32/32 DoubleExponent-PT-200-CTLFireability-08 756614 m, 15127 m/sec, 756614 t fired, .
66 EF FNDP 428/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 18892474 t fired, 1936559 attempts, .
Time elapsed: 686 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 37 (type EXCL) for DoubleExponent-PT-200-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 433/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 19123470 t fired, 1960210 attempts, .
Time elapsed: 691 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 DoubleExponent-PT-200-CTLFireability-06
lola: time limit : 363 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/363 2/32 DoubleExponent-PT-200-CTLFireability-06 25501 m, 5100 m/sec, 76502 t fired, .
66 EF FNDP 438/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 19353626 t fired, 1983858 attempts, .
Time elapsed: 696 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/363 3/32 DoubleExponent-PT-200-CTLFireability-06 51042 m, 5108 m/sec, 153125 t fired, .
66 EF FNDP 443/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 19583860 t fired, 2007506 attempts, .
Time elapsed: 701 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/363 4/32 DoubleExponent-PT-200-CTLFireability-06 76603 m, 5112 m/sec, 229807 t fired, .
66 EF FNDP 448/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 19814477 t fired, 2031014 attempts, .
Time elapsed: 706 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/363 5/32 DoubleExponent-PT-200-CTLFireability-06 102137 m, 5106 m/sec, 306410 t fired, .
66 EF FNDP 453/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 20045041 t fired, 2054642 attempts, .
Time elapsed: 711 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/363 6/32 DoubleExponent-PT-200-CTLFireability-06 127613 m, 5095 m/sec, 382839 t fired, .
66 EF FNDP 458/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 20275255 t fired, 2078241 attempts, .
Time elapsed: 716 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/363 7/32 DoubleExponent-PT-200-CTLFireability-06 153180 m, 5113 m/sec, 459540 t fired, .
66 EF FNDP 463/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 20505723 t fired, 2101793 attempts, .
Time elapsed: 721 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/363 8/32 DoubleExponent-PT-200-CTLFireability-06 178707 m, 5105 m/sec, 536119 t fired, .
66 EF FNDP 468/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 20735760 t fired, 2125374 attempts, .
Time elapsed: 726 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/363 9/32 DoubleExponent-PT-200-CTLFireability-06 204246 m, 5107 m/sec, 612738 t fired, .
66 EF FNDP 473/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 20965777 t fired, 2149051 attempts, .
Time elapsed: 731 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/363 10/32 DoubleExponent-PT-200-CTLFireability-06 229789 m, 5108 m/sec, 689366 t fired, .
66 EF FNDP 478/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 21196398 t fired, 2172707 attempts, .
Time elapsed: 736 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/363 11/32 DoubleExponent-PT-200-CTLFireability-06 255308 m, 5103 m/sec, 765924 t fired, .
66 EF FNDP 483/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 21426710 t fired, 2196349 attempts, .
Time elapsed: 741 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/363 12/32 DoubleExponent-PT-200-CTLFireability-06 280816 m, 5101 m/sec, 842446 t fired, .
66 EF FNDP 488/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 21657051 t fired, 2220007 attempts, .
Time elapsed: 746 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/363 13/32 DoubleExponent-PT-200-CTLFireability-06 306319 m, 5100 m/sec, 918955 t fired, .
66 EF FNDP 493/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 21887499 t fired, 2243659 attempts, .
Time elapsed: 751 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 65/363 14/32 DoubleExponent-PT-200-CTLFireability-06 331865 m, 5109 m/sec, 995593 t fired, .
66 EF FNDP 498/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 22118236 t fired, 2267322 attempts, .
Time elapsed: 756 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 70/363 15/32 DoubleExponent-PT-200-CTLFireability-06 357357 m, 5098 m/sec, 1072070 t fired, .
66 EF FNDP 503/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 22348041 t fired, 2290901 attempts, .
Time elapsed: 761 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 75/363 16/32 DoubleExponent-PT-200-CTLFireability-06 382889 m, 5106 m/sec, 1148666 t fired, .
66 EF FNDP 508/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 22578465 t fired, 2314558 attempts, .
Time elapsed: 766 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 80/363 18/32 DoubleExponent-PT-200-CTLFireability-06 408406 m, 5103 m/sec, 1225216 t fired, .
66 EF FNDP 513/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 22808833 t fired, 2338184 attempts, .
Time elapsed: 771 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 85/363 19/32 DoubleExponent-PT-200-CTLFireability-06 433888 m, 5096 m/sec, 1301663 t fired, .
66 EF FNDP 518/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 23039235 t fired, 2361765 attempts, .
Time elapsed: 776 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 90/363 20/32 DoubleExponent-PT-200-CTLFireability-06 459409 m, 5104 m/sec, 1378225 t fired, .
66 EF FNDP 523/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 23269773 t fired, 2385312 attempts, .
Time elapsed: 781 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 95/363 21/32 DoubleExponent-PT-200-CTLFireability-06 484946 m, 5107 m/sec, 1454838 t fired, .
66 EF FNDP 528/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 23500293 t fired, 2408980 attempts, .
Time elapsed: 786 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 100/363 22/32 DoubleExponent-PT-200-CTLFireability-06 510488 m, 5108 m/sec, 1531463 t fired, .
66 EF FNDP 533/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 23730923 t fired, 2432558 attempts, .
Time elapsed: 791 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 105/363 23/32 DoubleExponent-PT-200-CTLFireability-06 535972 m, 5096 m/sec, 1607915 t fired, .
66 EF FNDP 538/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 23961326 t fired, 2456185 attempts, .
Time elapsed: 796 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 110/363 24/32 DoubleExponent-PT-200-CTLFireability-06 561498 m, 5105 m/sec, 1684493 t fired, .
66 EF FNDP 543/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 24191671 t fired, 2479851 attempts, .
Time elapsed: 801 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 115/363 25/32 DoubleExponent-PT-200-CTLFireability-06 587059 m, 5112 m/sec, 1761177 t fired, .
66 EF FNDP 548/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 24422277 t fired, 2503477 attempts, .
Time elapsed: 806 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 120/363 26/32 DoubleExponent-PT-200-CTLFireability-06 612613 m, 5110 m/sec, 1837839 t fired, .
66 EF FNDP 553/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 24652748 t fired, 2527117 attempts, .
Time elapsed: 811 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 125/363 27/32 DoubleExponent-PT-200-CTLFireability-06 638141 m, 5105 m/sec, 1914422 t fired, .
66 EF FNDP 558/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 24883707 t fired, 2550664 attempts, .
Time elapsed: 816 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 130/363 28/32 DoubleExponent-PT-200-CTLFireability-06 663645 m, 5100 m/sec, 1990935 t fired, .
66 EF FNDP 563/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 25113926 t fired, 2574342 attempts, .
Time elapsed: 821 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 135/363 29/32 DoubleExponent-PT-200-CTLFireability-06 689129 m, 5096 m/sec, 2067386 t fired, .
66 EF FNDP 568/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 25344343 t fired, 2597957 attempts, .
Time elapsed: 826 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 140/363 30/32 DoubleExponent-PT-200-CTLFireability-06 714621 m, 5098 m/sec, 2143861 t fired, .
66 EF FNDP 573/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 25575042 t fired, 2621544 attempts, .
Time elapsed: 831 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 145/363 31/32 DoubleExponent-PT-200-CTLFireability-06 740188 m, 5113 m/sec, 2220562 t fired, .
66 EF FNDP 578/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 25805809 t fired, 2645111 attempts, .
Time elapsed: 836 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 150/363 32/32 DoubleExponent-PT-200-CTLFireability-06 765705 m, 5103 m/sec, 2297114 t fired, .
66 EF FNDP 583/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 26036071 t fired, 2668856 attempts, .
Time elapsed: 841 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for DoubleExponent-PT-200-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 588/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 26266765 t fired, 2692432 attempts, .
Time elapsed: 846 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 DoubleExponent-PT-200-CTLFireability-05
lola: time limit : 393 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/393 4/32 DoubleExponent-PT-200-CTLFireability-05 75143 m, 15028 m/sec, 75144 t fired, .
66 EF FNDP 593/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 26495707 t fired, 2716061 attempts, .
Time elapsed: 851 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/393 7/32 DoubleExponent-PT-200-CTLFireability-05 150753 m, 15122 m/sec, 150754 t fired, .
66 EF FNDP 598/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 26724691 t fired, 2739557 attempts, .
Time elapsed: 856 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/393 10/32 DoubleExponent-PT-200-CTLFireability-05 226473 m, 15144 m/sec, 226474 t fired, .
66 EF FNDP 603/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 26953344 t fired, 2763117 attempts, .
Time elapsed: 861 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/393 13/32 DoubleExponent-PT-200-CTLFireability-05 302158 m, 15137 m/sec, 302159 t fired, .
66 EF FNDP 608/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 27182296 t fired, 2786737 attempts, .
Time elapsed: 866 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/393 16/32 DoubleExponent-PT-200-CTLFireability-05 377759 m, 15120 m/sec, 377760 t fired, .
66 EF FNDP 613/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 27411372 t fired, 2810220 attempts, .
Time elapsed: 871 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/393 19/32 DoubleExponent-PT-200-CTLFireability-05 453323 m, 15112 m/sec, 453324 t fired, .
66 EF FNDP 618/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 27640213 t fired, 2833721 attempts, .
Time elapsed: 876 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/393 23/32 DoubleExponent-PT-200-CTLFireability-05 528933 m, 15122 m/sec, 528934 t fired, .
66 EF FNDP 623/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 27869058 t fired, 2857253 attempts, .
Time elapsed: 881 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/393 26/32 DoubleExponent-PT-200-CTLFireability-05 604573 m, 15128 m/sec, 604574 t fired, .
66 EF FNDP 628/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 28097871 t fired, 2880770 attempts, .
Time elapsed: 886 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/393 29/32 DoubleExponent-PT-200-CTLFireability-05 680245 m, 15134 m/sec, 680246 t fired, .
66 EF FNDP 633/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 28327066 t fired, 2904200 attempts, .
Time elapsed: 891 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/393 32/32 DoubleExponent-PT-200-CTLFireability-05 755870 m, 15125 m/sec, 755871 t fired, .
66 EF FNDP 638/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 28556264 t fired, 2927561 attempts, .
Time elapsed: 896 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for DoubleExponent-PT-200-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 643/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 28786786 t fired, 2951246 attempts, .
Time elapsed: 901 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 DoubleExponent-PT-200-CTLFireability-03
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for DoubleExponent-PT-200-CTLFireability-03
lola: result : false
lola: markings : 25
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DoubleExponent-PT-200-CTLFireability-02
lola: time limit : 539 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/539 2/32 DoubleExponent-PT-200-CTLFireability-02 40409 m, 8081 m/sec, 80819 t fired, .
66 EF FNDP 648/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 29016670 t fired, 2974729 attempts, .
Time elapsed: 906 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/539 4/32 DoubleExponent-PT-200-CTLFireability-02 80871 m, 8092 m/sec, 161743 t fired, .
66 EF FNDP 653/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 29246485 t fired, 2998271 attempts, .
Time elapsed: 911 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/539 6/32 DoubleExponent-PT-200-CTLFireability-02 121352 m, 8096 m/sec, 242705 t fired, .
66 EF FNDP 658/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 29475893 t fired, 3021886 attempts, .
Time elapsed: 916 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/539 7/32 DoubleExponent-PT-200-CTLFireability-02 161858 m, 8101 m/sec, 323717 t fired, .
66 EF FNDP 663/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 29706019 t fired, 3045383 attempts, .
Time elapsed: 921 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/539 9/32 DoubleExponent-PT-200-CTLFireability-02 202285 m, 8085 m/sec, 404572 t fired, .
66 EF FNDP 668/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 29935457 t fired, 3068991 attempts, .
Time elapsed: 926 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/539 11/32 DoubleExponent-PT-200-CTLFireability-02 242710 m, 8085 m/sec, 485422 t fired, .
66 EF FNDP 673/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 30165145 t fired, 3092535 attempts, .
Time elapsed: 931 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/539 12/32 DoubleExponent-PT-200-CTLFireability-02 283168 m, 8091 m/sec, 566338 t fired, .
66 EF FNDP 678/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 30395048 t fired, 3116113 attempts, .
Time elapsed: 936 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/539 14/32 DoubleExponent-PT-200-CTLFireability-02 323620 m, 8090 m/sec, 647242 t fired, .
66 EF FNDP 683/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 30625312 t fired, 3139639 attempts, .
Time elapsed: 941 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/539 16/32 DoubleExponent-PT-200-CTLFireability-02 363987 m, 8073 m/sec, 727976 t fired, .
66 EF FNDP 688/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 30855116 t fired, 3163169 attempts, .
Time elapsed: 946 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/539 17/32 DoubleExponent-PT-200-CTLFireability-02 404482 m, 8099 m/sec, 808966 t fired, .
66 EF FNDP 693/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 31085210 t fired, 3186732 attempts, .
Time elapsed: 951 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/539 19/32 DoubleExponent-PT-200-CTLFireability-02 444914 m, 8086 m/sec, 889830 t fired, .
66 EF FNDP 698/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 31315535 t fired, 3210297 attempts, .
Time elapsed: 956 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 60/539 21/32 DoubleExponent-PT-200-CTLFireability-02 485398 m, 8096 m/sec, 970797 t fired, .
66 EF FNDP 703/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 31545803 t fired, 3233936 attempts, .
Time elapsed: 961 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 65/539 22/32 DoubleExponent-PT-200-CTLFireability-02 525865 m, 8093 m/sec, 1051731 t fired, .
66 EF FNDP 708/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 31775765 t fired, 3257511 attempts, .
Time elapsed: 966 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 70/539 24/32 DoubleExponent-PT-200-CTLFireability-02 566310 m, 8089 m/sec, 1132621 t fired, .
66 EF FNDP 713/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 32005890 t fired, 3281120 attempts, .
Time elapsed: 971 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 75/539 26/32 DoubleExponent-PT-200-CTLFireability-02 606794 m, 8096 m/sec, 1213590 t fired, .
66 EF FNDP 718/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 32236010 t fired, 3304701 attempts, .
Time elapsed: 976 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 80/539 28/32 DoubleExponent-PT-200-CTLFireability-02 647146 m, 8070 m/sec, 1294293 t fired, .
66 EF FNDP 723/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 32466210 t fired, 3328237 attempts, .
Time elapsed: 981 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 85/539 29/32 DoubleExponent-PT-200-CTLFireability-02 687543 m, 8079 m/sec, 1375087 t fired, .
66 EF FNDP 728/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 32696385 t fired, 3351809 attempts, .
Time elapsed: 986 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 90/539 31/32 DoubleExponent-PT-200-CTLFireability-02 728005 m, 8092 m/sec, 1456011 t fired, .
66 EF FNDP 733/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 32926661 t fired, 3375422 attempts, .
Time elapsed: 991 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for DoubleExponent-PT-200-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 1 1 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 738/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 33157288 t fired, 3398945 attempts, .
Time elapsed: 996 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 DoubleExponent-PT-200-CTLFireability-00
lola: time limit : 651 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DoubleExponent-PT-200-CTLFireability-00
lola: result : false
lola: markings : 25
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 69 (type EXCL) for 33 DoubleExponent-PT-200-CTLFireability-07
lola: time limit : 868 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 743/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 33386467 t fired, 3422561 attempts, .
69 EF EXCL 5/868 2/32 DoubleExponent-PT-200-CTLFireability-07 106421 m, 21284 m/sec, 106421 t fired, .
Time elapsed: 1001 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 748/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 33615986 t fired, 3446037 attempts, .
69 EF EXCL 10/868 4/32 DoubleExponent-PT-200-CTLFireability-07 213839 m, 21483 m/sec, 213839 t fired, .
Time elapsed: 1006 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 753/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 33845347 t fired, 3469470 attempts, .
69 EF EXCL 15/868 5/32 DoubleExponent-PT-200-CTLFireability-07 321278 m, 21487 m/sec, 321278 t fired, .
Time elapsed: 1011 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 758/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 34074591 t fired, 3492997 attempts, .
69 EF EXCL 20/868 7/32 DoubleExponent-PT-200-CTLFireability-07 428658 m, 21476 m/sec, 428657 t fired, .
Time elapsed: 1016 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 763/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 34304212 t fired, 3516509 attempts, .
69 EF EXCL 25/868 8/32 DoubleExponent-PT-200-CTLFireability-07 536001 m, 21468 m/sec, 536001 t fired, .
Time elapsed: 1021 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 768/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 34533566 t fired, 3540054 attempts, .
69 EF EXCL 30/868 10/32 DoubleExponent-PT-200-CTLFireability-07 643397 m, 21479 m/sec, 643397 t fired, .
Time elapsed: 1026 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 773/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 34763243 t fired, 3563627 attempts, .
69 EF EXCL 35/868 11/32 DoubleExponent-PT-200-CTLFireability-07 750711 m, 21462 m/sec, 750711 t fired, .
Time elapsed: 1031 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 778/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 34993183 t fired, 3587055 attempts, .
69 EF EXCL 40/868 13/32 DoubleExponent-PT-200-CTLFireability-07 858105 m, 21478 m/sec, 858105 t fired, .
Time elapsed: 1036 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 783/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 35222602 t fired, 3610724 attempts, .
69 EF EXCL 45/868 14/32 DoubleExponent-PT-200-CTLFireability-07 965597 m, 21498 m/sec, 965597 t fired, .
Time elapsed: 1041 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 788/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 35452533 t fired, 3634262 attempts, .
69 EF EXCL 50/868 16/32 DoubleExponent-PT-200-CTLFireability-07 1073017 m, 21484 m/sec, 1073017 t fired, .
Time elapsed: 1046 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 793/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 35682498 t fired, 3657786 attempts, .
69 EF EXCL 55/868 17/32 DoubleExponent-PT-200-CTLFireability-07 1180413 m, 21479 m/sec, 1180413 t fired, .
Time elapsed: 1051 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 798/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 35911929 t fired, 3681398 attempts, .
69 EF EXCL 60/868 19/32 DoubleExponent-PT-200-CTLFireability-07 1288055 m, 21528 m/sec, 1288054 t fired, .
Time elapsed: 1056 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 803/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 36141507 t fired, 3704981 attempts, .
69 EF EXCL 65/868 20/32 DoubleExponent-PT-200-CTLFireability-07 1396173 m, 21623 m/sec, 1396173 t fired, .
Time elapsed: 1061 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 808/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 36370999 t fired, 3728534 attempts, .
69 EF EXCL 70/868 22/32 DoubleExponent-PT-200-CTLFireability-07 1504407 m, 21646 m/sec, 1504407 t fired, .
Time elapsed: 1066 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 813/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 36600559 t fired, 3752077 attempts, .
69 EF EXCL 75/868 24/32 DoubleExponent-PT-200-CTLFireability-07 1612534 m, 21625 m/sec, 1612534 t fired, .
Time elapsed: 1071 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 818/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 36830175 t fired, 3775666 attempts, .
69 EF EXCL 80/868 25/32 DoubleExponent-PT-200-CTLFireability-07 1721071 m, 21707 m/sec, 1721071 t fired, .
Time elapsed: 1076 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 823/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 37059631 t fired, 3799233 attempts, .
69 EF EXCL 85/868 27/32 DoubleExponent-PT-200-CTLFireability-07 1829549 m, 21695 m/sec, 1829548 t fired, .
Time elapsed: 1081 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 828/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 37289218 t fired, 3822766 attempts, .
69 EF EXCL 90/868 28/32 DoubleExponent-PT-200-CTLFireability-07 1937982 m, 21686 m/sec, 1937981 t fired, .
Time elapsed: 1086 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 833/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 37518384 t fired, 3846334 attempts, .
69 EF EXCL 95/868 30/32 DoubleExponent-PT-200-CTLFireability-07 2046507 m, 21705 m/sec, 2046506 t fired, .
Time elapsed: 1091 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 2 0 3 0 0 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 838/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 37748146 t fired, 3869676 attempts, .
69 EF EXCL 100/868 32/32 DoubleExponent-PT-200-CTLFireability-07 2154756 m, 21649 m/sec, 2154756 t fired, .
Time elapsed: 1096 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 69 (type EXCL) for DoubleExponent-PT-200-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 843/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 37978279 t fired, 3893229 attempts, .
Time elapsed: 1101 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 62 (type EXCL) for 24 DoubleExponent-PT-200-CTLFireability-04
lola: time limit : 1249 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 5/1249 2/32 DoubleExponent-PT-200-CTLFireability-04 105918 m, 21183 m/sec, 124942 t fired, .
66 EF FNDP 848/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 38207470 t fired, 3916701 attempts, .
Time elapsed: 1106 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 10/1249 4/32 DoubleExponent-PT-200-CTLFireability-04 211844 m, 21185 m/sec, 249950 t fired, .
66 EF FNDP 853/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 38436438 t fired, 3940069 attempts, .
Time elapsed: 1111 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 15/1249 6/32 DoubleExponent-PT-200-CTLFireability-04 317837 m, 21198 m/sec, 375029 t fired, .
66 EF FNDP 858/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 38665191 t fired, 3963602 attempts, .
Time elapsed: 1116 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 20/1249 8/32 DoubleExponent-PT-200-CTLFireability-04 423853 m, 21203 m/sec, 500101 t fired, .
66 EF FNDP 863/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 38894007 t fired, 3987214 attempts, .
Time elapsed: 1121 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 25/1249 10/32 DoubleExponent-PT-200-CTLFireability-04 529809 m, 21191 m/sec, 625143 t fired, .
66 EF FNDP 868/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 39122946 t fired, 4010591 attempts, .
Time elapsed: 1126 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 30/1249 11/32 DoubleExponent-PT-200-CTLFireability-04 635779 m, 21194 m/sec, 750197 t fired, .
66 EF FNDP 873/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 39351687 t fired, 4034098 attempts, .
Time elapsed: 1131 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 35/1249 13/32 DoubleExponent-PT-200-CTLFireability-04 741836 m, 21211 m/sec, 875325 t fired, .
66 EF FNDP 878/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 39580619 t fired, 4057624 attempts, .
Time elapsed: 1136 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 40/1249 15/32 DoubleExponent-PT-200-CTLFireability-04 847698 m, 21172 m/sec, 1000249 t fired, .
66 EF FNDP 883/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 39809789 t fired, 4081092 attempts, .
Time elapsed: 1141 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 45/1249 17/32 DoubleExponent-PT-200-CTLFireability-04 953770 m, 21214 m/sec, 1125422 t fired, .
66 EF FNDP 888/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 40039044 t fired, 4104516 attempts, .
Time elapsed: 1146 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 50/1249 19/32 DoubleExponent-PT-200-CTLFireability-04 1059881 m, 21222 m/sec, 1250636 t fired, .
66 EF FNDP 893/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 40268281 t fired, 4128023 attempts, .
Time elapsed: 1151 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 55/1249 21/32 DoubleExponent-PT-200-CTLFireability-04 1165903 m, 21204 m/sec, 1375777 t fired, .
66 EF FNDP 898/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 40497601 t fired, 4151540 attempts, .
Time elapsed: 1156 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 60/1249 22/32 DoubleExponent-PT-200-CTLFireability-04 1272251 m, 21269 m/sec, 1501246 t fired, .
66 EF FNDP 903/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 40726876 t fired, 4175056 attempts, .
Time elapsed: 1161 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 65/1249 24/32 DoubleExponent-PT-200-CTLFireability-04 1378359 m, 21221 m/sec, 1626426 t fired, .
66 EF FNDP 908/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 40955911 t fired, 4198454 attempts, .
Time elapsed: 1166 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 70/1249 26/32 DoubleExponent-PT-200-CTLFireability-04 1483522 m, 21032 m/sec, 1750440 t fired, .
66 EF FNDP 913/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 41184549 t fired, 4221883 attempts, .
Time elapsed: 1171 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 75/1249 28/32 DoubleExponent-PT-200-CTLFireability-04 1588675 m, 21030 m/sec, 1874492 t fired, .
66 EF FNDP 918/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 41413872 t fired, 4245248 attempts, .
Time elapsed: 1176 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 80/1249 30/32 DoubleExponent-PT-200-CTLFireability-04 1693649 m, 20994 m/sec, 1998362 t fired, .
66 EF FNDP 923/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 41642792 t fired, 4268709 attempts, .
Time elapsed: 1181 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 LTL EXCL 85/1249 32/32 DoubleExponent-PT-200-CTLFireability-04 1798666 m, 21003 m/sec, 2122289 t fired, .
66 EF FNDP 928/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 41872242 t fired, 4292080 attempts, .
Time elapsed: 1186 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 62 (type EXCL) for DoubleExponent-PT-200-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 933/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 42102712 t fired, 4315739 attempts, .
Time elapsed: 1191 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 DoubleExponent-PT-200-CTLFireability-09
lola: time limit : 2409 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/2409 2/32 DoubleExponent-PT-200-CTLFireability-09 129170 m, 25834 m/sec, 129172 t fired, .
66 EF FNDP 938/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 42332663 t fired, 4339293 attempts, .
Time elapsed: 1196 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/2409 4/32 DoubleExponent-PT-200-CTLFireability-09 258590 m, 25884 m/sec, 258592 t fired, .
66 EF FNDP 943/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 42562385 t fired, 4362911 attempts, .
Time elapsed: 1201 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/2409 6/32 DoubleExponent-PT-200-CTLFireability-09 388147 m, 25911 m/sec, 388149 t fired, .
66 EF FNDP 948/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 42792880 t fired, 4386485 attempts, .
Time elapsed: 1206 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/2409 8/32 DoubleExponent-PT-200-CTLFireability-09 517679 m, 25906 m/sec, 517681 t fired, .
66 EF FNDP 953/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 43022951 t fired, 4410109 attempts, .
Time elapsed: 1211 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/2409 10/32 DoubleExponent-PT-200-CTLFireability-09 647234 m, 25911 m/sec, 647235 t fired, .
66 EF FNDP 958/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 43253266 t fired, 4433720 attempts, .
Time elapsed: 1216 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/2409 12/32 DoubleExponent-PT-200-CTLFireability-09 776733 m, 25899 m/sec, 776734 t fired, .
66 EF FNDP 963/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 43483761 t fired, 4457299 attempts, .
Time elapsed: 1221 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/2409 14/32 DoubleExponent-PT-200-CTLFireability-09 906285 m, 25910 m/sec, 906287 t fired, .
66 EF FNDP 968/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 43714130 t fired, 4480855 attempts, .
Time elapsed: 1226 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 40/2409 16/32 DoubleExponent-PT-200-CTLFireability-09 1035904 m, 25923 m/sec, 1035906 t fired, .
66 EF FNDP 973/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 43944751 t fired, 4504348 attempts, .
Time elapsed: 1231 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 45/2409 18/32 DoubleExponent-PT-200-CTLFireability-09 1165477 m, 25914 m/sec, 1165478 t fired, .
66 EF FNDP 978/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 44174872 t fired, 4528083 attempts, .
Time elapsed: 1236 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 50/2409 20/32 DoubleExponent-PT-200-CTLFireability-09 1295106 m, 25925 m/sec, 1295108 t fired, .
66 EF FNDP 983/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 44405057 t fired, 4551710 attempts, .
Time elapsed: 1241 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 55/2409 22/32 DoubleExponent-PT-200-CTLFireability-09 1424441 m, 25867 m/sec, 1424443 t fired, .
66 EF FNDP 988/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 44635624 t fired, 4575298 attempts, .
Time elapsed: 1246 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 60/2409 24/32 DoubleExponent-PT-200-CTLFireability-09 1553223 m, 25756 m/sec, 1553225 t fired, .
66 EF FNDP 993/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 44866006 t fired, 4598904 attempts, .
Time elapsed: 1251 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 65/2409 26/32 DoubleExponent-PT-200-CTLFireability-09 1681677 m, 25690 m/sec, 1681679 t fired, .
66 EF FNDP 998/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 45096376 t fired, 4622555 attempts, .
Time elapsed: 1256 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 70/2409 28/32 DoubleExponent-PT-200-CTLFireability-09 1810345 m, 25733 m/sec, 1810346 t fired, .
66 EF FNDP 1003/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 45326578 t fired, 4646197 attempts, .
Time elapsed: 1261 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 75/2409 30/32 DoubleExponent-PT-200-CTLFireability-09 1938972 m, 25725 m/sec, 1938974 t fired, .
66 EF FNDP 1008/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 45556976 t fired, 4669842 attempts, .
Time elapsed: 1266 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 80/2409 32/32 DoubleExponent-PT-200-CTLFireability-09 2067343 m, 25674 m/sec, 2067344 t fired, .
66 EF FNDP 1013/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 45787410 t fired, 4693508 attempts, .
Time elapsed: 1271 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for DoubleExponent-PT-200-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1018/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 46017793 t fired, 4717078 attempts, .
Time elapsed: 1276 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1023/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 46248328 t fired, 4740688 attempts, .
Time elapsed: 1281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1028/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 46478812 t fired, 4764279 attempts, .
Time elapsed: 1286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1033/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 46709484 t fired, 4787879 attempts, .
Time elapsed: 1291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1038/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 46940401 t fired, 4811559 attempts, .
Time elapsed: 1296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1043/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 47171429 t fired, 4835259 attempts, .
Time elapsed: 1301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1048/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 47402142 t fired, 4858817 attempts, .
Time elapsed: 1306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1053/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 47632632 t fired, 4882301 attempts, .
Time elapsed: 1311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1058/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 47863452 t fired, 4905926 attempts, .
Time elapsed: 1316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1063/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 48094517 t fired, 4929579 attempts, .
Time elapsed: 1321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1068/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 48322787 t fired, 4952875 attempts, .
Time elapsed: 1326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1073/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 48555867 t fired, 4976742 attempts, .
Time elapsed: 1331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1078/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 48788900 t fired, 5000604 attempts, .
Time elapsed: 1336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1083/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 49021305 t fired, 5024608 attempts, .
Time elapsed: 1341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1088/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 49254241 t fired, 5048577 attempts, .
Time elapsed: 1346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1093/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 49487424 t fired, 5072467 attempts, .
Time elapsed: 1351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1098/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 49720110 t fired, 5096316 attempts, .
Time elapsed: 1356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1103/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 49953138 t fired, 5120277 attempts, .
Time elapsed: 1361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1108/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 50186408 t fired, 5144119 attempts, .
Time elapsed: 1366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1113/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 50419067 t fired, 5167988 attempts, .
Time elapsed: 1371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1118/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 50651768 t fired, 5191945 attempts, .
Time elapsed: 1376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1123/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 50884382 t fired, 5215967 attempts, .
Time elapsed: 1381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1128/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 51117378 t fired, 5239742 attempts, .
Time elapsed: 1386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1133/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 51350482 t fired, 5263520 attempts, .
Time elapsed: 1391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1138/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 51582715 t fired, 5287487 attempts, .
Time elapsed: 1396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1143/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 51814916 t fired, 5311464 attempts, .
Time elapsed: 1401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1148/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 52047711 t fired, 5335386 attempts, .
Time elapsed: 1406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1153/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 52281029 t fired, 5359244 attempts, .
Time elapsed: 1411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1158/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 52514492 t fired, 5383090 attempts, .
Time elapsed: 1416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1163/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 52748194 t fired, 5406908 attempts, .
Time elapsed: 1421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1168/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 52980843 t fired, 5430751 attempts, .
Time elapsed: 1426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1173/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 53213576 t fired, 5454586 attempts, .
Time elapsed: 1431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1178/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 53446632 t fired, 5478458 attempts, .
Time elapsed: 1436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1183/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 53679625 t fired, 5502450 attempts, .
Time elapsed: 1441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1188/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 53912737 t fired, 5526249 attempts, .
Time elapsed: 1446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1193/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 54146128 t fired, 5550121 attempts, .
Time elapsed: 1451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1198/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 54378892 t fired, 5573953 attempts, .
Time elapsed: 1456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1203/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 54611326 t fired, 5597912 attempts, .
Time elapsed: 1461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1208/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 54843911 t fired, 5621779 attempts, .
Time elapsed: 1466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1213/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 55076728 t fired, 5645606 attempts, .
Time elapsed: 1471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1218/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 55309560 t fired, 5669459 attempts, .
Time elapsed: 1476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1223/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 55542669 t fired, 5693288 attempts, .
Time elapsed: 1481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1228/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 55775506 t fired, 5717157 attempts, .
Time elapsed: 1486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1233/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 56008211 t fired, 5741106 attempts, .
Time elapsed: 1491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1238/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 56240951 t fired, 5764969 attempts, .
Time elapsed: 1496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1243/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 56473931 t fired, 5788753 attempts, .
Time elapsed: 1501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1248/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 56706806 t fired, 5812563 attempts, .
Time elapsed: 1506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1253/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 56939521 t fired, 5836527 attempts, .
Time elapsed: 1511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1258/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 57172633 t fired, 5860483 attempts, .
Time elapsed: 1516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1263/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 57405707 t fired, 5884318 attempts, .
Time elapsed: 1521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1268/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 57638700 t fired, 5908290 attempts, .
Time elapsed: 1526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1273/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 57871937 t fired, 5932206 attempts, .
Time elapsed: 1531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1278/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 58105049 t fired, 5956156 attempts, .
Time elapsed: 1536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1283/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 58337868 t fired, 5980004 attempts, .
Time elapsed: 1541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1288/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 58571208 t fired, 6003895 attempts, .
Time elapsed: 1546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1293/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 58804413 t fired, 6027905 attempts, .
Time elapsed: 1551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1298/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 59037756 t fired, 6051760 attempts, .
Time elapsed: 1556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1303/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 59271284 t fired, 6075629 attempts, .
Time elapsed: 1561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1308/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 59504354 t fired, 6099530 attempts, .
Time elapsed: 1566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1313/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 59737332 t fired, 6123370 attempts, .
Time elapsed: 1571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1318/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 59970729 t fired, 6147199 attempts, .
Time elapsed: 1576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1323/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 60203639 t fired, 6171031 attempts, .
Time elapsed: 1581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1328/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 60437126 t fired, 6194897 attempts, .
Time elapsed: 1586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1333/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 60669875 t fired, 6218800 attempts, .
Time elapsed: 1591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1338/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 60902822 t fired, 6242723 attempts, .
Time elapsed: 1596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1343/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 61135679 t fired, 6266656 attempts, .
Time elapsed: 1601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1348/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 61368586 t fired, 6290510 attempts, .
Time elapsed: 1606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1353/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 61601820 t fired, 6314437 attempts, .
Time elapsed: 1611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1358/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 61834878 t fired, 6338336 attempts, .
Time elapsed: 1616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1363/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 62068201 t fired, 6362223 attempts, .
Time elapsed: 1621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1368/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 62300904 t fired, 6386069 attempts, .
Time elapsed: 1626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1373/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 62533752 t fired, 6409921 attempts, .
Time elapsed: 1631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1378/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 62766776 t fired, 6433736 attempts, .
Time elapsed: 1636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1383/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 63000075 t fired, 6457719 attempts, .
Time elapsed: 1641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1388/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 63232963 t fired, 6481587 attempts, .
Time elapsed: 1646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1393/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 63465933 t fired, 6505513 attempts, .
Time elapsed: 1651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1398/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 63699357 t fired, 6529351 attempts, .
Time elapsed: 1656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1403/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 63932024 t fired, 6553203 attempts, .
Time elapsed: 1661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1408/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 64165161 t fired, 6576982 attempts, .
Time elapsed: 1666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1413/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 64398015 t fired, 6600856 attempts, .
Time elapsed: 1671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1418/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 64630851 t fired, 6624753 attempts, .
Time elapsed: 1676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1423/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 64864245 t fired, 6648695 attempts, .
Time elapsed: 1681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1428/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 65097928 t fired, 6672505 attempts, .
Time elapsed: 1686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1433/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 65330656 t fired, 6696350 attempts, .
Time elapsed: 1691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1438/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 65562890 t fired, 6720272 attempts, .
Time elapsed: 1696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1443/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 65795824 t fired, 6744094 attempts, .
Time elapsed: 1701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1448/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 66028928 t fired, 6768014 attempts, .
Time elapsed: 1706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1453/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 66261823 t fired, 6791867 attempts, .
Time elapsed: 1711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1458/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 66494831 t fired, 6815670 attempts, .
Time elapsed: 1716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1463/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 66727425 t fired, 6839568 attempts, .
Time elapsed: 1721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1468/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 66960306 t fired, 6863413 attempts, .
Time elapsed: 1726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1473/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 67193451 t fired, 6887185 attempts, .
Time elapsed: 1731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1478/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 67426180 t fired, 6911147 attempts, .
Time elapsed: 1736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1483/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 67659240 t fired, 6934953 attempts, .
Time elapsed: 1741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1488/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 67892145 t fired, 6958829 attempts, .
Time elapsed: 1746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1493/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 68125249 t fired, 6982660 attempts, .
Time elapsed: 1751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1498/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 68357354 t fired, 7006414 attempts, .
Time elapsed: 1756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1503/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 68590347 t fired, 7030307 attempts, .
Time elapsed: 1761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1508/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 68823180 t fired, 7054263 attempts, .
Time elapsed: 1766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1513/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 69055893 t fired, 7078172 attempts, .
Time elapsed: 1771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1518/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 69288757 t fired, 7102155 attempts, .
Time elapsed: 1776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1523/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 69521796 t fired, 7125982 attempts, .
Time elapsed: 1781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1528/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 69754418 t fired, 7149843 attempts, .
Time elapsed: 1786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1533/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 69987376 t fired, 7173776 attempts, .
Time elapsed: 1791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1538/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 70220695 t fired, 7197607 attempts, .
Time elapsed: 1796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1543/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 70453324 t fired, 7221523 attempts, .
Time elapsed: 1801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1548/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 70686168 t fired, 7245324 attempts, .
Time elapsed: 1806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1553/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 70919318 t fired, 7269232 attempts, .
Time elapsed: 1811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1558/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 71152038 t fired, 7293121 attempts, .
Time elapsed: 1816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1563/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 71384789 t fired, 7317046 attempts, .
Time elapsed: 1821 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1568/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 71618235 t fired, 7340871 attempts, .
Time elapsed: 1826 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1573/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 71850954 t fired, 7364906 attempts, .
Time elapsed: 1831 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1578/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 72083927 t fired, 7388816 attempts, .
Time elapsed: 1836 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1583/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 72316646 t fired, 7412660 attempts, .
Time elapsed: 1841 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1588/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 72549630 t fired, 7436529 attempts, .
Time elapsed: 1846 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1593/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 72782599 t fired, 7460433 attempts, .
Time elapsed: 1851 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1598/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 73015561 t fired, 7484291 attempts, .
Time elapsed: 1856 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1603/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 73248708 t fired, 7508229 attempts, .
Time elapsed: 1861 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1608/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 73481983 t fired, 7532083 attempts, .
Time elapsed: 1866 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1613/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 73714688 t fired, 7555986 attempts, .
Time elapsed: 1871 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1618/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 73947325 t fired, 7579921 attempts, .
Time elapsed: 1876 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1623/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 74180186 t fired, 7603859 attempts, .
Time elapsed: 1881 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1628/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 74413028 t fired, 7627814 attempts, .
Time elapsed: 1886 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1633/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 74646939 t fired, 7651704 attempts, .
Time elapsed: 1891 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1638/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 74880627 t fired, 7675598 attempts, .
Time elapsed: 1896 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1643/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 75114367 t fired, 7699514 attempts, .
Time elapsed: 1901 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1648/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 75347752 t fired, 7723394 attempts, .
Time elapsed: 1906 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1653/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 75581527 t fired, 7747318 attempts, .
Time elapsed: 1911 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1658/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 75814885 t fired, 7771271 attempts, .
Time elapsed: 1916 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1663/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 76048354 t fired, 7795246 attempts, .
Time elapsed: 1921 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1668/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 76281808 t fired, 7819106 attempts, .
Time elapsed: 1926 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1673/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 76515004 t fired, 7843112 attempts, .
Time elapsed: 1931 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1678/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 76747781 t fired, 7867112 attempts, .
Time elapsed: 1936 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1683/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 76981013 t fired, 7891141 attempts, .
Time elapsed: 1941 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1688/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 77214697 t fired, 7915020 attempts, .
Time elapsed: 1946 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1693/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 77448228 t fired, 7938928 attempts, .
Time elapsed: 1951 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1698/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 77681667 t fired, 7962913 attempts, .
Time elapsed: 1956 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1703/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 77914952 t fired, 7986780 attempts, .
Time elapsed: 1961 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1708/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 78148652 t fired, 8010623 attempts, .
Time elapsed: 1966 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1713/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 78381522 t fired, 8034528 attempts, .
Time elapsed: 1971 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1718/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 78615101 t fired, 8058404 attempts, .
Time elapsed: 1976 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1723/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 78848268 t fired, 8082368 attempts, .
Time elapsed: 1981 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1728/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 79081183 t fired, 8106392 attempts, .
Time elapsed: 1986 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1733/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 79314591 t fired, 8130402 attempts, .
Time elapsed: 1991 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1738/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 79547867 t fired, 8154362 attempts, .
Time elapsed: 1996 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1743/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 79781722 t fired, 8178290 attempts, .
Time elapsed: 2001 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1748/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 80015160 t fired, 8202145 attempts, .
Time elapsed: 2006 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1753/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 80248802 t fired, 8226019 attempts, .
Time elapsed: 2011 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1758/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 80482154 t fired, 8249896 attempts, .
Time elapsed: 2016 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1763/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 80715303 t fired, 8273904 attempts, .
Time elapsed: 2021 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1768/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 80948855 t fired, 8297600 attempts, .
Time elapsed: 2026 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1773/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 81182257 t fired, 8321557 attempts, .
Time elapsed: 2031 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1778/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 81415573 t fired, 8345484 attempts, .
Time elapsed: 2036 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1783/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 81648915 t fired, 8369391 attempts, .
Time elapsed: 2041 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1788/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 81882331 t fired, 8393341 attempts, .
Time elapsed: 2046 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1793/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 82115551 t fired, 8417362 attempts, .
Time elapsed: 2051 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1798/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 82348933 t fired, 8441441 attempts, .
Time elapsed: 2056 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1803/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 82582073 t fired, 8465480 attempts, .
Time elapsed: 2061 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DoubleExponent-PT-200-CTLFireability-01: DISJ 0 0 0 0 7 0 1 3
DoubleExponent-PT-200-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-07: EF 0 0 1 0 3 0 1 0
DoubleExponent-PT-200-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DoubleExponent-PT-200-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 EF FNDP 1808/3342 0/5 DoubleExponent-PT-200-CTLFireability-07 82815468 t fired, 8489429 attempts, .
Time elapsed: 2066 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DoubleExponent-PT-200-CTLFireability-00: CTL false CTL model checker
DoubleExponent-PT-200-CTLFireability-03: CTL false CTL model checker
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DoubleExponent-PT-200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r134-smll-167819412800498"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-200.tgz
mv DoubleExponent-PT-200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;