Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r126-tall-167814503700404.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool gold2022
Input is DLCflexbar-PT-4a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r126-tall-167814503700404
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 7.3K Feb 25 16:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 16:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 15:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 1.7M Mar 5 18:22 model.pnml
-rw-r--r-- 1 mcc users 8.1K Feb 25 16:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 16:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 25 16:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 16:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678250313448

gold2022
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> gold2022 --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a
MF=/home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
CPN OverApproximation is only usable on colored models
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

Time left: 3589

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@233.41,6798816@@@


Time left: 3287
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.072638 on verification
@@@0.25,65228@@@


Query index 0 was solved
Query is NOT satisfied.

Spent 0.081334 on verification
@@@0.24,65212@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 2 -n
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 2 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3287
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.043894 on verification
@@@0.15,65396@@@


Query index 0 was solved
Query is satisfied.

Spent 0.063462 on verification
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 3 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3287
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.049073 on verification
@@@0.14,65604@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 4 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3286
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.040894 on verification
@@@0.15,65536@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 5 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3286
------------------- QUERY 6 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.046446 on verification
@@@0.16,65396@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 6 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3285
------------------- QUERY 7 ----------------------
No solution found



Time left: 2983
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.045135 on verification
@@@0.14,65464@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 8 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2982
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.057101 on verification
@@@0.15,65428@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 9 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2982
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.045073 on verification
@@@0.15,65496@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 10 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2982
------------------- QUERY 11 ----------------------
No solution found



Time left: 2679
------------------- QUERY 12 ----------------------
No solution found
Command terminated by signal 9
@@@237.69,7997812@@@


Time left: 2378
------------------- QUERY 13 ----------------------
No solution found
Command terminated by signal 9
@@@257.90,6953996@@@


Time left: 2075
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.131564 on verification
@@@0.35,65340@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 14 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2075
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.052986 on verification
@@@0.14,65268@@@


Query index 0 was solved
Query is NOT satisfied.

Spent 0.052595 on verification
@@@0.14,65428@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 15 -n
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.VP3dpkTdnG /home/mcc/BenchKit/bin/tmp/tmp.HmwjxLZ39a --binary-query-io 1 -x 15 -n

FORMULA DLCflexbar-PT-4a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2074
------------------- QUERY 16 ----------------------
No solution found
Command terminated by signal 9
@@@263.92,7439948@@@


Time left: 1772
---------------------------------------------------
Step 2: Sequential processing
---------------------------------------------------
Remaining 6 queries are verified sequentially.
Each query is verified for a dynamic timeout (at least 598 seconds)
Time left: 1772
------------------- QUERY 1 ----------------------
Running query 1 for 598 seconds. Remaining: 6 queries and 1772 seconds
No solution found
Command terminated by signal 9
@@@309.69,9193828@@@


Time left: 1172
------------------- QUERY 7 ----------------------
Running query 7 for 598 seconds. Remaining: 5 queries and 1172 seconds
No solution found
Command terminated by signal 9
@@@424.45,8381872@@@


Time left: 570
------------------- QUERY 11 ----------------------
Time left: 570
---------------------------------------------------
Step 4: Random Parallel processing
---------------------------------------------------
Doing random parallel verification of individual queries (6 in total)
Each query is verified by 4 parallel strategies for 95 seconds
------------------- QUERY 1 ----------------------
No solution found



Time left: 472
------------------- QUERY 7 ----------------------
No solution found



Time left: 374
------------------- QUERY 11 ----------------------
No solution found



Time left: 277
------------------- QUERY 12 ----------------------
No solution found



Time left: 180
------------------- QUERY 13 ----------------------
No solution found



Time left: 82
------------------- QUERY 16 ----------------------
No solution found



Time left: -4
Out of time, terminating!
terminated-with-cleanup

BK_STOP 1678253908023

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="gold2022"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool gold2022"
echo " Input is DLCflexbar-PT-4a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r126-tall-167814503700404"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;