Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814479101066.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DatabaseWithMutex-PT-04, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814479101066
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 21K Feb 25 13:17 CTLCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 25 13:17 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 25 13:16 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 13:16 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K Feb 25 15:56 LTLCardinality.txt
-rw-r--r-- 1 mcc users 41K Feb 25 15:56 LTLCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Feb 25 15:56 LTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 15:56 LTLFireability.xml
-rw-r--r-- 1 mcc users 53K Feb 25 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 295K Feb 25 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 46K Feb 25 13:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 248K Feb 25 13:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 15:56 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.3K Feb 25 15:56 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 61K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-00
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-01
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-02
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-03
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-04
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-05
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-06
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-07
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-08
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-09
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-10
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-11
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-12
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-13
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-14
FORMULA_NAME DatabaseWithMutex-PT-04-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678314441991

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DatabaseWithMutex-PT-04
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 22:27:23] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 22:27:23] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 22:27:23] [INFO ] Load time of PNML (sax parser for PT used): 38 ms
[2023-03-08 22:27:23] [INFO ] Transformed 140 places.
[2023-03-08 22:27:23] [INFO ] Transformed 128 transitions.
[2023-03-08 22:27:23] [INFO ] Parsed PT model containing 140 places and 128 transitions and 416 arcs in 97 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
[2023-03-08 22:27:23] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-08 22:27:23] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-08 22:27:23] [INFO ] Reduced 12 identical enabling conditions.
[2023-03-08 22:27:23] [INFO ] Reduced 12 identical enabling conditions.
Support contains 140 out of 140 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 10 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
// Phase 1: matrix 128 rows 140 cols
[2023-03-08 22:27:23] [INFO ] Computed 28 place invariants in 20 ms
[2023-03-08 22:27:24] [INFO ] Implicit Places using invariants in 409 ms returned []
[2023-03-08 22:27:24] [INFO ] Invariant cache hit.
[2023-03-08 22:27:24] [INFO ] Implicit Places using invariants and state equation in 92 ms returned []
Implicit Place search using SMT with State Equation took 524 ms to find 0 implicit places.
[2023-03-08 22:27:24] [INFO ] Invariant cache hit.
[2023-03-08 22:27:24] [INFO ] Dead Transitions using invariants and state equation in 78 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 614 ms. Remains : 140/140 places, 128/128 transitions.
Support contains 140 out of 140 places after structural reductions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 30 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 16 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Finished random walk after 8432 steps, including 2 resets, run visited all 39 properties in 79 ms. (steps per millisecond=106 )
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 12 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 16 place count 140 transition count 112
Reduce places removed 20 places and 0 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 1 with 52 rules applied. Total rules applied 68 place count 120 transition count 80
Reduce places removed 32 places and 0 transitions.
Iterating post reduction 2 with 32 rules applied. Total rules applied 100 place count 88 transition count 80
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 16 Pre rules applied. Total rules applied 100 place count 88 transition count 64
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 3 with 32 rules applied. Total rules applied 132 place count 72 transition count 64
Applied a total of 132 rules in 16 ms. Remains 72 /140 variables (removed 68) and now considering 64/128 (removed 64) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 72/140 places, 64/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 8 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 3 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 8 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 8 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 3 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 7 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 3 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 11 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 16 place count 140 transition count 112
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 32 place count 124 transition count 112
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 16 Pre rules applied. Total rules applied 32 place count 124 transition count 96
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 2 with 32 rules applied. Total rules applied 64 place count 108 transition count 96
Applied a total of 64 rules in 10 ms. Remains 108 /140 variables (removed 32) and now considering 96/128 (removed 32) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 108/140 places, 96/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 96 transitions.
Finished random walk after 7 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=7 )
FORMULA DatabaseWithMutex-PT-04-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 140 transition count 96
Reduce places removed 36 places and 0 transitions.
Drop transitions removed 32 transitions
Trivial Post-agglo rules discarded 32 transitions
Performed 32 trivial Post agglomeration. Transition count delta: 32
Iterating post reduction 1 with 68 rules applied. Total rules applied 100 place count 104 transition count 64
Reduce places removed 32 places and 0 transitions.
Iterating post reduction 2 with 32 rules applied. Total rules applied 132 place count 72 transition count 64
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 16 Pre rules applied. Total rules applied 132 place count 72 transition count 48
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 3 with 32 rules applied. Total rules applied 164 place count 56 transition count 48
Applied a total of 164 rules in 7 ms. Remains 56 /140 variables (removed 84) and now considering 48/128 (removed 80) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 56/140 places, 48/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 2 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 2 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 16 place count 140 transition count 112
Reduce places removed 20 places and 0 transitions.
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Iterating post reduction 1 with 36 rules applied. Total rules applied 52 place count 120 transition count 96
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 2 with 16 rules applied. Total rules applied 68 place count 104 transition count 96
Applied a total of 68 rules in 7 ms. Remains 104 /140 variables (removed 36) and now considering 96/128 (removed 32) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 104/140 places, 96/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 4 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 22:27:24] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:24] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 3 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Drop transitions removed 31 transitions
Trivial Post-agglo rules discarded 31 transitions
Performed 31 trivial Post agglomeration. Transition count delta: 31
Iterating post reduction 0 with 31 rules applied. Total rules applied 31 place count 140 transition count 97
Reduce places removed 35 places and 0 transitions.
Drop transitions removed 29 transitions
Trivial Post-agglo rules discarded 29 transitions
Performed 29 trivial Post agglomeration. Transition count delta: 29
Iterating post reduction 1 with 64 rules applied. Total rules applied 95 place count 105 transition count 68
Reduce places removed 29 places and 0 transitions.
Iterating post reduction 2 with 29 rules applied. Total rules applied 124 place count 76 transition count 68
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 16 Pre rules applied. Total rules applied 124 place count 76 transition count 52
Deduced a syphon composed of 16 places in 0 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 3 with 32 rules applied. Total rules applied 156 place count 60 transition count 52
Applied a total of 156 rules in 7 ms. Remains 60 /140 variables (removed 80) and now considering 52/128 (removed 76) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 60/140 places, 52/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 2 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 2 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 52 transitions.
Finished random walk after 15 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=15 )
FORMULA DatabaseWithMutex-PT-04-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 5 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 128 transitions.
Starting structural reductions in LTL mode, iteration 0 : 140/140 places, 128/128 transitions.
Applied a total of 0 rules in 2 ms. Remains 140 /140 variables (removed 0) and now considering 128/128 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 140/140 places, 128/128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 4 ms
[2023-03-08 22:27:25] [INFO ] Input system was already deterministic with 128 transitions.
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:25] [INFO ] Flatten gal took : 6 ms
[2023-03-08 22:27:25] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 22:27:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 140 places, 128 transitions and 416 arcs took 1 ms.
Total runtime 1778 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DatabaseWithMutex-PT-04
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA DatabaseWithMutex-PT-04-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DatabaseWithMutex-PT-04-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678314806885

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

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4 CTL EXCL 10/225 12/32 DatabaseWithMutex-PT-04-CTLFireability-01 2540972 m, 222572 m/sec, 6758518 t fired, .

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4 CTL EXCL 15/225 16/32 DatabaseWithMutex-PT-04-CTLFireability-01 3442644 m, 180334 m/sec, 10043707 t fired, .

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4 CTL EXCL 20/225 19/32 DatabaseWithMutex-PT-04-CTLFireability-01 4224174 m, 156306 m/sec, 13389028 t fired, .

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4 CTL EXCL 25/225 23/32 DatabaseWithMutex-PT-04-CTLFireability-01 5057298 m, 166624 m/sec, 16710730 t fired, .

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4 CTL EXCL 30/225 26/32 DatabaseWithMutex-PT-04-CTLFireability-01 5802525 m, 149045 m/sec, 20093154 t fired, .

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lola: fired transitions : 174
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DatabaseWithMutex-PT-04-CTLFireability-02
lola: time limit : 810 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for DatabaseWithMutex-PT-04-CTLFireability-02
lola: result : false
lola: markings : 39
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 15 DatabaseWithMutex-PT-04-CTLFireability-06
lola: time limit : 1080 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for DatabaseWithMutex-PT-04-CTLFireability-06
lola: result : true
lola: markings : 4557
lola: fired transitions : 16020
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DatabaseWithMutex-PT-04-CTLFireability-00
lola: time limit : 1620 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DatabaseWithMutex-PT-04-CTLFireability-00
lola: result : true
lola: markings : 7
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DatabaseWithMutex-PT-04-CTLFireability-07
lola: time limit : 3240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for DatabaseWithMutex-PT-04-CTLFireability-07
lola: result : false
lola: markings : 5581
lola: fired transitions : 10908
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DatabaseWithMutex-PT-04-CTLFireability-00: EGEF true CTL model checker
DatabaseWithMutex-PT-04-CTLFireability-01: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-02: CTL false CTL model checker
DatabaseWithMutex-PT-04-CTLFireability-03: CTL false CTL model checker
DatabaseWithMutex-PT-04-CTLFireability-05: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-06: EFAG false tscc_search
DatabaseWithMutex-PT-04-CTLFireability-07: CTL false CTL model checker
DatabaseWithMutex-PT-04-CTLFireability-08: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-09: CTL false CTL model checker
DatabaseWithMutex-PT-04-CTLFireability-10: DISJ unknown DISJ
DatabaseWithMutex-PT-04-CTLFireability-11: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-13: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-14: CTL unknown AGGR
DatabaseWithMutex-PT-04-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DatabaseWithMutex-PT-04"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DatabaseWithMutex-PT-04, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814479101066"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DatabaseWithMutex-PT-04.tgz
mv DatabaseWithMutex-PT-04 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;