Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478900906.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DNAwalker-PT-05track28LR, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478900906
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 6.8K Feb 25 13:00 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 13:00 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 12:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 12:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:55 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:55 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:55 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:55 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 13:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 125K Feb 25 13:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Feb 25 13:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 13:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:55 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:55 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 12 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 108K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-00
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-01
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-02
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-03
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-04
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-05
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-06
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-07
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-08
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-09
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-10
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-11
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-12
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-13
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-14
FORMULA_NAME DNAwalker-PT-05track28LR-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678288621039

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DNAwalker-PT-05track28LR
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 15:17:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 15:17:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 15:17:02] [INFO ] Load time of PNML (sax parser for PT used): 49 ms
[2023-03-08 15:17:02] [INFO ] Transformed 34 places.
[2023-03-08 15:17:02] [INFO ] Transformed 250 transitions.
[2023-03-08 15:17:02] [INFO ] Parsed PT model containing 34 places and 250 transitions and 728 arcs in 108 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Support contains 29 out of 34 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 12 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:02] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
// Phase 1: matrix 247 rows 34 cols
[2023-03-08 15:17:02] [INFO ] Computed 0 place invariants in 15 ms
[2023-03-08 15:17:02] [INFO ] Dead Transitions using invariants and state equation in 359 ms found 0 transitions.
[2023-03-08 15:17:02] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:02] [INFO ] Invariant cache hit.
[2023-03-08 15:17:03] [INFO ] Implicit Places using invariants in 33 ms returned []
[2023-03-08 15:17:03] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:03] [INFO ] Invariant cache hit.
[2023-03-08 15:17:03] [INFO ] State equation strengthened by 54 read => feed constraints.
[2023-03-08 15:17:03] [INFO ] Implicit Places using invariants and state equation in 108 ms returned []
Implicit Place search using SMT with State Equation took 142 ms to find 0 implicit places.
[2023-03-08 15:17:03] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:03] [INFO ] Invariant cache hit.
[2023-03-08 15:17:03] [INFO ] Dead Transitions using invariants and state equation in 100 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 637 ms. Remains : 34/34 places, 250/250 transitions.
Support contains 29 out of 34 places after structural reductions.
[2023-03-08 15:17:03] [INFO ] Flatten gal took : 34 ms
[2023-03-08 15:17:03] [INFO ] Flatten gal took : 15 ms
[2023-03-08 15:17:03] [INFO ] Input system was already deterministic with 250 transitions.
Incomplete random walk after 10000 steps, including 642 resets, run finished after 437 ms. (steps per millisecond=22 ) properties (out of 52) seen :46
Incomplete Best-First random walk after 10001 steps, including 58 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 62 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 56 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 67 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 60 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 63 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-08 15:17:04] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:04] [INFO ] Invariant cache hit.
[2023-03-08 15:17:04] [INFO ] After 162ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-08 15:17:14] [INFO ] After 10369ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 6 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 8 out of 34 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 34/34 places, 250/250 transitions.
Graph (complete) has 240 edges and 34 vertex of which 33 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.3 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 0 with 16 rules applied. Total rules applied 17 place count 33 transition count 233
Reduce places removed 6 places and 6 transitions.
Iterating global reduction 1 with 6 rules applied. Total rules applied 23 place count 27 transition count 227
Applied a total of 23 rules in 25 ms. Remains 27 /34 variables (removed 7) and now considering 227/250 (removed 23) transitions.
// Phase 1: matrix 227 rows 27 cols
[2023-03-08 15:17:14] [INFO ] Computed 0 place invariants in 3 ms
[2023-03-08 15:17:14] [INFO ] Dead Transitions using invariants and state equation in 96 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 121 ms. Remains : 27/34 places, 227/250 transitions.
Incomplete random walk after 10000 steps, including 879 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 110 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1754379 steps, run timeout after 3001 ms. (steps per millisecond=584 ) properties seen :{}
Probabilistic random walk after 1754379 steps, saw 419876 distinct states, run finished after 3002 ms. (steps per millisecond=584 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-08 15:17:17] [INFO ] Invariant cache hit.
[2023-03-08 15:17:17] [INFO ] After 17ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 15:17:26] [INFO ] After 9062ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 8 out of 27 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 27/27 places, 227/227 transitions.
Applied a total of 0 rules in 4 ms. Remains 27 /27 variables (removed 0) and now considering 227/227 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 4 ms. Remains : 27/27 places, 227/227 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 27/27 places, 227/227 transitions.
Applied a total of 0 rules in 5 ms. Remains 27 /27 variables (removed 0) and now considering 227/227 (removed 0) transitions.
[2023-03-08 15:17:26] [INFO ] Invariant cache hit.
[2023-03-08 15:17:26] [INFO ] Implicit Places using invariants in 34 ms returned []
[2023-03-08 15:17:26] [INFO ] Invariant cache hit.
[2023-03-08 15:17:27] [INFO ] Implicit Places using invariants and state equation in 133 ms returned [16, 19, 26]
Discarding 3 places :
Drop transitions removed 14 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 15 transitions.
Implicit Place search using SMT with State Equation took 173 ms to find 3 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 24/27 places, 212/227 transitions.
Applied a total of 0 rules in 7 ms. Remains 24 /24 variables (removed 0) and now considering 212/212 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 185 ms. Remains : 24/27 places, 212/227 transitions.
Incomplete random walk after 10000 steps, including 583 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 100 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1980021 steps, run timeout after 3001 ms. (steps per millisecond=659 ) properties seen :{}
Probabilistic random walk after 1980021 steps, saw 471364 distinct states, run finished after 3001 ms. (steps per millisecond=659 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 212 rows 24 cols
[2023-03-08 15:17:30] [INFO ] Computed 0 place invariants in 3 ms
[2023-03-08 15:17:30] [INFO ] After 21ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 15:17:39] [INFO ] After 9062ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 0 ms.
Support contains 8 out of 24 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 24/24 places, 212/212 transitions.
Applied a total of 0 rules in 4 ms. Remains 24 /24 variables (removed 0) and now considering 212/212 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 4 ms. Remains : 24/24 places, 212/212 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 24/24 places, 212/212 transitions.
Applied a total of 0 rules in 3 ms. Remains 24 /24 variables (removed 0) and now considering 212/212 (removed 0) transitions.
[2023-03-08 15:17:39] [INFO ] Invariant cache hit.
[2023-03-08 15:17:39] [INFO ] Implicit Places using invariants in 41 ms returned []
[2023-03-08 15:17:39] [INFO ] Invariant cache hit.
[2023-03-08 15:17:39] [INFO ] Implicit Places using invariants and state equation in 115 ms returned []
Implicit Place search using SMT with State Equation took 159 ms to find 0 implicit places.
[2023-03-08 15:17:39] [INFO ] Redundant transitions in 11 ms returned []
[2023-03-08 15:17:39] [INFO ] Invariant cache hit.
[2023-03-08 15:17:39] [INFO ] Dead Transitions using invariants and state equation in 72 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 250 ms. Remains : 24/24 places, 212/212 transitions.
Applied a total of 0 rules in 4 ms. Remains 24 /24 variables (removed 0) and now considering 212/212 (removed 0) transitions.
Running SMT prover for 1 properties.
[2023-03-08 15:17:39] [INFO ] Invariant cache hit.
[2023-03-08 15:17:39] [INFO ] After 18ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 15:17:48] [INFO ] After 9053ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
FORMULA DNAwalker-PT-05track28LR-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 15:17:48] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 15 ms
FORMULA DNAwalker-PT-05track28LR-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 10 ms
[2023-03-08 15:17:48] [INFO ] Input system was already deterministic with 250 transitions.
Computed a total of 34 stabilizing places and 246 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:48] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
// Phase 1: matrix 247 rows 34 cols
[2023-03-08 15:17:48] [INFO ] Computed 0 place invariants in 1 ms
[2023-03-08 15:17:48] [INFO ] Dead Transitions using invariants and state equation in 81 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 84 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 9 ms
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 10 ms
[2023-03-08 15:17:48] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:48] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:48] [INFO ] Invariant cache hit.
[2023-03-08 15:17:48] [INFO ] Dead Transitions using invariants and state equation in 76 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 78 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 9 ms
[2023-03-08 15:17:48] [INFO ] Flatten gal took : 9 ms
[2023-03-08 15:17:48] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:48] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:48] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 85 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 88 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 8 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 8 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 77 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 79 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 16 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 7 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 87 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 89 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 7 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 17 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 86 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 91 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 7 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 16 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 79 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 81 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 5 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 73 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 79 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 77 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 79 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 2 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 75 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 78 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 4 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:49] [INFO ] Dead Transitions using invariants and state equation in 85 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 92 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:49] [INFO ] Flatten gal took : 7 ms
[2023-03-08 15:17:49] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 4 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:49] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:49] [INFO ] Invariant cache hit.
[2023-03-08 15:17:50] [INFO ] Dead Transitions using invariants and state equation in 79 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 84 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:50] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 4 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:50] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:50] [INFO ] Invariant cache hit.
[2023-03-08 15:17:50] [INFO ] Dead Transitions using invariants and state equation in 81 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 88 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:50] [INFO ] Input system was already deterministic with 250 transitions.
Starting structural reductions in LTL mode, iteration 0 : 34/34 places, 250/250 transitions.
Applied a total of 0 rules in 1 ms. Remains 34 /34 variables (removed 0) and now considering 250/250 (removed 0) transitions.
[2023-03-08 15:17:50] [INFO ] Flow matrix only has 247 transitions (discarded 3 similar events)
[2023-03-08 15:17:50] [INFO ] Invariant cache hit.
[2023-03-08 15:17:50] [INFO ] Dead Transitions using invariants and state equation in 80 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 83 ms. Remains : 34/34 places, 250/250 transitions.
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 4 ms
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:50] [INFO ] Input system was already deterministic with 250 transitions.
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 6 ms
[2023-03-08 15:17:50] [INFO ] Flatten gal took : 5 ms
[2023-03-08 15:17:50] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 15:17:50] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 34 places, 250 transitions and 728 arcs took 1 ms.
Total runtime 47992 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DNAwalker-PT-05track28LR
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA DNAwalker-PT-05track28LR-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DNAwalker-PT-05track28LR-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678288771763

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 25 (type EXCL) for 24 DNAwalker-PT-05track28LR-CTLFireability-08
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-08
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 4 (type EXCL) for 3 DNAwalker-PT-05track28LR-CTLFireability-01
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 4 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-01
lola: result : false
lola: markings : 31234
lola: fired transitions : 40093
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 DNAwalker-PT-05track28LR-CTLFireability-15
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 44 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-15
lola: result : false
lola: markings : 9
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 DNAwalker-PT-05track28LR-CTLFireability-10
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 46 (type FNDP) for 36 DNAwalker-PT-05track28LR-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type EQUN) for 36 DNAwalker-PT-05track28LR-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type SRCH) for 36 DNAwalker-PT-05track28LR-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 46 (type FNDP) for DNAwalker-PT-05track28LR-CTLFireability-14
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 47 (type EQUN) for DNAwalker-PT-05track28LR-CTLFireability-14 (obsolete)
lola: CANCELED task # 50 (type SRCH) for DNAwalker-PT-05track28LR-CTLFireability-14 (obsolete)
lola: LAUNCH task # 51 (type FNDP) for 6 DNAwalker-PT-05track28LR-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type FNDP) for DNAwalker-PT-05track28LR-CTLFireability-02
lola: result : true
lola: fired transitions : 21
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/372/CTLFireability-47.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 47 (type EQUN) for DNAwalker-PT-05track28LR-CTLFireability-14
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/400 8/32 DNAwalker-PT-05track28LR-CTLFireability-10 1742750 m, 348550 m/sec, 5908644 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/400 14/32 DNAwalker-PT-05track28LR-CTLFireability-10 3251914 m, 301832 m/sec, 12075460 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/400 20/32 DNAwalker-PT-05track28LR-CTLFireability-10 4698416 m, 289300 m/sec, 18367703 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/400 26/32 DNAwalker-PT-05track28LR-CTLFireability-10 6090814 m, 278479 m/sec, 24549943 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/400 31/32 DNAwalker-PT-05track28LR-CTLFireability-10 7294680 m, 240773 m/sec, 31228140 t fired, .

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lola: CANCELED task # 28 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 19 (type EXCL) for 18 DNAwalker-PT-05track28LR-CTLFireability-06
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-06
lola: result : false
lola: markings : 9
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 DNAwalker-PT-05track28LR-CTLFireability-05
lola: time limit : 510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-05
lola: result : false
lola: markings : 16
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 DNAwalker-PT-05track28LR-CTLFireability-04
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for DNAwalker-PT-05track28LR-CTLFireability-04
lola: result : false
lola: markings : 9
lola: fired transitions : 25
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-04: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-05: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/714 5/32 DNAwalker-PT-05track28LR-CTLFireability-03 1114094 m, 222818 m/sec, 3694183 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/714 10/32 DNAwalker-PT-05track28LR-CTLFireability-03 2159834 m, 209148 m/sec, 7396947 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/714 14/32 DNAwalker-PT-05track28LR-CTLFireability-03 3101854 m, 188404 m/sec, 11333850 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/714 17/32 DNAwalker-PT-05track28LR-CTLFireability-03 3987041 m, 177037 m/sec, 15241678 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/714 21/32 DNAwalker-PT-05track28LR-CTLFireability-03 4917643 m, 186120 m/sec, 18831947 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/714 25/32 DNAwalker-PT-05track28LR-CTLFireability-03 5835243 m, 183520 m/sec, 22555866 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/714 29/32 DNAwalker-PT-05track28LR-CTLFireability-03 6766285 m, 186208 m/sec, 26302048 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
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DNAwalker-PT-05track28LR-CTLFireability-05: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

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DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
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DNAwalker-PT-05track28LR-CTLFireability-05: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/882 7/32 DNAwalker-PT-05track28LR-CTLFireability-00 1497489 m, 299497 m/sec, 6565788 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

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DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/882 13/32 DNAwalker-PT-05track28LR-CTLFireability-00 2917849 m, 284072 m/sec, 13143400 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

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DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/882 18/32 DNAwalker-PT-05track28LR-CTLFireability-00 4181633 m, 252756 m/sec, 19871214 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
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DNAwalker-PT-05track28LR-CTLFireability-05: CTL false CTL model checker
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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

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DNAwalker-PT-05track28LR-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/882 23/32 DNAwalker-PT-05track28LR-CTLFireability-00 5470095 m, 257692 m/sec, 26224381 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
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DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker

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DNAwalker-PT-05track28LR-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-13: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/882 29/32 DNAwalker-PT-05track28LR-CTLFireability-00 6772166 m, 260414 m/sec, 32754517 t fired, .

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DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
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DNAwalker-PT-05track28LR-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
DNAwalker-PT-05track28LR-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DNAwalker-PT-05track28LR-CTLFireability-00: CTL unknown AGGR
DNAwalker-PT-05track28LR-CTLFireability-01: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-02: EF DL true findpath
DNAwalker-PT-05track28LR-CTLFireability-03: CTL unknown AGGR
DNAwalker-PT-05track28LR-CTLFireability-04: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-05: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-06: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-07: AGEF false tscc_search
DNAwalker-PT-05track28LR-CTLFireability-08: CTL false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-10: CTL unknown AGGR
DNAwalker-PT-05track28LR-CTLFireability-12: AFAG false CTL model checker
DNAwalker-PT-05track28LR-CTLFireability-13: EG true state space / EG
DNAwalker-PT-05track28LR-CTLFireability-14: DISJ true findpath
DNAwalker-PT-05track28LR-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DNAwalker-PT-05track28LR"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DNAwalker-PT-05track28LR, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478900906"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DNAwalker-PT-05track28LR.tgz
mv DNAwalker-PT-05track28LR execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;