Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478900858.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCshifumi-PT-6a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478900858
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.4M
-rw-r--r-- 1 mcc users 8.8K Feb 27 04:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 101K Feb 27 04:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 27 00:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 27 00:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 27 09:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K Feb 27 09:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 27 06:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 27 06:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.9M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-00
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-01
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-02
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-03
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-04
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-05
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-06
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-07
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-08
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-09
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-10
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-11
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-12
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-13
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-14
FORMULA_NAME DLCshifumi-PT-6a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678284026156

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCshifumi-PT-6a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 14:00:27] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 14:00:27] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 14:00:28] [INFO ] Load time of PNML (sax parser for PT used): 524 ms
[2023-03-08 14:00:28] [INFO ] Transformed 3568 places.
[2023-03-08 14:00:28] [INFO ] Transformed 25936 transitions.
[2023-03-08 14:00:28] [INFO ] Found NUPN structural information;
[2023-03-08 14:00:28] [INFO ] Parsed PT model containing 3568 places and 25936 transitions and 101182 arcs in 726 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Ensure Unique test removed 2976 transitions
Reduce redundant transitions removed 2976 transitions.
Support contains 256 out of 3568 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 3568/3568 places, 22960/22960 transitions.
Discarding 346 places :
Symmetric choice reduction at 0 with 346 rule applications. Total rules 346 place count 3222 transition count 20538
Iterating global reduction 0 with 346 rules applied. Total rules applied 692 place count 3222 transition count 20538
Ensure Unique test removed 169 transitions
Reduce isomorphic transitions removed 169 transitions.
Iterating post reduction 0 with 169 rules applied. Total rules applied 861 place count 3222 transition count 20369
Applied a total of 861 rules in 1417 ms. Remains 3222 /3568 variables (removed 346) and now considering 20369/22960 (removed 2591) transitions.
[2023-03-08 14:00:29] [INFO ] Flow matrix only has 1413 transitions (discarded 18956 similar events)
// Phase 1: matrix 1413 rows 3222 cols
[2023-03-08 14:00:30] [INFO ] Computed 2415 place invariants in 35 ms
[2023-03-08 14:00:32] [INFO ] Implicit Places using invariants in 2316 ms returned []
Implicit Place search using SMT only with invariants took 2345 ms to find 0 implicit places.
[2023-03-08 14:00:32] [INFO ] Flow matrix only has 1413 transitions (discarded 18956 similar events)
[2023-03-08 14:00:32] [INFO ] Invariant cache hit.
[2023-03-08 14:01:02] [INFO ] Dead Transitions using invariants and state equation in 29911 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 3222/3568 places, 20369/22960 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33680 ms. Remains : 3222/3568 places, 20369/22960 transitions.
Support contains 256 out of 3222 places after structural reductions.
[2023-03-08 14:01:03] [INFO ] Flatten gal took : 1179 ms
[2023-03-08 14:01:04] [INFO ] Flatten gal took : 960 ms
[2023-03-08 14:01:05] [INFO ] Input system was already deterministic with 20369 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 867 ms. (steps per millisecond=11 ) properties (out of 116) seen :110
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 368 ms. (steps per millisecond=27 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 333 ms. (steps per millisecond=30 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 333 ms. (steps per millisecond=30 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 364 ms. (steps per millisecond=27 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 332 ms. (steps per millisecond=30 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 335 ms. (steps per millisecond=29 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-08 14:01:08] [INFO ] Flow matrix only has 1413 transitions (discarded 18956 similar events)
[2023-03-08 14:01:08] [INFO ] Invariant cache hit.
[2023-03-08 14:01:09] [INFO ] After 616ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-08 14:01:10] [INFO ] [Nat]Absence check using 2415 positive place invariants in 875 ms returned sat
[2023-03-08 14:01:13] [INFO ] After 2668ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-08 14:01:14] [INFO ] State equation strengthened by 403 read => feed constraints.
[2023-03-08 14:01:15] [INFO ] After 1316ms SMT Verify possible using 403 Read/Feed constraints in natural domain returned unsat :0 sat :6
[2023-03-08 14:01:17] [INFO ] After 3254ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :6
Attempting to minimize the solution found.
Minimization took 1248 ms.
[2023-03-08 14:01:18] [INFO ] After 9115ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :6
Fused 6 Parikh solutions to 5 different solutions.
Parikh walk visited 1 properties in 416 ms.
Support contains 16 out of 3222 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Graph (trivial) has 1207 edges and 3222 vertex of which 390 / 3222 are part of one of the 189 SCC in 8 ms
Free SCC test removed 201 places
Drop transitions removed 11913 transitions
Reduce isomorphic transitions removed 11913 transitions.
Graph (complete) has 11266 edges and 3021 vertex of which 1543 are kept as prefixes of interest. Removing 1478 places using SCC suffix rule.16 ms
Discarding 1478 places :
Also discarding 3115 output transitions
Drop transitions removed 3115 transitions
Drop transitions removed 1505 transitions
Reduce isomorphic transitions removed 1505 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 1508 rules applied. Total rules applied 1510 place count 1543 transition count 3833
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 1513 place count 1540 transition count 3833
Discarding 1464 places :
Symmetric choice reduction at 2 with 1464 rule applications. Total rules 2977 place count 76 transition count 209
Iterating global reduction 2 with 1464 rules applied. Total rules applied 4441 place count 76 transition count 209
Ensure Unique test removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 2 with 25 rules applied. Total rules applied 4466 place count 76 transition count 184
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 1 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 3 with 14 rules applied. Total rules applied 4480 place count 69 transition count 177
Drop transitions removed 66 transitions
Reduce isomorphic transitions removed 66 transitions.
Graph (complete) has 164 edges and 69 vertex of which 65 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.1 ms
Discarding 4 places :
Also discarding 0 output transitions
Iterating post reduction 3 with 67 rules applied. Total rules applied 4547 place count 65 transition count 111
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 3 Pre rules applied. Total rules applied 4547 place count 65 transition count 108
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 4 with 6 rules applied. Total rules applied 4553 place count 62 transition count 108
Drop transitions removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 4 with 25 rules applied. Total rules applied 4578 place count 62 transition count 83
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 2 Pre rules applied. Total rules applied 4578 place count 62 transition count 81
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 5 with 4 rules applied. Total rules applied 4582 place count 60 transition count 81
Discarding 12 places :
Symmetric choice reduction at 5 with 12 rule applications. Total rules 4594 place count 48 transition count 63
Iterating global reduction 5 with 12 rules applied. Total rules applied 4606 place count 48 transition count 63
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 5 with 3 rules applied. Total rules applied 4609 place count 48 transition count 60
Free-agglomeration rule applied 2 times with reduction of 5 identical transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 4611 place count 48 transition count 53
Reduce places removed 2 places and 0 transitions.
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 7 rules applied. Total rules applied 4618 place count 46 transition count 48
Applied a total of 4618 rules in 163 ms. Remains 46 /3222 variables (removed 3176) and now considering 48/20369 (removed 20321) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 163 ms. Remains : 46/3222 places, 48/20369 transitions.
Finished random walk after 36 steps, including 0 resets, run visited all 5 properties in 2 ms. (steps per millisecond=18 )
[2023-03-08 14:01:19] [INFO ] Flatten gal took : 706 ms
[2023-03-08 14:01:20] [INFO ] Flatten gal took : 740 ms
[2023-03-08 14:01:21] [INFO ] Input system was already deterministic with 20369 transitions.
Computed a total of 2227 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 3192 transition count 18146
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 3192 transition count 18146
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 74 place count 3192 transition count 18132
Drop transitions removed 5768 transitions
Redundant transition composition rules discarded 5768 transitions
Iterating global reduction 1 with 5768 rules applied. Total rules applied 5842 place count 3192 transition count 12364
Applied a total of 5842 rules in 1657 ms. Remains 3192 /3222 variables (removed 30) and now considering 12364/20369 (removed 8005) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1659 ms. Remains : 3192/3222 places, 12364/20369 transitions.
[2023-03-08 14:01:23] [INFO ] Flatten gal took : 635 ms
[2023-03-08 14:01:24] [INFO ] Flatten gal took : 711 ms
[2023-03-08 14:01:24] [INFO ] Input system was already deterministic with 12364 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 28 places :
Symmetric choice reduction at 0 with 28 rule applications. Total rules 28 place count 3194 transition count 18526
Iterating global reduction 0 with 28 rules applied. Total rules applied 56 place count 3194 transition count 18526
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 69 place count 3194 transition count 18513
Drop transitions removed 6144 transitions
Redundant transition composition rules discarded 6144 transitions
Iterating global reduction 1 with 6144 rules applied. Total rules applied 6213 place count 3194 transition count 12369
Applied a total of 6213 rules in 1437 ms. Remains 3194 /3222 variables (removed 28) and now considering 12369/20369 (removed 8000) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1438 ms. Remains : 3194/3222 places, 12369/20369 transitions.
[2023-03-08 14:01:26] [INFO ] Flatten gal took : 628 ms
[2023-03-08 14:01:27] [INFO ] Flatten gal took : 678 ms
[2023-03-08 14:01:27] [INFO ] Input system was already deterministic with 12369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 25 place count 3197 transition count 18730
Iterating global reduction 0 with 25 rules applied. Total rules applied 50 place count 3197 transition count 18730
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 61 place count 3197 transition count 18719
Drop transitions removed 6332 transitions
Redundant transition composition rules discarded 6332 transitions
Iterating global reduction 1 with 6332 rules applied. Total rules applied 6393 place count 3197 transition count 12387
Applied a total of 6393 rules in 1461 ms. Remains 3197 /3222 variables (removed 25) and now considering 12387/20369 (removed 7982) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1465 ms. Remains : 3197/3222 places, 12387/20369 transitions.
[2023-03-08 14:01:30] [INFO ] Flatten gal took : 700 ms
[2023-03-08 14:01:30] [INFO ] Flatten gal took : 746 ms
[2023-03-08 14:01:31] [INFO ] Input system was already deterministic with 12387 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Graph (trivial) has 1209 edges and 3222 vertex of which 384 / 3222 are part of one of the 187 SCC in 4 ms
Free SCC test removed 197 places
Ensure Unique test removed 3361 transitions
Reduce isomorphic transitions removed 3361 transitions.
Drop transitions removed 182 transitions
Trivial Post-agglo rules discarded 182 transitions
Performed 182 trivial Post agglomeration. Transition count delta: 182
Iterating post reduction 0 with 182 rules applied. Total rules applied 183 place count 3025 transition count 16826
Reduce places removed 182 places and 0 transitions.
Iterating post reduction 1 with 182 rules applied. Total rules applied 365 place count 2843 transition count 16826
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 365 place count 2843 transition count 16825
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 367 place count 2842 transition count 16825
Discarding 175 places :
Symmetric choice reduction at 2 with 175 rule applications. Total rules 542 place count 2667 transition count 14376
Iterating global reduction 2 with 175 rules applied. Total rules applied 717 place count 2667 transition count 14376
Ensure Unique test removed 1912 transitions
Reduce isomorphic transitions removed 1912 transitions.
Iterating post reduction 2 with 1912 rules applied. Total rules applied 2629 place count 2667 transition count 12464
Performed 193 Post agglomeration using F-continuation condition.Transition count delta: 193
Deduced a syphon composed of 193 places in 2 ms
Reduce places removed 193 places and 0 transitions.
Iterating global reduction 3 with 386 rules applied. Total rules applied 3015 place count 2474 transition count 12271
Ensure Unique test removed 2032 transitions
Reduce isomorphic transitions removed 2032 transitions.
Iterating post reduction 3 with 2032 rules applied. Total rules applied 5047 place count 2474 transition count 10239
Drop transitions removed 5788 transitions
Redundant transition composition rules discarded 5788 transitions
Iterating global reduction 4 with 5788 rules applied. Total rules applied 10835 place count 2474 transition count 4451
Reduce places removed 815 places and 0 transitions.
Iterating post reduction 4 with 815 rules applied. Total rules applied 11650 place count 1659 transition count 4451
Discarding 1392 places :
Symmetric choice reduction at 5 with 1392 rule applications. Total rules 13042 place count 267 transition count 752
Iterating global reduction 5 with 1392 rules applied. Total rules applied 14434 place count 267 transition count 752
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 5 with 28 rules applied. Total rules applied 14462 place count 253 transition count 738
Applied a total of 14462 rules in 1647 ms. Remains 253 /3222 variables (removed 2969) and now considering 738/20369 (removed 19631) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1647 ms. Remains : 253/3222 places, 738/20369 transitions.
[2023-03-08 14:01:32] [INFO ] Flatten gal took : 13 ms
[2023-03-08 14:01:32] [INFO ] Flatten gal took : 14 ms
[2023-03-08 14:01:32] [INFO ] Input system was already deterministic with 738 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 29 place count 3193 transition count 18336
Iterating global reduction 0 with 29 rules applied. Total rules applied 58 place count 3193 transition count 18336
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 72 place count 3193 transition count 18322
Drop transitions removed 5956 transitions
Redundant transition composition rules discarded 5956 transitions
Iterating global reduction 1 with 5956 rules applied. Total rules applied 6028 place count 3193 transition count 12366
Applied a total of 6028 rules in 1470 ms. Remains 3193 /3222 variables (removed 29) and now considering 12366/20369 (removed 8003) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1471 ms. Remains : 3193/3222 places, 12366/20369 transitions.
[2023-03-08 14:01:35] [INFO ] Flatten gal took : 668 ms
[2023-03-08 14:01:35] [INFO ] Flatten gal took : 652 ms
[2023-03-08 14:01:36] [INFO ] Input system was already deterministic with 12366 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 3192 transition count 17963
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 3192 transition count 17963
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 72 place count 3192 transition count 17951
Drop transitions removed 5580 transitions
Redundant transition composition rules discarded 5580 transitions
Iterating global reduction 1 with 5580 rules applied. Total rules applied 5652 place count 3192 transition count 12371
Applied a total of 5652 rules in 1542 ms. Remains 3192 /3222 variables (removed 30) and now considering 12371/20369 (removed 7998) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1544 ms. Remains : 3192/3222 places, 12371/20369 transitions.
[2023-03-08 14:01:38] [INFO ] Flatten gal took : 630 ms
[2023-03-08 14:01:39] [INFO ] Flatten gal took : 706 ms
[2023-03-08 14:01:39] [INFO ] Input system was already deterministic with 12371 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 3192 transition count 18146
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 3192 transition count 18146
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 73 place count 3192 transition count 18133
Drop transitions removed 5768 transitions
Redundant transition composition rules discarded 5768 transitions
Iterating global reduction 1 with 5768 rules applied. Total rules applied 5841 place count 3192 transition count 12365
Applied a total of 5841 rules in 1467 ms. Remains 3192 /3222 variables (removed 30) and now considering 12365/20369 (removed 8004) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1468 ms. Remains : 3192/3222 places, 12365/20369 transitions.
[2023-03-08 14:01:41] [INFO ] Flatten gal took : 663 ms
[2023-03-08 14:01:42] [INFO ] Flatten gal took : 651 ms
[2023-03-08 14:01:42] [INFO ] Input system was already deterministic with 12365 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 3192 transition count 18329
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 3192 transition count 18329
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 74 place count 3192 transition count 18315
Drop transitions removed 5956 transitions
Redundant transition composition rules discarded 5956 transitions
Iterating global reduction 1 with 5956 rules applied. Total rules applied 6030 place count 3192 transition count 12359
Applied a total of 6030 rules in 1448 ms. Remains 3192 /3222 variables (removed 30) and now considering 12359/20369 (removed 8010) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1448 ms. Remains : 3192/3222 places, 12359/20369 transitions.
[2023-03-08 14:01:44] [INFO ] Flatten gal took : 626 ms
[2023-03-08 14:01:45] [INFO ] Flatten gal took : 714 ms
[2023-03-08 14:01:45] [INFO ] Input system was already deterministic with 12359 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 28 places :
Symmetric choice reduction at 0 with 28 rule applications. Total rules 28 place count 3194 transition count 18343
Iterating global reduction 0 with 28 rules applied. Total rules applied 56 place count 3194 transition count 18343
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 69 place count 3194 transition count 18330
Drop transitions removed 5956 transitions
Redundant transition composition rules discarded 5956 transitions
Iterating global reduction 1 with 5956 rules applied. Total rules applied 6025 place count 3194 transition count 12374
Applied a total of 6025 rules in 1492 ms. Remains 3194 /3222 variables (removed 28) and now considering 12374/20369 (removed 7995) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1492 ms. Remains : 3194/3222 places, 12374/20369 transitions.
[2023-03-08 14:01:48] [INFO ] Flatten gal took : 669 ms
[2023-03-08 14:01:48] [INFO ] Flatten gal took : 657 ms
[2023-03-08 14:01:49] [INFO ] Input system was already deterministic with 12374 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 3201 transition count 19124
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 3201 transition count 19124
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 53 place count 3201 transition count 19113
Drop transitions removed 6708 transitions
Redundant transition composition rules discarded 6708 transitions
Iterating global reduction 1 with 6708 rules applied. Total rules applied 6761 place count 3201 transition count 12405
Applied a total of 6761 rules in 1546 ms. Remains 3201 /3222 variables (removed 21) and now considering 12405/20369 (removed 7964) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1546 ms. Remains : 3201/3222 places, 12405/20369 transitions.
[2023-03-08 14:01:51] [INFO ] Flatten gal took : 641 ms
[2023-03-08 14:01:51] [INFO ] Flatten gal took : 664 ms
[2023-03-08 14:01:52] [INFO ] Input system was already deterministic with 12405 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 29 place count 3193 transition count 18153
Iterating global reduction 0 with 29 rules applied. Total rules applied 58 place count 3193 transition count 18153
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 0 with 13 rules applied. Total rules applied 71 place count 3193 transition count 18140
Drop transitions removed 5768 transitions
Redundant transition composition rules discarded 5768 transitions
Iterating global reduction 1 with 5768 rules applied. Total rules applied 5839 place count 3193 transition count 12372
Applied a total of 5839 rules in 1484 ms. Remains 3193 /3222 variables (removed 29) and now considering 12372/20369 (removed 7997) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1484 ms. Remains : 3193/3222 places, 12372/20369 transitions.
[2023-03-08 14:01:54] [INFO ] Flatten gal took : 630 ms
[2023-03-08 14:01:55] [INFO ] Flatten gal took : 729 ms
[2023-03-08 14:01:55] [INFO ] Input system was already deterministic with 12372 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Graph (trivial) has 1218 edges and 3222 vertex of which 386 / 3222 are part of one of the 188 SCC in 2 ms
Free SCC test removed 198 places
Ensure Unique test removed 3369 transitions
Reduce isomorphic transitions removed 3369 transitions.
Drop transitions removed 183 transitions
Trivial Post-agglo rules discarded 183 transitions
Performed 183 trivial Post agglomeration. Transition count delta: 183
Iterating post reduction 0 with 183 rules applied. Total rules applied 184 place count 3024 transition count 16817
Reduce places removed 183 places and 0 transitions.
Iterating post reduction 1 with 183 rules applied. Total rules applied 367 place count 2841 transition count 16817
Discarding 175 places :
Symmetric choice reduction at 2 with 175 rule applications. Total rules 542 place count 2666 transition count 14374
Iterating global reduction 2 with 175 rules applied. Total rules applied 717 place count 2666 transition count 14374
Ensure Unique test removed 1918 transitions
Reduce isomorphic transitions removed 1918 transitions.
Iterating post reduction 2 with 1918 rules applied. Total rules applied 2635 place count 2666 transition count 12456
Performed 195 Post agglomeration using F-continuation condition.Transition count delta: 195
Deduced a syphon composed of 195 places in 3 ms
Reduce places removed 195 places and 0 transitions.
Iterating global reduction 3 with 390 rules applied. Total rules applied 3025 place count 2471 transition count 12261
Ensure Unique test removed 2226 transitions
Reduce isomorphic transitions removed 2226 transitions.
Iterating post reduction 3 with 2226 rules applied. Total rules applied 5251 place count 2471 transition count 10035
Drop transitions removed 5782 transitions
Redundant transition composition rules discarded 5782 transitions
Iterating global reduction 4 with 5782 rules applied. Total rules applied 11033 place count 2471 transition count 4253
Reduce places removed 815 places and 0 transitions.
Iterating post reduction 4 with 815 rules applied. Total rules applied 11848 place count 1656 transition count 4253
Discarding 1400 places :
Symmetric choice reduction at 5 with 1400 rule applications. Total rules 13248 place count 256 transition count 695
Iterating global reduction 5 with 1400 rules applied. Total rules applied 14648 place count 256 transition count 695
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: 14
Deduced a syphon composed of 14 places in 0 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 5 with 28 rules applied. Total rules applied 14676 place count 242 transition count 681
Applied a total of 14676 rules in 1188 ms. Remains 242 /3222 variables (removed 2980) and now considering 681/20369 (removed 19688) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1188 ms. Remains : 242/3222 places, 681/20369 transitions.
[2023-03-08 14:01:56] [INFO ] Flatten gal took : 12 ms
[2023-03-08 14:01:56] [INFO ] Flatten gal took : 14 ms
[2023-03-08 14:01:56] [INFO ] Input system was already deterministic with 681 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Graph (trivial) has 1220 edges and 3222 vertex of which 390 / 3222 are part of one of the 189 SCC in 1 ms
Free SCC test removed 201 places
Ensure Unique test removed 3750 transitions
Reduce isomorphic transitions removed 3750 transitions.
Drop transitions removed 183 transitions
Trivial Post-agglo rules discarded 183 transitions
Performed 183 trivial Post agglomeration. Transition count delta: 183
Iterating post reduction 0 with 183 rules applied. Total rules applied 184 place count 3021 transition count 16436
Reduce places removed 183 places and 0 transitions.
Iterating post reduction 1 with 183 rules applied. Total rules applied 367 place count 2838 transition count 16436
Discarding 175 places :
Symmetric choice reduction at 2 with 175 rule applications. Total rules 542 place count 2663 transition count 13993
Iterating global reduction 2 with 175 rules applied. Total rules applied 717 place count 2663 transition count 13993
Ensure Unique test removed 2106 transitions
Reduce isomorphic transitions removed 2106 transitions.
Iterating post reduction 2 with 2106 rules applied. Total rules applied 2823 place count 2663 transition count 11887
Performed 195 Post agglomeration using F-continuation condition.Transition count delta: 195
Deduced a syphon composed of 195 places in 2 ms
Reduce places removed 195 places and 0 transitions.
Iterating global reduction 3 with 390 rules applied. Total rules applied 3213 place count 2468 transition count 11692
Ensure Unique test removed 2226 transitions
Reduce isomorphic transitions removed 2226 transitions.
Iterating post reduction 3 with 2226 rules applied. Total rules applied 5439 place count 2468 transition count 9466
Drop transitions removed 5593 transitions
Redundant transition composition rules discarded 5593 transitions
Iterating global reduction 4 with 5593 rules applied. Total rules applied 11032 place count 2468 transition count 3873
Reduce places removed 978 places and 0 transitions.
Iterating post reduction 4 with 978 rules applied. Total rules applied 12010 place count 1490 transition count 3873
Discarding 1263 places :
Symmetric choice reduction at 5 with 1263 rule applications. Total rules 13273 place count 227 transition count 606
Iterating global reduction 5 with 1263 rules applied. Total rules applied 14536 place count 227 transition count 606
Performed 13 Post agglomeration using F-continuation condition.Transition count delta: 13
Deduced a syphon composed of 13 places in 0 ms
Reduce places removed 13 places and 0 transitions.
Iterating global reduction 5 with 26 rules applied. Total rules applied 14562 place count 214 transition count 593
Applied a total of 14562 rules in 1351 ms. Remains 214 /3222 variables (removed 3008) and now considering 593/20369 (removed 19776) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1351 ms. Remains : 214/3222 places, 593/20369 transitions.
[2023-03-08 14:01:58] [INFO ] Flatten gal took : 10 ms
[2023-03-08 14:01:58] [INFO ] Flatten gal took : 12 ms
[2023-03-08 14:01:58] [INFO ] Input system was already deterministic with 593 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 3192 transition count 18329
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 3192 transition count 18329
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 74 place count 3192 transition count 18315
Drop transitions removed 5956 transitions
Redundant transition composition rules discarded 5956 transitions
Iterating global reduction 1 with 5956 rules applied. Total rules applied 6030 place count 3192 transition count 12359
Applied a total of 6030 rules in 1486 ms. Remains 3192 /3222 variables (removed 30) and now considering 12359/20369 (removed 8010) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1486 ms. Remains : 3192/3222 places, 12359/20369 transitions.
[2023-03-08 14:02:00] [INFO ] Flatten gal took : 644 ms
[2023-03-08 14:02:01] [INFO ] Flatten gal took : 721 ms
[2023-03-08 14:02:01] [INFO ] Input system was already deterministic with 12359 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 32 place count 3190 transition count 17949
Iterating global reduction 0 with 32 rules applied. Total rules applied 64 place count 3190 transition count 17949
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 78 place count 3190 transition count 17935
Drop transitions removed 5580 transitions
Redundant transition composition rules discarded 5580 transitions
Iterating global reduction 1 with 5580 rules applied. Total rules applied 5658 place count 3190 transition count 12355
Applied a total of 5658 rules in 1546 ms. Remains 3190 /3222 variables (removed 32) and now considering 12355/20369 (removed 8014) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1546 ms. Remains : 3190/3222 places, 12355/20369 transitions.
[2023-03-08 14:02:03] [INFO ] Flatten gal took : 687 ms
[2023-03-08 14:02:04] [INFO ] Flatten gal took : 629 ms
[2023-03-08 14:02:04] [INFO ] Input system was already deterministic with 12355 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3222/3222 places, 20369/20369 transitions.
Graph (trivial) has 1180 edges and 3222 vertex of which 368 / 3222 are part of one of the 182 SCC in 2 ms
Free SCC test removed 186 places
Ensure Unique test removed 2202 transitions
Reduce isomorphic transitions removed 2202 transitions.
Drop transitions removed 180 transitions
Trivial Post-agglo rules discarded 180 transitions
Performed 180 trivial Post agglomeration. Transition count delta: 180
Iterating post reduction 0 with 180 rules applied. Total rules applied 181 place count 3036 transition count 17987
Reduce places removed 180 places and 0 transitions.
Iterating post reduction 1 with 180 rules applied. Total rules applied 361 place count 2856 transition count 17987
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 3 Pre rules applied. Total rules applied 361 place count 2856 transition count 17984
Deduced a syphon composed of 3 places in 4 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 367 place count 2853 transition count 17984
Discarding 170 places :
Symmetric choice reduction at 2 with 170 rule applications. Total rules 537 place count 2683 transition count 16296
Iterating global reduction 2 with 170 rules applied. Total rules applied 707 place count 2683 transition count 16296
Ensure Unique test removed 1155 transitions
Reduce isomorphic transitions removed 1155 transitions.
Iterating post reduction 2 with 1155 rules applied. Total rules applied 1862 place count 2683 transition count 15141
Performed 192 Post agglomeration using F-continuation condition.Transition count delta: 192
Deduced a syphon composed of 192 places in 4 ms
Reduce places removed 192 places and 0 transitions.
Iterating global reduction 3 with 384 rules applied. Total rules applied 2246 place count 2491 transition count 14949
Ensure Unique test removed 1644 transitions
Reduce isomorphic transitions removed 1644 transitions.
Iterating post reduction 3 with 1644 rules applied. Total rules applied 3890 place count 2491 transition count 13305
Drop transitions removed 6738 transitions
Redundant transition composition rules discarded 6738 transitions
Iterating global reduction 4 with 6738 rules applied. Total rules applied 10628 place count 2491 transition count 6567
Reduce places removed 322 places and 0 transitions.
Iterating post reduction 4 with 322 rules applied. Total rules applied 10950 place count 2169 transition count 6567
Discarding 1784 places :
Symmetric choice reduction at 5 with 1784 rule applications. Total rules 12734 place count 385 transition count 1256
Iterating global reduction 5 with 1784 rules applied. Total rules applied 14518 place count 385 transition count 1256
Performed 12 Post agglomeration using F-continuation condition.Transition count delta: 12
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 5 with 24 rules applied. Total rules applied 14542 place count 373 transition count 1244
Applied a total of 14542 rules in 1501 ms. Remains 373 /3222 variables (removed 2849) and now considering 1244/20369 (removed 19125) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1501 ms. Remains : 373/3222 places, 1244/20369 transitions.
[2023-03-08 14:02:06] [INFO ] Flatten gal took : 21 ms
[2023-03-08 14:02:06] [INFO ] Flatten gal took : 23 ms
[2023-03-08 14:02:06] [INFO ] Input system was already deterministic with 1244 transitions.
[2023-03-08 14:02:07] [INFO ] Flatten gal took : 727 ms
[2023-03-08 14:02:07] [INFO ] Flatten gal took : 723 ms
[2023-03-08 14:02:07] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 14:02:07] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 3222 places, 20369 transitions and 81444 arcs took 71 ms.
Total runtime 100378 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCshifumi-PT-6a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/367
CTLFireability

FORMULA DLCshifumi-PT-6a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678284453278

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/367/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/367/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/367/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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5 CTL EXCL 0/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 121 m, 24 m/sec, 35514 t fired, .

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5 CTL EXCL 5/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 3769 m, 729 m/sec, 1284180 t fired, .

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5 CTL EXCL 10/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 7882 m, 822 m/sec, 2696901 t fired, .

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5 CTL EXCL 15/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 11789 m, 781 m/sec, 3987447 t fired, .

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5 CTL EXCL 21/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 25167 m, 2675 m/sec, 8404195 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

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DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 1 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 1 0 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 26/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 44487 m, 3864 m/sec, 14684096 t fired, .

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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 31/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 49182 m, 939 m/sec, 16229135 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 37/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 65788 m, 3321 m/sec, 21820102 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 42/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 87688 m, 4380 m/sec, 28907950 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 47/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 109848 m, 4432 m/sec, 35953250 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 52/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 131473 m, 4325 m/sec, 42978732 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 57/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 151420 m, 3989 m/sec, 49410728 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 62/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 173711 m, 4458 m/sec, 56560529 t fired, .

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DLCshifumi-PT-6a-CTLFireability-03: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 67/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 196123 m, 4482 m/sec, 63722727 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 72/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 217924 m, 4360 m/sec, 70829007 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 77/201 1/32 DLCshifumi-PT-6a-CTLFireability-00 237514 m, 3918 m/sec, 77154285 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 82/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 259032 m, 4303 m/sec, 84227172 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-CTLFireability-00: DISJ 0 1 1 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-05: CONJ 0 2 0 0 2 0 0 0
DLCshifumi-PT-6a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-11: EG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-12: AFAG 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
5 CTL EXCL 87/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 280588 m, 4311 m/sec, 91304639 t fired, .

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5 CTL EXCL 92/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 301175 m, 4117 m/sec, 97906020 t fired, .

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5 CTL EXCL 97/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 323377 m, 4440 m/sec, 104961255 t fired, .

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5 CTL EXCL 102/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 345172 m, 4359 m/sec, 111953872 t fired, .

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5 CTL EXCL 107/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 366929 m, 4351 m/sec, 118905333 t fired, .

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5 CTL EXCL 112/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 387107 m, 4035 m/sec, 125552117 t fired, .

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5 CTL EXCL 117/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 408888 m, 4356 m/sec, 132743074 t fired, .

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5 CTL EXCL 122/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 429666 m, 4155 m/sec, 139466283 t fired, .

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5 CTL EXCL 127/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 451499 m, 4366 m/sec, 146424031 t fired, .

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5 CTL EXCL 132/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 472135 m, 4127 m/sec, 153151699 t fired, .

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5 CTL EXCL 137/201 2/32 DLCshifumi-PT-6a-CTLFireability-00 493670 m, 4307 m/sec, 160056771 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 479 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-6a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCshifumi-PT-6a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478900858"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-6a.tgz
mv DLCshifumi-PT-6a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;