Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478800842.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCshifumi-PT-5a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478800842
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.3M
-rw-r--r-- 1 mcc users 6.7K Feb 26 11:48 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 26 11:48 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K Feb 26 10:17 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Feb 26 10:17 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Feb 26 15:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 26 15:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 26 13:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 13:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.9M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-00
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-01
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-02
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-03
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-04
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-05
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-06
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-07
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-08
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-09
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-10
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-11
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-12
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-13
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-14
FORMULA_NAME DLCshifumi-PT-5a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678281994452

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCshifumi-PT-5a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 13:26:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 13:26:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 13:26:36] [INFO ] Load time of PNML (sax parser for PT used): 349 ms
[2023-03-08 13:26:36] [INFO ] Transformed 2162 places.
[2023-03-08 13:26:36] [INFO ] Transformed 14865 transitions.
[2023-03-08 13:26:36] [INFO ] Found NUPN structural information;
[2023-03-08 13:26:36] [INFO ] Parsed PT model containing 2162 places and 14865 transitions and 57457 arcs in 462 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Ensure Unique test removed 1757 transitions
Reduce redundant transitions removed 1757 transitions.
Support contains 145 out of 2162 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 2162/2162 places, 13108/13108 transitions.
Discarding 239 places :
Symmetric choice reduction at 0 with 239 rule applications. Total rules 239 place count 1923 transition count 11182
Iterating global reduction 0 with 239 rules applied. Total rules applied 478 place count 1923 transition count 11182
Ensure Unique test removed 116 transitions
Reduce isomorphic transitions removed 116 transitions.
Iterating post reduction 0 with 116 rules applied. Total rules applied 594 place count 1923 transition count 11066
Drop transitions removed 3897 transitions
Redundant transition composition rules discarded 3897 transitions
Iterating global reduction 1 with 3897 rules applied. Total rules applied 4491 place count 1923 transition count 7169
Applied a total of 4491 rules in 898 ms. Remains 1923 /2162 variables (removed 239) and now considering 7169/13108 (removed 5939) transitions.
[2023-03-08 13:26:37] [INFO ] Flow matrix only has 957 transitions (discarded 6212 similar events)
// Phase 1: matrix 957 rows 1923 cols
[2023-03-08 13:26:37] [INFO ] Computed 1378 place invariants in 26 ms
[2023-03-08 13:26:49] [INFO ] Implicit Places using invariants in 12012 ms returned [673, 674, 675, 676, 677, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, 691, 692, 693, 694, 696, 697, 698, 699, 700, 701, 702, 703, 704, 705, 707, 708, 709, 710, 711, 712, 713, 714, 715, 716, 717, 718, 719, 720, 721, 722, 723, 724, 725, 726, 727, 728, 729, 731, 732, 733, 734, 735, 736, 737, 739, 740, 741, 742, 743, 744, 745, 746, 747, 748, 749, 751, 752, 753, 754, 755, 756, 757, 758, 759, 760, 761, 762, 763, 764, 765, 766, 767, 768, 769, 770, 771, 772, 773, 774, 775, 776, 777, 778, 779, 780, 781, 782, 783, 784, 785, 786, 787, 788, 790, 791, 792, 793, 794, 795, 796, 797, 798, 800, 801, 802, 803, 804, 805, 806, 807, 808, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 848, 849, 850, 852, 853, 854, 855, 857, 858, 859, 861, 862, 863, 864, 865, 866, 867, 869, 870, 871, 872, 873, 874, 875, 876, 877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 889, 891, 892, 894, 895, 896, 897, 898, 899, 900, 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, 927, 929, 930, 931, 933, 935, 936, 937, 938, 939, 940, 941, 942, 943, 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, 963, 964, 965, 966, 967, 969, 970, 971, 972, 973, 974, 975, 976, 977, 979, 980, 981, 982, 983, 984, 985, 986, 987, 989, 990, 991, 992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1019, 1020, 1021, 1022, 1023, 1024, 1025, 1026, 1027, 1029, 1030, 1031, 1032, 1033, 1035, 1036, 1037, 1038, 1039, 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055, 1056, 1057, 1058, 1059, 1060, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1081, 1082, 1083, 1084, 1085, 1086, 1087, 1089, 1090, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1104, 1105, 1106, 1107, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119, 1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1131, 1132, 1133, 1134, 1135, 1136, 1137, 1139, 1140, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151, 1152, 1153, 1154, 1155, 1156, 1157, 1160, 1161, 1162, 1163, 1165, 1166, 1167, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1224, 1225, 1226, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1317, 1318, 1319, 1320, 1322, 1324, 1325, 1326, 1327, 1328, 1329, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, 1384, 1385, 1386, 1387, 1388, 1389, 1390, 1391, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1401, 1402, 1404, 1405, 1406, 1407, 1408, 1409, 1410, 1412, 1413, 1415, 1416, 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425, 1426, 1427, 1429, 1430, 1431, 1432, 1433, 1434, 1435, 1436, 1437, 1438, 1439, 1440, 1441, 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1454, 1455, 1456, 1457, 1459, 1460, 1461, 1462, 1464, 1465, 1466, 1467, 1468, 1469, 1470, 1471, 1472, 1473, 1474, 1475, 1476, 1477, 1478, 1479, 1481, 1482, 1483, 1484, 1485, 1486, 1487, 1488, 1489, 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1516, 1517, 1518, 1519, 1520, 1521, 1522, 1523, 1525, 1526, 1527, 1528, 1529, 1530, 1531, 1532, 1533, 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1544, 1545, 1546, 1547, 1549, 1550, 1551, 1552, 1553, 1554, 1555, 1556, 1557, 1558, 1559, 1560, 1561, 1562, 1563, 1564, 1565, 1566, 1567, 1568, 1569, 1570, 1571, 1572, 1573, 1574, 1575, 1576, 1577, 1578, 1579, 1580, 1581, 1582, 1583, 1584, 1585, 1586, 1587, 1588, 1589, 1590, 1591, 1593, 1595, 1596, 1597, 1598, 1599, 1601, 1602, 1603, 1604, 1605, 1606, 1607, 1608, 1609, 1610, 1613, 1614, 1615, 1616, 1617, 1618, 1620, 1621, 1623, 1625, 1626, 1627, 1628, 1629, 1630, 1631, 1633, 1634, 1635, 1636, 1637, 1638, 1639, 1640, 1641, 1642, 1643, 1644, 1645, 1646, 1647, 1648, 1649, 1650, 1651, 1652, 1653, 1654, 1655, 1656, 1657, 1658, 1659, 1660, 1661, 1662, 1663, 1664, 1666, 1667, 1668, 1669, 1670, 1671, 1672, 1673, 1674, 1675, 1676, 1677, 1678, 1679, 1680, 1681, 1682, 1683, 1684, 1685, 1686, 1687, 1688, 1689, 1690, 1691, 1692, 1693, 1694, 1695, 1696, 1697, 1699, 1700, 1701, 1702, 1703, 1704, 1705, 1706, 1707, 1708, 1710, 1711, 1712, 1713, 1714, 1715, 1716, 1717, 1718, 1719, 1721, 1723, 1724, 1725, 1726, 1727, 1728, 1729, 1730, 1731, 1732, 1733, 1734, 1735, 1736, 1737, 1738, 1739, 1741, 1742, 1743, 1744, 1745, 1746, 1747, 1748, 1749, 1750, 1751, 1752, 1755, 1756, 1757, 1758, 1759, 1760, 1761, 1762, 1763, 1764, 1765, 1766, 1767, 1768, 1769, 1770, 1771, 1772, 1773, 1774, 1775, 1776, 1777, 1778, 1779, 1780, 1781, 1782, 1783, 1784, 1785, 1786, 1787, 1788, 1789, 1790, 1791, 1792, 1793, 1794, 1795, 1796, 1797, 1798, 1799, 1800, 1801, 1802, 1803, 1804, 1805, 1806, 1807, 1808, 1809, 1810, 1811, 1812, 1813, 1814, 1815, 1816, 1817, 1818, 1819, 1820, 1822, 1823, 1824, 1825, 1826, 1827, 1828, 1829, 1831, 1832, 1833, 1834, 1835, 1836, 1837, 1838, 1839, 1840, 1841, 1842, 1843, 1844, 1845, 1846, 1847, 1848, 1849, 1850, 1851, 1852, 1853, 1854, 1855, 1856, 1857, 1858, 1859, 1860, 1861, 1862, 1863, 1864, 1865, 1866, 1867, 1868, 1869, 1870, 1871, 1872, 1873, 1874, 1875, 1876, 1877, 1878, 1879, 1880, 1881, 1882, 1883, 1884, 1885, 1886, 1887, 1888, 1889, 1890, 1891, 1892, 1893, 1894, 1895, 1896, 1897, 1898, 1899, 1900, 1901, 1902, 1903, 1904, 1905, 1907, 1908, 1909, 1910, 1911, 1912, 1913, 1914, 1915, 1916, 1917, 1918, 1919, 1920, 1921, 1922]
Discarding 1168 places :
Ensure Unique test removed 5459 transitions
Reduce isomorphic transitions removed 5459 transitions.
Implicit Place search using SMT only with invariants took 12075 ms to find 1168 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 755/2162 places, 1710/13108 transitions.
Drop transitions removed 471 transitions
Redundant transition composition rules discarded 471 transitions
Iterating global reduction 0 with 471 rules applied. Total rules applied 471 place count 755 transition count 1239
Applied a total of 471 rules in 36 ms. Remains 755 /755 variables (removed 0) and now considering 1239/1710 (removed 471) transitions.
[2023-03-08 13:26:49] [INFO ] Flow matrix only has 957 transitions (discarded 282 similar events)
// Phase 1: matrix 957 rows 755 cols
[2023-03-08 13:26:49] [INFO ] Computed 210 place invariants in 3 ms
[2023-03-08 13:26:49] [INFO ] Implicit Places using invariants in 117 ms returned []
[2023-03-08 13:26:49] [INFO ] Flow matrix only has 957 transitions (discarded 282 similar events)
[2023-03-08 13:26:49] [INFO ] Invariant cache hit.
[2023-03-08 13:26:49] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 13:26:49] [INFO ] Implicit Places using invariants and state equation in 341 ms returned []
Implicit Place search using SMT with State Equation took 460 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 755/2162 places, 1239/13108 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 13471 ms. Remains : 755/2162 places, 1239/13108 transitions.
Support contains 145 out of 755 places after structural reductions.
[2023-03-08 13:26:52] [INFO ] Flatten gal took : 93 ms
[2023-03-08 13:26:52] [INFO ] Flatten gal took : 46 ms
[2023-03-08 13:26:52] [INFO ] Input system was already deterministic with 1239 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 399 ms. (steps per millisecond=25 ) properties (out of 73) seen :71
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-08 13:26:52] [INFO ] Flow matrix only has 957 transitions (discarded 282 similar events)
[2023-03-08 13:26:52] [INFO ] Invariant cache hit.
[2023-03-08 13:26:52] [INFO ] [Real]Absence check using 210 positive place invariants in 39 ms returned sat
[2023-03-08 13:26:53] [INFO ] After 508ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 13:26:53] [INFO ] [Nat]Absence check using 210 positive place invariants in 28 ms returned sat
[2023-03-08 13:26:53] [INFO ] After 303ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-08 13:26:53] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 13:26:53] [INFO ] After 85ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-08 13:26:53] [INFO ] After 212ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 82 ms.
[2023-03-08 13:26:53] [INFO ] After 766ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 17 ms.
Support contains 9 out of 755 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Graph (trivial) has 1221 edges and 755 vertex of which 660 / 755 are part of one of the 127 SCC in 7 ms
Free SCC test removed 533 places
Drop transitions removed 1220 transitions
Reduce isomorphic transitions removed 1220 transitions.
Graph (complete) has 228 edges and 222 vertex of which 21 are kept as prefixes of interest. Removing 201 places using SCC suffix rule.0 ms
Discarding 201 places :
Also discarding 0 output transitions
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 5 place count 21 transition count 16
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 9 place count 18 transition count 15
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 9 place count 18 transition count 13
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 13 place count 16 transition count 13
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 14 place count 15 transition count 12
Iterating global reduction 2 with 1 rules applied. Total rules applied 15 place count 15 transition count 12
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 16 place count 15 transition count 11
Applied a total of 16 rules in 17 ms. Remains 15 /755 variables (removed 740) and now considering 11/1239 (removed 1228) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 17 ms. Remains : 15/755 places, 11/1239 transitions.
Finished random walk after 10 steps, including 0 resets, run visited all 2 properties in 1 ms. (steps per millisecond=10 )
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 40 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 31 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1239 transitions.
Computed a total of 83 stabilizing places and 1 stable transitions
Graph (complete) has 1448 edges and 755 vertex of which 673 are kept as prefixes of interest. Removing 82 places using SCC suffix rule.6 ms
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 80 places and 0 transitions.
Iterating post reduction 0 with 80 rules applied. Total rules applied 80 place count 675 transition count 1239
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 95 place count 660 transition count 1209
Iterating global reduction 1 with 15 rules applied. Total rules applied 110 place count 660 transition count 1209
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 117 place count 660 transition count 1202
Applied a total of 117 rules in 42 ms. Remains 660 /755 variables (removed 95) and now considering 1202/1239 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 660/755 places, 1202/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 22 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 22 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 689 transition count 1239
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 76 place count 679 transition count 1219
Iterating global reduction 1 with 10 rules applied. Total rules applied 86 place count 679 transition count 1219
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 91 place count 679 transition count 1214
Applied a total of 91 rules in 34 ms. Remains 679 /755 variables (removed 76) and now considering 1214/1239 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 679/755 places, 1214/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 20 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 20 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1214 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 67 places and 0 transitions.
Iterating post reduction 0 with 67 rules applied. Total rules applied 67 place count 688 transition count 1239
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 81 place count 674 transition count 1211
Iterating global reduction 1 with 14 rules applied. Total rules applied 95 place count 674 transition count 1211
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 101 place count 674 transition count 1205
Applied a total of 101 rules in 39 ms. Remains 674 /755 variables (removed 81) and now considering 1205/1239 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 674/755 places, 1205/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 20 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 22 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1205 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Graph (trivial) has 1233 edges and 755 vertex of which 669 / 755 are part of one of the 128 SCC in 2 ms
Free SCC test removed 541 places
Ensure Unique test removed 1103 transitions
Reduce isomorphic transitions removed 1103 transitions.
Graph (complete) has 345 edges and 214 vertex of which 134 are kept as prefixes of interest. Removing 80 places using SCC suffix rule.1 ms
Discarding 80 places :
Also discarding 0 output transitions
Discarding 126 places :
Symmetric choice reduction at 0 with 126 rule applications. Total rules 128 place count 8 transition count 10
Iterating global reduction 0 with 126 rules applied. Total rules applied 254 place count 8 transition count 10
Applied a total of 254 rules in 9 ms. Remains 8 /755 variables (removed 747) and now considering 10/1239 (removed 1229) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 8/755 places, 10/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 0 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 80 places and 0 transitions.
Iterating post reduction 0 with 80 rules applied. Total rules applied 80 place count 675 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 97 place count 658 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 114 place count 658 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 121 place count 658 transition count 1198
Applied a total of 121 rules in 35 ms. Remains 658 /755 variables (removed 97) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 658/755 places, 1198/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 19 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 20 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 81 places and 0 transitions.
Iterating post reduction 0 with 81 rules applied. Total rules applied 81 place count 674 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 98 place count 657 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 115 place count 657 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 122 place count 657 transition count 1198
Applied a total of 122 rules in 35 ms. Remains 657 /755 variables (removed 98) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 657/755 places, 1198/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 19 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 19 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 73 places and 0 transitions.
Iterating post reduction 0 with 73 rules applied. Total rules applied 73 place count 682 transition count 1239
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 87 place count 668 transition count 1211
Iterating global reduction 1 with 14 rules applied. Total rules applied 101 place count 668 transition count 1211
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 107 place count 668 transition count 1205
Applied a total of 107 rules in 34 ms. Remains 668 /755 variables (removed 87) and now considering 1205/1239 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 668/755 places, 1205/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:54] [INFO ] Input system was already deterministic with 1205 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 79 places and 0 transitions.
Iterating post reduction 0 with 79 rules applied. Total rules applied 79 place count 676 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 96 place count 659 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 113 place count 659 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 120 place count 659 transition count 1198
Applied a total of 120 rules in 23 ms. Remains 659 /755 variables (removed 96) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 659/755 places, 1198/1239 transitions.
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:54] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 78 places and 0 transitions.
Iterating post reduction 0 with 78 rules applied. Total rules applied 78 place count 677 transition count 1239
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 93 place count 662 transition count 1209
Iterating global reduction 1 with 15 rules applied. Total rules applied 108 place count 662 transition count 1209
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 115 place count 662 transition count 1202
Applied a total of 115 rules in 23 ms. Remains 662 /755 variables (removed 93) and now considering 1202/1239 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 662/755 places, 1202/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 17 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 17 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1202 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 76 places and 0 transitions.
Iterating post reduction 0 with 76 rules applied. Total rules applied 76 place count 679 transition count 1239
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 91 place count 664 transition count 1209
Iterating global reduction 1 with 15 rules applied. Total rules applied 106 place count 664 transition count 1209
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 112 place count 664 transition count 1203
Applied a total of 112 rules in 25 ms. Remains 664 /755 variables (removed 91) and now considering 1203/1239 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 664/755 places, 1203/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 17 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1203 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 79 places and 0 transitions.
Iterating post reduction 0 with 79 rules applied. Total rules applied 79 place count 676 transition count 1239
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 95 place count 660 transition count 1207
Iterating global reduction 1 with 16 rules applied. Total rules applied 111 place count 660 transition count 1207
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 117 place count 660 transition count 1201
Applied a total of 117 rules in 29 ms. Remains 660 /755 variables (removed 95) and now considering 1201/1239 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 660/755 places, 1201/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 17 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1201 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 81 places and 0 transitions.
Iterating post reduction 0 with 81 rules applied. Total rules applied 81 place count 674 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 98 place count 657 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 115 place count 657 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 122 place count 657 transition count 1198
Applied a total of 122 rules in 16 ms. Remains 657 /755 variables (removed 98) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 657/755 places, 1198/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Graph (trivial) has 1197 edges and 755 vertex of which 642 / 755 are part of one of the 125 SCC in 1 ms
Free SCC test removed 517 places
Ensure Unique test removed 1050 transitions
Reduce isomorphic transitions removed 1050 transitions.
Graph (complete) has 398 edges and 238 vertex of which 165 are kept as prefixes of interest. Removing 73 places using SCC suffix rule.1 ms
Discarding 73 places :
Also discarding 0 output transitions
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 10 place count 165 transition count 181
Reduce places removed 8 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 11 rules applied. Total rules applied 21 place count 157 transition count 178
Discarding 120 places :
Symmetric choice reduction at 2 with 120 rule applications. Total rules 141 place count 37 transition count 57
Iterating global reduction 2 with 120 rules applied. Total rules applied 261 place count 37 transition count 57
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 263 place count 37 transition count 55
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 265 place count 36 transition count 54
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 4 with 2 rules applied. Total rules applied 267 place count 36 transition count 52
Applied a total of 267 rules in 14 ms. Remains 36 /755 variables (removed 719) and now considering 52/1239 (removed 1187) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 36/755 places, 52/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 0 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 52 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 80 places and 0 transitions.
Iterating post reduction 0 with 80 rules applied. Total rules applied 80 place count 675 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 97 place count 658 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 114 place count 658 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 121 place count 658 transition count 1198
Applied a total of 121 rules in 16 ms. Remains 658 /755 variables (removed 97) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 658/755 places, 1198/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 78 places and 0 transitions.
Iterating post reduction 0 with 78 rules applied. Total rules applied 78 place count 677 transition count 1239
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 95 place count 660 transition count 1205
Iterating global reduction 1 with 17 rules applied. Total rules applied 112 place count 660 transition count 1205
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 119 place count 660 transition count 1198
Applied a total of 119 rules in 37 ms. Remains 660 /755 variables (removed 95) and now considering 1198/1239 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 660/755 places, 1198/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1198 transitions.
Starting structural reductions in LTL mode, iteration 0 : 755/755 places, 1239/1239 transitions.
Reduce places removed 77 places and 0 transitions.
Iterating post reduction 0 with 77 rules applied. Total rules applied 77 place count 678 transition count 1239
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 93 place count 662 transition count 1207
Iterating global reduction 1 with 16 rules applied. Total rules applied 109 place count 662 transition count 1207
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 116 place count 662 transition count 1200
Applied a total of 116 rules in 19 ms. Remains 662 /755 variables (removed 93) and now considering 1200/1239 (removed 39) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 662/755 places, 1200/1239 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:26:55] [INFO ] Input system was already deterministic with 1200 transitions.
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 18 ms
[2023-03-08 13:26:55] [INFO ] Flatten gal took : 19 ms
[2023-03-08 13:26:55] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-08 13:26:55] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 755 places, 1239 transitions and 2687 arcs took 4 ms.
Total runtime 19996 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCshifumi-PT-5a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA DLCshifumi-PT-5a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-5a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-5a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678283904830

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 13 (type EXCL) for 12 DLCshifumi-PT-5a-CTLFireability-04
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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13 CTL EXCL 5/224 1/32 DLCshifumi-PT-5a-CTLFireability-04 47807 m, 9561 m/sec, 1430941 t fired, .

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13 CTL EXCL 10/224 1/32 DLCshifumi-PT-5a-CTLFireability-04 98518 m, 10142 m/sec, 2932884 t fired, .

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13 CTL EXCL 15/224 2/32 DLCshifumi-PT-5a-CTLFireability-04 150177 m, 10331 m/sec, 4422932 t fired, .

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13 CTL EXCL 20/224 2/32 DLCshifumi-PT-5a-CTLFireability-04 199163 m, 9797 m/sec, 5890694 t fired, .

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13 CTL EXCL 30/224 3/32 DLCshifumi-PT-5a-CTLFireability-04 300400 m, 9875 m/sec, 8855444 t fired, .

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13 CTL EXCL 35/224 3/32 DLCshifumi-PT-5a-CTLFireability-04 348901 m, 9700 m/sec, 10335849 t fired, .

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13 CTL EXCL 40/224 4/32 DLCshifumi-PT-5a-CTLFireability-04 397034 m, 9626 m/sec, 11824162 t fired, .

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13 CTL EXCL 45/224 4/32 DLCshifumi-PT-5a-CTLFireability-04 444353 m, 9463 m/sec, 13309559 t fired, .

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13 CTL EXCL 50/224 5/32 DLCshifumi-PT-5a-CTLFireability-04 492279 m, 9585 m/sec, 14766212 t fired, .

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13 CTL EXCL 15/3373 2/5 DLCshifumi-PT-5a-CTLFireability-04 152871 m, 10240 m/sec, 4499236 t fired, .
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13 CTL EXCL 25/3373 3/5 DLCshifumi-PT-5a-CTLFireability-04 252954 m, 10327 m/sec, 7439044 t fired, .
46 CTL EXCL 25/210 3/32 DLCshifumi-PT-5a-CTLFireability-15 262279 m, 10710 m/sec, 7967957 t fired, .

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13 CTL EXCL 30/3373 3/5 DLCshifumi-PT-5a-CTLFireability-04 301938 m, 9796 m/sec, 8901318 t fired, .
46 CTL EXCL 30/210 3/32 DLCshifumi-PT-5a-CTLFireability-15 312548 m, 10053 m/sec, 9533885 t fired, .

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13 CTL EXCL 35/3373 3/5 DLCshifumi-PT-5a-CTLFireability-04 350200 m, 9652 m/sec, 10376929 t fired, .
46 CTL EXCL 35/210 4/32 DLCshifumi-PT-5a-CTLFireability-15 362519 m, 9994 m/sec, 11124378 t fired, .

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13 CTL EXCL 40/3373 4/5 DLCshifumi-PT-5a-CTLFireability-04 398058 m, 9571 m/sec, 11856079 t fired, .
46 CTL EXCL 40/210 4/32 DLCshifumi-PT-5a-CTLFireability-15 412070 m, 9910 m/sec, 12710106 t fired, .

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13 CTL EXCL 45/3373 4/5 DLCshifumi-PT-5a-CTLFireability-04 445218 m, 9432 m/sec, 13334302 t fired, .
46 CTL EXCL 45/210 4/32 DLCshifumi-PT-5a-CTLFireability-15 461310 m, 9848 m/sec, 14286302 t fired, .

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13 CTL EXCL 50/3373 5/5 DLCshifumi-PT-5a-CTLFireability-04 492700 m, 9496 m/sec, 14778880 t fired, .
46 CTL EXCL 50/210 5/32 DLCshifumi-PT-5a-CTLFireability-15 510651 m, 9868 m/sec, 15840395 t fired, .

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13 CTL EXCL 55/3373 5/5 DLCshifumi-PT-5a-CTLFireability-04 539928 m, 9445 m/sec, 16249887 t fired, .
46 CTL EXCL 55/210 5/32 DLCshifumi-PT-5a-CTLFireability-15 559931 m, 9856 m/sec, 17422699 t fired, .

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46 CTL EXCL 60/210 6/32 DLCshifumi-PT-5a-CTLFireability-15 611884 m, 10390 m/sec, 18998699 t fired, .

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46 CTL EXCL 70/224 7/32 DLCshifumi-PT-5a-CTLFireability-15 717088 m, 10179 m/sec, 22153552 t fired, .

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46 CTL EXCL 75/224 7/32 DLCshifumi-PT-5a-CTLFireability-15 772119 m, 11006 m/sec, 23747456 t fired, .

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46 CTL EXCL 80/224 8/32 DLCshifumi-PT-5a-CTLFireability-15 823913 m, 10358 m/sec, 25315540 t fired, .

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46 CTL EXCL 85/224 8/32 DLCshifumi-PT-5a-CTLFireability-15 876773 m, 10572 m/sec, 26889730 t fired, .

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DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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46 CTL EXCL 220/224 20/32 DLCshifumi-PT-5a-CTLFireability-15 2259834 m, 10252 m/sec, 69304885 t fired, .

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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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46 CTL EXCL 5/224 1/5 DLCshifumi-PT-5a-CTLFireability-15 52257 m, -441515 m/sec, 1616484 t fired, .

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DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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46 CTL EXCL 10/224 1/5 DLCshifumi-PT-5a-CTLFireability-15 105247 m, 10598 m/sec, 3228894 t fired, .

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DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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46 CTL EXCL 15/224 2/5 DLCshifumi-PT-5a-CTLFireability-15 158817 m, 10714 m/sec, 4832163 t fired, .

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46 CTL EXCL 20/224 2/5 DLCshifumi-PT-5a-CTLFireability-15 209881 m, 10212 m/sec, 6410331 t fired, .

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46 CTL EXCL 25/224 3/5 DLCshifumi-PT-5a-CTLFireability-15 263394 m, 10702 m/sec, 8002147 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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46 CTL EXCL 30/224 3/5 DLCshifumi-PT-5a-CTLFireability-15 314272 m, 10175 m/sec, 9585950 t fired, .

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46 CTL EXCL 35/224 4/5 DLCshifumi-PT-5a-CTLFireability-15 364360 m, 10017 m/sec, 11184597 t fired, .

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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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46 CTL EXCL 40/224 4/5 DLCshifumi-PT-5a-CTLFireability-15 414138 m, 9955 m/sec, 12777585 t fired, .

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46 CTL EXCL 45/224 4/5 DLCshifumi-PT-5a-CTLFireability-15 463496 m, 9871 m/sec, 14356070 t fired, .

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46 CTL EXCL 50/224 5/5 DLCshifumi-PT-5a-CTLFireability-15 513363 m, 9973 m/sec, 15927064 t fired, .

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46 CTL EXCL 55/224 5/5 DLCshifumi-PT-5a-CTLFireability-15 562669 m, 9861 m/sec, 17509598 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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40 CTL EXCL 5/237 1/32 DLCshifumi-PT-5a-CTLFireability-13 44339 m, 8867 m/sec, 1374265 t fired, .

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40 CTL EXCL 15/237 2/32 DLCshifumi-PT-5a-CTLFireability-13 133556 m, 9056 m/sec, 4064929 t fired, .

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40 CTL EXCL 20/237 2/32 DLCshifumi-PT-5a-CTLFireability-13 176955 m, 8679 m/sec, 5394952 t fired, .

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40 CTL EXCL 25/237 2/32 DLCshifumi-PT-5a-CTLFireability-13 220794 m, 8767 m/sec, 6731050 t fired, .

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40 CTL EXCL 30/237 3/32 DLCshifumi-PT-5a-CTLFireability-13 265519 m, 8945 m/sec, 8067369 t fired, .

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40 CTL EXCL 40/237 3/32 DLCshifumi-PT-5a-CTLFireability-13 350727 m, 8511 m/sec, 10744284 t fired, .

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40 CTL EXCL 45/237 4/32 DLCshifumi-PT-5a-CTLFireability-13 392924 m, 8439 m/sec, 12090046 t fired, .

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40 CTL EXCL 50/237 4/32 DLCshifumi-PT-5a-CTLFireability-13 434551 m, 8325 m/sec, 13438524 t fired, .

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40 CTL EXCL 55/237 5/32 DLCshifumi-PT-5a-CTLFireability-13 476822 m, 8454 m/sec, 14769441 t fired, .

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40 CTL EXCL 60/237 5/32 DLCshifumi-PT-5a-CTLFireability-13 518730 m, 8381 m/sec, 16103087 t fired, .

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40 CTL EXCL 65/237 5/32 DLCshifumi-PT-5a-CTLFireability-13 560627 m, 8379 m/sec, 17444112 t fired, .

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40 CTL EXCL 70/237 6/32 DLCshifumi-PT-5a-CTLFireability-13 604418 m, 8758 m/sec, 18774806 t fired, .

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40 CTL EXCL 75/237 6/32 DLCshifumi-PT-5a-CTLFireability-13 649852 m, 9086 m/sec, 20110728 t fired, .

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40 CTL EXCL 80/237 6/32 DLCshifumi-PT-5a-CTLFireability-13 693717 m, 8773 m/sec, 21435335 t fired, .

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40 CTL EXCL 85/237 7/32 DLCshifumi-PT-5a-CTLFireability-13 738326 m, 8921 m/sec, 22766133 t fired, .

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40 CTL EXCL 90/237 7/32 DLCshifumi-PT-5a-CTLFireability-13 783852 m, 9105 m/sec, 24094319 t fired, .

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40 CTL EXCL 95/237 8/32 DLCshifumi-PT-5a-CTLFireability-13 827428 m, 8715 m/sec, 25416806 t fired, .

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40 CTL EXCL 100/237 8/32 DLCshifumi-PT-5a-CTLFireability-13 871826 m, 8879 m/sec, 26741900 t fired, .

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40 CTL EXCL 105/237 8/32 DLCshifumi-PT-5a-CTLFireability-13 914719 m, 8578 m/sec, 28058899 t fired, .

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40 CTL EXCL 110/237 9/32 DLCshifumi-PT-5a-CTLFireability-13 956933 m, 8442 m/sec, 29373573 t fired, .

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40 CTL EXCL 115/237 9/32 DLCshifumi-PT-5a-CTLFireability-13 998340 m, 8281 m/sec, 30680711 t fired, .

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40 CTL EXCL 120/237 9/32 DLCshifumi-PT-5a-CTLFireability-13 1044125 m, 9157 m/sec, 32018539 t fired, .

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40 CTL EXCL 125/237 10/32 DLCshifumi-PT-5a-CTLFireability-13 1088633 m, 8901 m/sec, 33346274 t fired, .

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40 CTL EXCL 130/237 10/32 DLCshifumi-PT-5a-CTLFireability-13 1133547 m, 8982 m/sec, 34680604 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 135/237 11/32 DLCshifumi-PT-5a-CTLFireability-13 1179100 m, 9110 m/sec, 36011495 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 140/237 11/32 DLCshifumi-PT-5a-CTLFireability-13 1222380 m, 8656 m/sec, 37332911 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 145/237 11/32 DLCshifumi-PT-5a-CTLFireability-13 1265793 m, 8682 m/sec, 38651455 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 150/237 12/32 DLCshifumi-PT-5a-CTLFireability-13 1310509 m, 8943 m/sec, 39976010 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 155/237 12/32 DLCshifumi-PT-5a-CTLFireability-13 1353772 m, 8652 m/sec, 41300653 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 160/237 12/32 DLCshifumi-PT-5a-CTLFireability-13 1395816 m, 8408 m/sec, 42615750 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 165/237 13/32 DLCshifumi-PT-5a-CTLFireability-13 1437807 m, 8398 m/sec, 43937493 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 170/237 13/32 DLCshifumi-PT-5a-CTLFireability-13 1478950 m, 8228 m/sec, 45266163 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 175/237 13/32 DLCshifumi-PT-5a-CTLFireability-13 1519897 m, 8189 m/sec, 46601089 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 180/237 14/32 DLCshifumi-PT-5a-CTLFireability-13 1560654 m, 8151 m/sec, 47935968 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 185/237 14/32 DLCshifumi-PT-5a-CTLFireability-13 1601833 m, 8235 m/sec, 49268955 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 190/237 14/32 DLCshifumi-PT-5a-CTLFireability-13 1642819 m, 8197 m/sec, 50598744 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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DLCshifumi-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 195/237 15/32 DLCshifumi-PT-5a-CTLFireability-13 1685546 m, 8545 m/sec, 51925850 t fired, .

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40 CTL EXCL 200/237 15/32 DLCshifumi-PT-5a-CTLFireability-13 1726903 m, 8271 m/sec, 53255582 t fired, .

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40 CTL EXCL 205/237 16/32 DLCshifumi-PT-5a-CTLFireability-13 1767655 m, 8150 m/sec, 54576675 t fired, .

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40 CTL EXCL 210/237 16/32 DLCshifumi-PT-5a-CTLFireability-13 1808348 m, 8138 m/sec, 55902522 t fired, .

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40 CTL EXCL 215/237 16/32 DLCshifumi-PT-5a-CTLFireability-13 1848941 m, 8118 m/sec, 57231878 t fired, .

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40 CTL EXCL 225/237 17/32 DLCshifumi-PT-5a-CTLFireability-13 1934156 m, 8743 m/sec, 59884613 t fired, .

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40 CTL EXCL 235/237 18/32 DLCshifumi-PT-5a-CTLFireability-13 2028201 m, 9452 m/sec, 62539218 t fired, .

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34 CTL EXCL 5/237 1/32 DLCshifumi-PT-5a-CTLFireability-11 111933 m, 22386 m/sec, 1598422 t fired, .
40 CTL EXCL 5/2848 1/5 DLCshifumi-PT-5a-CTLFireability-13 45034 m, -396633 m/sec, 1395407 t fired, .

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34 CTL EXCL 10/237 3/32 DLCshifumi-PT-5a-CTLFireability-11 237275 m, 25068 m/sec, 3193683 t fired, .
40 CTL EXCL 10/219 1/5 DLCshifumi-PT-5a-CTLFireability-13 89017 m, 8796 m/sec, 2742739 t fired, .

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34 CTL EXCL 15/237 4/32 DLCshifumi-PT-5a-CTLFireability-11 362562 m, 25057 m/sec, 4786766 t fired, .
40 CTL EXCL 15/219 2/5 DLCshifumi-PT-5a-CTLFireability-13 134256 m, 9047 m/sec, 4086259 t fired, .

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34 CTL EXCL 20/237 5/32 DLCshifumi-PT-5a-CTLFireability-11 493605 m, 26208 m/sec, 6365398 t fired, .
40 CTL EXCL 20/219 2/5 DLCshifumi-PT-5a-CTLFireability-13 177529 m, 8654 m/sec, 5413374 t fired, .

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DLCshifumi-PT-5a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/237 6/32 DLCshifumi-PT-5a-CTLFireability-11 622122 m, 25703 m/sec, 7950968 t fired, .
40 CTL EXCL 25/219 2/5 DLCshifumi-PT-5a-CTLFireability-13 221365 m, 8767 m/sec, 6748629 t fired, .

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DLCshifumi-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/237 7/32 DLCshifumi-PT-5a-CTLFireability-11 760344 m, 27644 m/sec, 9515335 t fired, .
40 CTL EXCL 30/219 3/5 DLCshifumi-PT-5a-CTLFireability-13 265907 m, 8908 m/sec, 8079153 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/237 8/32 DLCshifumi-PT-5a-CTLFireability-11 902715 m, 28474 m/sec, 11090495 t fired, .
40 CTL EXCL 35/219 3/5 DLCshifumi-PT-5a-CTLFireability-13 308619 m, 8542 m/sec, 9415135 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/237 10/32 DLCshifumi-PT-5a-CTLFireability-11 1038371 m, 27131 m/sec, 12660479 t fired, .
40 CTL EXCL 40/219 3/5 DLCshifumi-PT-5a-CTLFireability-13 350850 m, 8446 m/sec, 10748170 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/237 11/32 DLCshifumi-PT-5a-CTLFireability-11 1166139 m, 25553 m/sec, 14248529 t fired, .
40 CTL EXCL 45/219 4/5 DLCshifumi-PT-5a-CTLFireability-13 392789 m, 8387 m/sec, 12085527 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/237 12/32 DLCshifumi-PT-5a-CTLFireability-11 1306648 m, 28101 m/sec, 15813385 t fired, .
40 CTL EXCL 50/219 4/5 DLCshifumi-PT-5a-CTLFireability-13 434235 m, 8289 m/sec, 13428124 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 55/237 13/32 DLCshifumi-PT-5a-CTLFireability-11 1446991 m, 28068 m/sec, 17376594 t fired, .
40 CTL EXCL 55/219 5/5 DLCshifumi-PT-5a-CTLFireability-13 476290 m, 8411 m/sec, 14752595 t fired, .

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DLCshifumi-PT-5a-CTLFireability-08: F 0 1 0 0 1 0 0 0
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DLCshifumi-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 60/237 14/32 DLCshifumi-PT-5a-CTLFireability-11 1589970 m, 28595 m/sec, 18937704 t fired, .
40 CTL EXCL 60/219 5/5 DLCshifumi-PT-5a-CTLFireability-13 517941 m, 8330 m/sec, 16077891 t fired, .

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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 65/237 16/32 DLCshifumi-PT-5a-CTLFireability-11 1725768 m, 27159 m/sec, 20513434 t fired, .
40 CTL EXCL 65/219 5/5 DLCshifumi-PT-5a-CTLFireability-13 559579 m, 8327 m/sec, 17412320 t fired, .

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DLCshifumi-PT-5a-CTLFireability-14: CTL true CTL model checker

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DLCshifumi-PT-5a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 71/237 17/32 DLCshifumi-PT-5a-CTLFireability-11 1874421 m, 29730 m/sec, 22061303 t fired, .

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34 CTL EXCL 76/237 18/32 DLCshifumi-PT-5a-CTLFireability-11 2008171 m, 26750 m/sec, 23651018 t fired, .

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DLCshifumi-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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34 CTL EXCL 81/237 19/32 DLCshifumi-PT-5a-CTLFireability-11 2143444 m, 27054 m/sec, 25271774 t fired, .

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1 CTL EXCL 10/478 1/32 DLCshifumi-PT-5a-CTLFireability-00 75171 m, 4796 m/sec, 2309690 t fired, .

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1 CTL EXCL 15/478 2/32 DLCshifumi-PT-5a-CTLFireability-00 127300 m, 10425 m/sec, 3878213 t fired, .

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1 CTL EXCL 20/478 2/32 DLCshifumi-PT-5a-CTLFireability-00 176978 m, 9935 m/sec, 5395622 t fired, .

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1 CTL EXCL 25/478 2/32 DLCshifumi-PT-5a-CTLFireability-00 227794 m, 10163 m/sec, 6944897 t fired, .

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1 CTL EXCL 55/478 5/32 DLCshifumi-PT-5a-CTLFireability-00 516980 m, 9683 m/sec, 16046126 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 472 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml