Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478800826.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCshifumi-PT-4a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478800826
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.3M
-rw-r--r-- 1 mcc users 6.0K Feb 26 08:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 26 08:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 08:05 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 26 08:05 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 15:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.5K Feb 26 09:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 26 09:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.7K Feb 26 08:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 26 08:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.9M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-00
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-01
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-02
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-03
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-04
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-05
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-06
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-07
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-08
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-09
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-10
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-11
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-12
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-13
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-14
FORMULA_NAME DLCshifumi-PT-4a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678281053977

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCshifumi-PT-4a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 13:10:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 13:10:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 13:10:55] [INFO ] Load time of PNML (sax parser for PT used): 242 ms
[2023-03-08 13:10:55] [INFO ] Transformed 1178 places.
[2023-03-08 13:10:55] [INFO ] Transformed 7504 transitions.
[2023-03-08 13:10:55] [INFO ] Found NUPN structural information;
[2023-03-08 13:10:55] [INFO ] Parsed PT model containing 1178 places and 7504 transitions and 28610 arcs in 481 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 26 ms.
Ensure Unique test removed 924 transitions
Reduce redundant transitions removed 924 transitions.
Support contains 163 out of 1178 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1178/1178 places, 6580/6580 transitions.
Discarding 136 places :
Symmetric choice reduction at 0 with 136 rule applications. Total rules 136 place count 1042 transition count 5900
Iterating global reduction 0 with 136 rules applied. Total rules applied 272 place count 1042 transition count 5900
Ensure Unique test removed 68 transitions
Reduce isomorphic transitions removed 68 transitions.
Iterating post reduction 0 with 68 rules applied. Total rules applied 340 place count 1042 transition count 5832
Drop transitions removed 2160 transitions
Redundant transition composition rules discarded 2160 transitions
Iterating global reduction 1 with 2160 rules applied. Total rules applied 2500 place count 1042 transition count 3672
Applied a total of 2500 rules in 362 ms. Remains 1042 /1178 variables (removed 136) and now considering 3672/6580 (removed 2908) transitions.
[2023-03-08 13:10:56] [INFO ] Flow matrix only has 612 transitions (discarded 3060 similar events)
// Phase 1: matrix 612 rows 1042 cols
[2023-03-08 13:10:56] [INFO ] Computed 691 place invariants in 22 ms
[2023-03-08 13:10:59] [INFO ] Implicit Places using invariants in 3567 ms returned [430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 441, 442, 444, 446, 448, 449, 450, 452, 453, 454, 455, 458, 459, 460, 461, 462, 463, 464, 466, 468, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, 480, 481, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 494, 496, 497, 498, 499, 500, 501, 503, 504, 506, 507, 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 524, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 541, 542, 544, 545, 546, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 572, 573, 574, 575, 576, 577, 578, 579, 580, 582, 583, 584, 585, 586, 587, 588, 589, 590, 592, 593, 594, 597, 598, 599, 600, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 615, 616, 618, 619, 620, 621, 622, 623, 624, 625, 626, 628, 629, 630, 632, 634, 636, 637, 638, 639, 641, 642, 643, 644, 646, 647, 648, 649, 650, 651, 652, 653, 654, 656, 657, 658, 659, 660, 663, 664, 665, 666, 667, 668, 669, 670, 672, 673, 674, 675, 676, 677, 678, 679, 681, 682, 683, 684, 685, 686, 687, 688, 689, 692, 693, 694, 695, 696, 699, 700, 701, 702, 704, 705, 706, 707, 708, 709, 710, 711, 712, 714, 716, 718, 719, 720, 721, 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, 746, 747, 749, 750, 751, 752, 753, 754, 755, 756, 758, 760, 761, 762, 763, 764, 765, 766, 767, 768, 770, 771, 772, 774, 775, 776, 777, 778, 779, 780, 781, 782, 783, 784, 785, 786, 787, 788, 789, 791, 792, 793, 794, 795, 796, 797, 798, 799, 800, 801, 802, 803, 804, 806, 807, 808, 809, 810, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 826, 827, 828, 829, 830, 831, 832, 833, 834, 835, 836, 838, 840, 841, 842, 843, 844, 846, 847, 848, 849, 850, 851, 852, 853, 854, 855, 856, 857, 858, 859, 861, 862, 863, 865, 866, 867, 868, 869, 870, 872, 873, 874, 876, 877, 878, 879, 881, 882, 883, 884, 885, 887, 888, 889, 890, 891, 892, 894, 895, 896, 897, 898, 899, 900, 901, 902, 903, 905, 907, 908, 909, 910, 911, 912, 913, 914, 917, 918, 920, 921, 922, 923, 926, 927, 928, 929, 930, 931, 933, 934, 935, 936, 937, 938, 939, 940, 942, 943, 944, 945, 946, 947, 949, 950, 951, 952, 953, 954, 955, 956, 958, 959, 960, 961, 962, 963, 964, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 976, 977, 979, 980, 981, 982, 983, 984, 986, 988, 989, 990, 991, 992, 993, 994, 996, 997, 998, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1008, 1010, 1012, 1014, 1015, 1016, 1018, 1019, 1020, 1021, 1022, 1023, 1024, 1025, 1026, 1027, 1028, 1030, 1032, 1033, 1034, 1036, 1037, 1038, 1039, 1041]
Discarding 521 places :
Ensure Unique test removed 2318 transitions
Reduce isomorphic transitions removed 2318 transitions.
Implicit Place search using SMT only with invariants took 3612 ms to find 521 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 521/1178 places, 1354/6580 transitions.
Drop transitions removed 555 transitions
Redundant transition composition rules discarded 555 transitions
Iterating global reduction 0 with 555 rules applied. Total rules applied 555 place count 521 transition count 799
Applied a total of 555 rules in 29 ms. Remains 521 /521 variables (removed 0) and now considering 799/1354 (removed 555) transitions.
[2023-03-08 13:11:00] [INFO ] Flow matrix only has 612 transitions (discarded 187 similar events)
// Phase 1: matrix 612 rows 521 cols
[2023-03-08 13:11:00] [INFO ] Computed 170 place invariants in 4 ms
[2023-03-08 13:11:00] [INFO ] Implicit Places using invariants in 387 ms returned []
[2023-03-08 13:11:00] [INFO ] Flow matrix only has 612 transitions (discarded 187 similar events)
[2023-03-08 13:11:00] [INFO ] Invariant cache hit.
[2023-03-08 13:11:00] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 13:11:00] [INFO ] Implicit Places using invariants and state equation in 217 ms returned []
Implicit Place search using SMT with State Equation took 605 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 521/1178 places, 799/6580 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 4609 ms. Remains : 521/1178 places, 799/6580 transitions.
Support contains 163 out of 521 places after structural reductions.
[2023-03-08 13:11:00] [INFO ] Flatten gal took : 78 ms
[2023-03-08 13:11:00] [INFO ] Flatten gal took : 40 ms
[2023-03-08 13:11:01] [INFO ] Input system was already deterministic with 799 transitions.
Support contains 160 out of 521 places (down from 163) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 442 ms. (steps per millisecond=22 ) properties (out of 94) seen :92
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-08 13:11:01] [INFO ] Flow matrix only has 612 transitions (discarded 187 similar events)
[2023-03-08 13:11:01] [INFO ] Invariant cache hit.
[2023-03-08 13:11:01] [INFO ] [Real]Absence check using 170 positive place invariants in 28 ms returned sat
[2023-03-08 13:11:01] [INFO ] After 145ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 13:11:01] [INFO ] [Nat]Absence check using 170 positive place invariants in 25 ms returned sat
[2023-03-08 13:11:02] [INFO ] After 177ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-08 13:11:02] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 13:11:02] [INFO ] After 31ms SMT Verify possible using 1 Read/Feed constraints in natural domain returned unsat :1 sat :1
[2023-03-08 13:11:02] [INFO ] After 76ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 33 ms.
[2023-03-08 13:11:02] [INFO ] After 412ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 5 ms.
Support contains 2 out of 521 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 521/521 places, 799/799 transitions.
Graph (trivial) has 795 edges and 521 vertex of which 427 / 521 are part of one of the 79 SCC in 4 ms
Free SCC test removed 348 places
Drop transitions removed 795 transitions
Reduce isomorphic transitions removed 795 transitions.
Graph (complete) has 173 edges and 173 vertex of which 5 are kept as prefixes of interest. Removing 168 places using SCC suffix rule.0 ms
Discarding 168 places :
Also discarding 0 output transitions
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 2 place count 5 transition count 3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 4 place count 4 transition count 3
Applied a total of 4 rules in 10 ms. Remains 4 /521 variables (removed 517) and now considering 3/799 (removed 796) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 10 ms. Remains : 4/521 places, 3/799 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=1 )
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 31 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 29 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 799 transitions.
Computed a total of 92 stabilizing places and 1 stable transitions
Graph (complete) has 968 edges and 521 vertex of which 430 are kept as prefixes of interest. Removing 91 places using SCC suffix rule.4 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Graph (trivial) has 791 edges and 521 vertex of which 422 / 521 are part of one of the 79 SCC in 4 ms
Free SCC test removed 343 places
Ensure Unique test removed 707 transitions
Reduce isomorphic transitions removed 707 transitions.
Graph (complete) has 261 edges and 178 vertex of which 88 are kept as prefixes of interest. Removing 90 places using SCC suffix rule.0 ms
Discarding 90 places :
Also discarding 0 output transitions
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 88 transition count 91
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 87 transition count 91
Discarding 75 places :
Symmetric choice reduction at 2 with 75 rule applications. Total rules 79 place count 12 transition count 16
Iterating global reduction 2 with 75 rules applied. Total rules applied 154 place count 12 transition count 16
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 155 place count 12 transition count 15
Applied a total of 155 rules in 12 ms. Remains 12 /521 variables (removed 509) and now considering 15/799 (removed 784) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 12/521 places, 15/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 0 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 77 places and 0 transitions.
Iterating post reduction 0 with 77 rules applied. Total rules applied 77 place count 444 transition count 799
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 96 place count 425 transition count 761
Iterating global reduction 1 with 19 rules applied. Total rules applied 115 place count 425 transition count 761
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 122 place count 425 transition count 754
Applied a total of 122 rules in 22 ms. Remains 425 /521 variables (removed 96) and now considering 754/799 (removed 45) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 425/521 places, 754/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 754 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 80 places and 0 transitions.
Iterating post reduction 0 with 80 rules applied. Total rules applied 80 place count 441 transition count 799
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 96 place count 425 transition count 767
Iterating global reduction 1 with 16 rules applied. Total rules applied 112 place count 425 transition count 767
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 118 place count 425 transition count 761
Applied a total of 118 rules in 19 ms. Remains 425 /521 variables (removed 96) and now considering 761/799 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 425/521 places, 761/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 16 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 761 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Graph (trivial) has 763 edges and 521 vertex of which 404 / 521 are part of one of the 77 SCC in 1 ms
Free SCC test removed 327 places
Ensure Unique test removed 667 transitions
Reduce isomorphic transitions removed 667 transitions.
Graph (complete) has 301 edges and 194 vertex of which 110 are kept as prefixes of interest. Removing 84 places using SCC suffix rule.0 ms
Discarding 84 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 110 transition count 131
Reduce places removed 1 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 1 with 5 rules applied. Total rules applied 8 place count 109 transition count 127
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 14 place count 105 transition count 125
Discarding 75 places :
Symmetric choice reduction at 3 with 75 rule applications. Total rules 89 place count 30 transition count 48
Iterating global reduction 3 with 75 rules applied. Total rules applied 164 place count 30 transition count 48
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 165 place count 30 transition count 47
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 166 place count 30 transition count 47
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 167 place count 29 transition count 46
Iterating global reduction 3 with 1 rules applied. Total rules applied 168 place count 29 transition count 46
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 169 place count 29 transition count 45
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 170 place count 29 transition count 44
Applied a total of 170 rules in 12 ms. Remains 29 /521 variables (removed 492) and now considering 44/799 (removed 755) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 29/521 places, 44/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 44 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Graph (trivial) has 795 edges and 521 vertex of which 428 / 521 are part of one of the 79 SCC in 1 ms
Free SCC test removed 349 places
Ensure Unique test removed 716 transitions
Reduce isomorphic transitions removed 716 transitions.
Graph (complete) has 252 edges and 172 vertex of which 82 are kept as prefixes of interest. Removing 90 places using SCC suffix rule.0 ms
Discarding 90 places :
Also discarding 0 output transitions
Discarding 77 places :
Symmetric choice reduction at 0 with 77 rule applications. Total rules 79 place count 5 transition count 6
Iterating global reduction 0 with 77 rules applied. Total rules applied 156 place count 5 transition count 6
Applied a total of 156 rules in 5 ms. Remains 5 /521 variables (removed 516) and now considering 6/799 (removed 793) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 5/521 places, 6/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 0 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 0 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 6 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
FORMULA DLCshifumi-PT-4a-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 87 places and 0 transitions.
Iterating post reduction 0 with 87 rules applied. Total rules applied 87 place count 434 transition count 799
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 107 place count 414 transition count 759
Iterating global reduction 1 with 20 rules applied. Total rules applied 127 place count 414 transition count 759
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 134 place count 414 transition count 752
Applied a total of 134 rules in 19 ms. Remains 414 /521 variables (removed 107) and now considering 752/799 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 19 ms. Remains : 414/521 places, 752/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 13 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 13 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 752 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 82 places and 0 transitions.
Iterating post reduction 0 with 82 rules applied. Total rules applied 82 place count 439 transition count 799
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 100 place count 421 transition count 763
Iterating global reduction 1 with 18 rules applied. Total rules applied 118 place count 421 transition count 763
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 122 place count 421 transition count 759
Applied a total of 122 rules in 15 ms. Remains 421 /521 variables (removed 100) and now considering 759/799 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 421/521 places, 759/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 13 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 13 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 759 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 90 places and 0 transitions.
Iterating post reduction 0 with 90 rules applied. Total rules applied 90 place count 431 transition count 799
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 112 place count 409 transition count 755
Iterating global reduction 1 with 22 rules applied. Total rules applied 134 place count 409 transition count 755
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 141 place count 409 transition count 748
Applied a total of 141 rules in 16 ms. Remains 409 /521 variables (removed 112) and now considering 748/799 (removed 51) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 409/521 places, 748/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 748 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 89 places and 0 transitions.
Iterating post reduction 0 with 89 rules applied. Total rules applied 89 place count 432 transition count 799
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 111 place count 410 transition count 755
Iterating global reduction 1 with 22 rules applied. Total rules applied 133 place count 410 transition count 755
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 140 place count 410 transition count 748
Applied a total of 140 rules in 13 ms. Remains 410 /521 variables (removed 111) and now considering 748/799 (removed 51) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 410/521 places, 748/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 748 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 77 places and 0 transitions.
Iterating post reduction 0 with 77 rules applied. Total rules applied 77 place count 444 transition count 799
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 94 place count 427 transition count 765
Iterating global reduction 1 with 17 rules applied. Total rules applied 111 place count 427 transition count 765
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 117 place count 427 transition count 759
Applied a total of 117 rules in 12 ms. Remains 427 /521 variables (removed 94) and now considering 759/799 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 427/521 places, 759/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 15 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 759 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Graph (trivial) has 789 edges and 521 vertex of which 423 / 521 are part of one of the 78 SCC in 2 ms
Free SCC test removed 345 places
Ensure Unique test removed 708 transitions
Reduce isomorphic transitions removed 708 transitions.
Graph (complete) has 260 edges and 176 vertex of which 87 are kept as prefixes of interest. Removing 89 places using SCC suffix rule.0 ms
Discarding 89 places :
Also discarding 0 output transitions
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 87 transition count 89
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 7 place count 85 transition count 88
Discarding 76 places :
Symmetric choice reduction at 2 with 76 rule applications. Total rules 83 place count 9 transition count 12
Iterating global reduction 2 with 76 rules applied. Total rules applied 159 place count 9 transition count 12
Applied a total of 159 rules in 6 ms. Remains 9 /521 variables (removed 512) and now considering 12/799 (removed 787) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 9/521 places, 12/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 1 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 76 places and 0 transitions.
Iterating post reduction 0 with 76 rules applied. Total rules applied 76 place count 445 transition count 799
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 96 place count 425 transition count 759
Iterating global reduction 1 with 20 rules applied. Total rules applied 116 place count 425 transition count 759
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 123 place count 425 transition count 752
Applied a total of 123 rules in 11 ms. Remains 425 /521 variables (removed 96) and now considering 752/799 (removed 47) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 425/521 places, 752/799 transitions.
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:02] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:02] [INFO ] Input system was already deterministic with 752 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 88 places and 0 transitions.
Iterating post reduction 0 with 88 rules applied. Total rules applied 88 place count 433 transition count 799
Discarding 21 places :
Symmetric choice reduction at 1 with 21 rule applications. Total rules 109 place count 412 transition count 757
Iterating global reduction 1 with 21 rules applied. Total rules applied 130 place count 412 transition count 757
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 137 place count 412 transition count 750
Applied a total of 137 rules in 14 ms. Remains 412 /521 variables (removed 109) and now considering 750/799 (removed 49) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 412/521 places, 750/799 transitions.
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 12 ms
[2023-03-08 13:11:03] [INFO ] Input system was already deterministic with 750 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 87 places and 0 transitions.
Iterating post reduction 0 with 87 rules applied. Total rules applied 87 place count 434 transition count 799
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 107 place count 414 transition count 759
Iterating global reduction 1 with 20 rules applied. Total rules applied 127 place count 414 transition count 759
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 133 place count 414 transition count 753
Applied a total of 133 rules in 11 ms. Remains 414 /521 variables (removed 107) and now considering 753/799 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 414/521 places, 753/799 transitions.
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:03] [INFO ] Input system was already deterministic with 753 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 90 places and 0 transitions.
Iterating post reduction 0 with 90 rules applied. Total rules applied 90 place count 431 transition count 799
Discarding 21 places :
Symmetric choice reduction at 1 with 21 rule applications. Total rules 111 place count 410 transition count 757
Iterating global reduction 1 with 21 rules applied. Total rules applied 132 place count 410 transition count 757
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 139 place count 410 transition count 750
Applied a total of 139 rules in 9 ms. Remains 410 /521 variables (removed 111) and now considering 750/799 (removed 49) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 410/521 places, 750/799 transitions.
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 14 ms
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:03] [INFO ] Input system was already deterministic with 750 transitions.
Starting structural reductions in LTL mode, iteration 0 : 521/521 places, 799/799 transitions.
Reduce places removed 88 places and 0 transitions.
Iterating post reduction 0 with 88 rules applied. Total rules applied 88 place count 433 transition count 799
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 110 place count 411 transition count 755
Iterating global reduction 1 with 22 rules applied. Total rules applied 132 place count 411 transition count 755
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 139 place count 411 transition count 748
Applied a total of 139 rules in 8 ms. Remains 411 /521 variables (removed 110) and now considering 748/799 (removed 51) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 411/521 places, 748/799 transitions.
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 10 ms
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 11 ms
[2023-03-08 13:11:03] [INFO ] Input system was already deterministic with 748 transitions.
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 22 ms
[2023-03-08 13:11:03] [INFO ] Flatten gal took : 19 ms
[2023-03-08 13:11:03] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 11 ms.
[2023-03-08 13:11:03] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 521 places, 799 transitions and 1767 arcs took 3 ms.
Total runtime 8050 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCshifumi-PT-4a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA DLCshifumi-PT-4a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-4a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678282486819

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type SKEL/FNDP) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/EQUN) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 53 (type SKEL/SRCH) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 50 (type FNDP) for DLCshifumi-PT-4a-CTLFireability-00 (obsolete)
lola: CANCELED task # 51 (type EQUN) for DLCshifumi-PT-4a-CTLFireability-00 (obsolete)
lola: FINISHED task # 50 (type SKEL/FNDP) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/375/CTLFireability-51.sara.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.

lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 11 (type EXCL) for 10 DLCshifumi-PT-4a-CTLFireability-02
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type SKEL/EQUN) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: LAUNCH task # 54 (type SKEL/SRCH) for 22 DLCshifumi-PT-4a-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 54 (type SKEL/SRCH) for DLCshifumi-PT-4a-CTLFireability-07
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type FNDP) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type SRCH) for 0 DLCshifumi-PT-4a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type SRCH) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/375/CTLFireability-56.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 55 (type FNDP) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for DLCshifumi-PT-4a-CTLFireability-00 (obsolete)
lola: FINISHED task # 56 (type EQUN) for DLCshifumi-PT-4a-CTLFireability-00
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/257 1/32 DLCshifumi-PT-4a-CTLFireability-02 199793 m, 39958 m/sec, 2266758 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/257 2/32 DLCshifumi-PT-4a-CTLFireability-02 429911 m, 46023 m/sec, 4606981 t fired, .

Time elapsed: 11 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/257 3/32 DLCshifumi-PT-4a-CTLFireability-02 665065 m, 47030 m/sec, 6908547 t fired, .

Time elapsed: 16 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/257 4/32 DLCshifumi-PT-4a-CTLFireability-02 911054 m, 49197 m/sec, 9182853 t fired, .

Time elapsed: 21 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/257 6/32 DLCshifumi-PT-4a-CTLFireability-02 1160684 m, 49926 m/sec, 11447728 t fired, .

Time elapsed: 26 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/257 7/32 DLCshifumi-PT-4a-CTLFireability-02 1410360 m, 49935 m/sec, 13716121 t fired, .

Time elapsed: 31 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 35/257 8/32 DLCshifumi-PT-4a-CTLFireability-02 1665180 m, 50964 m/sec, 15989465 t fired, .

Time elapsed: 36 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 40/257 9/32 DLCshifumi-PT-4a-CTLFireability-02 1906626 m, 48289 m/sec, 18290765 t fired, .

Time elapsed: 41 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 45/257 10/32 DLCshifumi-PT-4a-CTLFireability-02 2166619 m, 51998 m/sec, 20524779 t fired, .

Time elapsed: 46 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 50/257 11/32 DLCshifumi-PT-4a-CTLFireability-02 2413813 m, 49438 m/sec, 22804555 t fired, .

Time elapsed: 51 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 55/257 12/32 DLCshifumi-PT-4a-CTLFireability-02 2679177 m, 53072 m/sec, 25037194 t fired, .

Time elapsed: 56 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 60/257 13/32 DLCshifumi-PT-4a-CTLFireability-02 2940179 m, 52200 m/sec, 27289425 t fired, .

Time elapsed: 61 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 65/257 14/32 DLCshifumi-PT-4a-CTLFireability-02 3179731 m, 47910 m/sec, 29653483 t fired, .

Time elapsed: 66 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 70/257 15/32 DLCshifumi-PT-4a-CTLFireability-02 3437769 m, 51607 m/sec, 31902997 t fired, .

Time elapsed: 71 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 75/257 17/32 DLCshifumi-PT-4a-CTLFireability-02 3706754 m, 53797 m/sec, 34150137 t fired, .

Time elapsed: 76 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 80/257 18/32 DLCshifumi-PT-4a-CTLFireability-02 3972825 m, 53214 m/sec, 36405539 t fired, .

Time elapsed: 81 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 85/257 19/32 DLCshifumi-PT-4a-CTLFireability-02 4227853 m, 51005 m/sec, 38684326 t fired, .

Time elapsed: 86 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 90/257 20/32 DLCshifumi-PT-4a-CTLFireability-02 4500783 m, 54586 m/sec, 40933650 t fired, .

Time elapsed: 91 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 95/257 21/32 DLCshifumi-PT-4a-CTLFireability-02 4777841 m, 55411 m/sec, 43187103 t fired, .

Time elapsed: 96 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 100/257 23/32 DLCshifumi-PT-4a-CTLFireability-02 5048594 m, 54150 m/sec, 45444709 t fired, .

Time elapsed: 101 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 105/257 24/32 DLCshifumi-PT-4a-CTLFireability-02 5327817 m, 55844 m/sec, 47726983 t fired, .

Time elapsed: 106 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 110/257 25/32 DLCshifumi-PT-4a-CTLFireability-02 5608670 m, 56170 m/sec, 50002713 t fired, .

Time elapsed: 111 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 115/257 26/32 DLCshifumi-PT-4a-CTLFireability-02 5888577 m, 55981 m/sec, 52212788 t fired, .

Time elapsed: 116 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 120/257 27/32 DLCshifumi-PT-4a-CTLFireability-02 6170558 m, 56396 m/sec, 54425734 t fired, .

Time elapsed: 121 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 125/257 29/32 DLCshifumi-PT-4a-CTLFireability-02 6447563 m, 55401 m/sec, 56643706 t fired, .

Time elapsed: 126 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 130/257 30/32 DLCshifumi-PT-4a-CTLFireability-02 6707185 m, 51924 m/sec, 58916100 t fired, .

Time elapsed: 131 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 135/257 31/32 DLCshifumi-PT-4a-CTLFireability-02 6980700 m, 54703 m/sec, 61155836 t fired, .

Time elapsed: 136 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 140/257 32/32 DLCshifumi-PT-4a-CTLFireability-02 7261408 m, 56141 m/sec, 63385815 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 11 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 47 (type EXCL) for 46 DLCshifumi-PT-4a-CTLFireability-15
lola: time limit : 265 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-15
lola: result : false
lola: markings : 1
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 DLCshifumi-PT-4a-CTLFireability-14
lola: time limit : 287 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-14
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 DLCshifumi-PT-4a-CTLFireability-13
lola: time limit : 314 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 DLCshifumi-PT-4a-CTLFireability-12
lola: time limit : 345 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/345 1/32 DLCshifumi-PT-4a-CTLFireability-12 225924 m, 45184 m/sec, 2295239 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/345 3/32 DLCshifumi-PT-4a-CTLFireability-12 479456 m, 50706 m/sec, 4595497 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/345 4/32 DLCshifumi-PT-4a-CTLFireability-12 736982 m, 51505 m/sec, 6844994 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/345 5/32 DLCshifumi-PT-4a-CTLFireability-12 1010944 m, 54792 m/sec, 9115474 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/345 6/32 DLCshifumi-PT-4a-CTLFireability-12 1291960 m, 56203 m/sec, 11360287 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/345 7/32 DLCshifumi-PT-4a-CTLFireability-12 1583244 m, 58256 m/sec, 13609598 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/345 8/32 DLCshifumi-PT-4a-CTLFireability-12 1850821 m, 53515 m/sec, 15934373 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/345 10/32 DLCshifumi-PT-4a-CTLFireability-12 2142936 m, 58423 m/sec, 18185129 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 45/345 11/32 DLCshifumi-PT-4a-CTLFireability-12 2418229 m, 55058 m/sec, 20424394 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/345 12/32 DLCshifumi-PT-4a-CTLFireability-12 2713368 m, 59027 m/sec, 22619263 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 55/345 13/32 DLCshifumi-PT-4a-CTLFireability-12 2996234 m, 56573 m/sec, 24900562 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 60/345 15/32 DLCshifumi-PT-4a-CTLFireability-12 3264541 m, 53661 m/sec, 27179604 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 65/345 16/32 DLCshifumi-PT-4a-CTLFireability-12 3563771 m, 59846 m/sec, 29383062 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 70/345 17/32 DLCshifumi-PT-4a-CTLFireability-12 3872063 m, 61658 m/sec, 31593983 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 75/345 18/32 DLCshifumi-PT-4a-CTLFireability-12 4149554 m, 55498 m/sec, 33877161 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 80/345 20/32 DLCshifumi-PT-4a-CTLFireability-12 4459123 m, 61913 m/sec, 36105560 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 85/345 21/32 DLCshifumi-PT-4a-CTLFireability-12 4765900 m, 61355 m/sec, 38318973 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 90/345 22/32 DLCshifumi-PT-4a-CTLFireability-12 5066926 m, 60205 m/sec, 40543407 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 95/345 24/32 DLCshifumi-PT-4a-CTLFireability-12 5374043 m, 61423 m/sec, 42748016 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 100/345 25/32 DLCshifumi-PT-4a-CTLFireability-12 5688658 m, 62923 m/sec, 44935856 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 105/345 26/32 DLCshifumi-PT-4a-CTLFireability-12 6006628 m, 63594 m/sec, 47118117 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 110/345 28/32 DLCshifumi-PT-4a-CTLFireability-12 6326279 m, 63930 m/sec, 49291262 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 115/345 29/32 DLCshifumi-PT-4a-CTLFireability-12 6618841 m, 58512 m/sec, 51547136 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 120/345 30/32 DLCshifumi-PT-4a-CTLFireability-12 6928410 m, 61913 m/sec, 53783770 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 125/345 32/32 DLCshifumi-PT-4a-CTLFireability-12 7241922 m, 62702 m/sec, 55990781 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 38 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 35 (type EXCL) for 34 DLCshifumi-PT-4a-CTLFireability-11
lola: time limit : 369 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/369 2/32 DLCshifumi-PT-4a-CTLFireability-11 232594 m, 46518 m/sec, 2354494 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/369 3/32 DLCshifumi-PT-4a-CTLFireability-11 486338 m, 50748 m/sec, 4650224 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/369 4/32 DLCshifumi-PT-4a-CTLFireability-11 748203 m, 52373 m/sec, 6945419 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/369 5/32 DLCshifumi-PT-4a-CTLFireability-11 1025007 m, 55360 m/sec, 9223774 t fired, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/369 6/32 DLCshifumi-PT-4a-CTLFireability-11 1305633 m, 56125 m/sec, 11483681 t fired, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/369 7/32 DLCshifumi-PT-4a-CTLFireability-11 1597674 m, 58408 m/sec, 13718987 t fired, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/369 9/32 DLCshifumi-PT-4a-CTLFireability-11 1861195 m, 52704 m/sec, 16023225 t fired, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/369 10/32 DLCshifumi-PT-4a-CTLFireability-11 2151991 m, 58159 m/sec, 18249380 t fired, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/369 11/32 DLCshifumi-PT-4a-CTLFireability-11 2430825 m, 55766 m/sec, 20516241 t fired, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/369 12/32 DLCshifumi-PT-4a-CTLFireability-11 2729399 m, 59714 m/sec, 22732121 t fired, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/369 14/32 DLCshifumi-PT-4a-CTLFireability-11 3007018 m, 55523 m/sec, 25001366 t fired, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 60/369 15/32 DLCshifumi-PT-4a-CTLFireability-11 3278857 m, 54367 m/sec, 27294181 t fired, .

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 65/369 16/32 DLCshifumi-PT-4a-CTLFireability-11 3586107 m, 61450 m/sec, 29535783 t fired, .

Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 70/369 17/32 DLCshifumi-PT-4a-CTLFireability-11 3893458 m, 61470 m/sec, 31788490 t fired, .

Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 75/369 19/32 DLCshifumi-PT-4a-CTLFireability-11 4177835 m, 56875 m/sec, 34086943 t fired, .

Time elapsed: 351 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 80/369 20/32 DLCshifumi-PT-4a-CTLFireability-11 4483384 m, 61109 m/sec, 36290910 t fired, .

Time elapsed: 356 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 85/369 21/32 DLCshifumi-PT-4a-CTLFireability-11 4790254 m, 61374 m/sec, 38499345 t fired, .

Time elapsed: 361 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 90/369 23/32 DLCshifumi-PT-4a-CTLFireability-11 5089893 m, 59927 m/sec, 40718952 t fired, .

Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 95/369 24/32 DLCshifumi-PT-4a-CTLFireability-11 5396429 m, 61307 m/sec, 42923509 t fired, .

Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 100/369 25/32 DLCshifumi-PT-4a-CTLFireability-11 5716289 m, 63972 m/sec, 45124031 t fired, .

Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 105/369 27/32 DLCshifumi-PT-4a-CTLFireability-11 6038102 m, 64362 m/sec, 47336131 t fired, .

Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 110/369 28/32 DLCshifumi-PT-4a-CTLFireability-11 6360649 m, 64509 m/sec, 49528996 t fired, .

Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 115/369 30/32 DLCshifumi-PT-4a-CTLFireability-11 6653039 m, 58478 m/sec, 51812900 t fired, .

Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 120/369 31/32 DLCshifumi-PT-4a-CTLFireability-11 6962830 m, 61958 m/sec, 54040844 t fired, .

Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 125/369 32/32 DLCshifumi-PT-4a-CTLFireability-11 7278453 m, 63124 m/sec, 56246778 t fired, .

Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 35 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 29 (type EXCL) for 28 DLCshifumi-PT-4a-CTLFireability-09
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-09
lola: result : false
lola: markings : 2
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 DLCshifumi-PT-4a-CTLFireability-08
lola: time limit : 456 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-08
lola: result : false
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 DLCshifumi-PT-4a-CTLFireability-07
lola: time limit : 532 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-07
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 DLCshifumi-PT-4a-CTLFireability-06
lola: time limit : 638 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/638 1/32 DLCshifumi-PT-4a-CTLFireability-06 42532 m, 8506 m/sec, 2443457 t fired, .

Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/638 1/32 DLCshifumi-PT-4a-CTLFireability-06 84143 m, 8322 m/sec, 4814098 t fired, .

Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/638 1/32 DLCshifumi-PT-4a-CTLFireability-06 125465 m, 8264 m/sec, 7170685 t fired, .

Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/638 1/32 DLCshifumi-PT-4a-CTLFireability-06 166215 m, 8150 m/sec, 9535777 t fired, .

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/638 1/32 DLCshifumi-PT-4a-CTLFireability-06 207257 m, 8208 m/sec, 11883877 t fired, .

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 248367 m, 8222 m/sec, 14220345 t fired, .

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 288354 m, 7997 m/sec, 16526897 t fired, .

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 40/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 327714 m, 7872 m/sec, 18809853 t fired, .

Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 45/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 366616 m, 7780 m/sec, 21085877 t fired, .

Time elapsed: 451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 50/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 406553 m, 7987 m/sec, 23410192 t fired, .

Time elapsed: 456 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 55/638 2/32 DLCshifumi-PT-4a-CTLFireability-06 447755 m, 8240 m/sec, 25765316 t fired, .

Time elapsed: 461 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 60/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 490182 m, 8485 m/sec, 28152618 t fired, .

Time elapsed: 466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 65/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 531747 m, 8313 m/sec, 30508768 t fired, .

Time elapsed: 471 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 70/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 572443 m, 8139 m/sec, 32832985 t fired, .

Time elapsed: 476 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 75/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 612539 m, 8019 m/sec, 35139740 t fired, .

Time elapsed: 481 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 80/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 654523 m, 8396 m/sec, 37505787 t fired, .

Time elapsed: 486 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 85/638 3/32 DLCshifumi-PT-4a-CTLFireability-06 696411 m, 8377 m/sec, 39864108 t fired, .

Time elapsed: 491 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 90/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 737234 m, 8164 m/sec, 42193549 t fired, .

Time elapsed: 496 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 95/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 777646 m, 8082 m/sec, 44505032 t fired, .

Time elapsed: 501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 100/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 817799 m, 8030 m/sec, 46823676 t fired, .

Time elapsed: 506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 105/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 857352 m, 7910 m/sec, 49122987 t fired, .

Time elapsed: 511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 110/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 897438 m, 8017 m/sec, 51446582 t fired, .

Time elapsed: 516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 115/638 4/32 DLCshifumi-PT-4a-CTLFireability-06 937145 m, 7941 m/sec, 53774252 t fired, .

Time elapsed: 521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 120/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 976688 m, 7908 m/sec, 56077014 t fired, .

Time elapsed: 526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 125/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 1016789 m, 8020 m/sec, 58407069 t fired, .

Time elapsed: 531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 130/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 1058848 m, 8411 m/sec, 60783648 t fired, .

Time elapsed: 536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 135/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 1101780 m, 8586 m/sec, 63167143 t fired, .

Time elapsed: 541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 140/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 1143516 m, 8347 m/sec, 65508011 t fired, .

Time elapsed: 546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 145/638 5/32 DLCshifumi-PT-4a-CTLFireability-06 1184950 m, 8286 m/sec, 67835280 t fired, .

Time elapsed: 551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 150/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1226529 m, 8315 m/sec, 70155304 t fired, .

Time elapsed: 556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 155/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1268875 m, 8469 m/sec, 72505684 t fired, .

Time elapsed: 561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 160/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1309656 m, 8156 m/sec, 74810238 t fired, .

Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 165/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1350892 m, 8247 m/sec, 77123674 t fired, .

Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 170/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1391836 m, 8188 m/sec, 79424230 t fired, .

Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 175/638 6/32 DLCshifumi-PT-4a-CTLFireability-06 1432072 m, 8047 m/sec, 81701413 t fired, .

Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 180/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1471477 m, 7881 m/sec, 83961987 t fired, .

Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 185/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1511705 m, 8045 m/sec, 86240509 t fired, .

Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 190/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1552075 m, 8074 m/sec, 88511813 t fired, .

Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 195/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1591925 m, 7970 m/sec, 90766059 t fired, .

Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 200/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1630577 m, 7730 m/sec, 92984826 t fired, .

Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 205/638 7/32 DLCshifumi-PT-4a-CTLFireability-06 1670782 m, 8041 m/sec, 95260217 t fired, .

Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 210/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1709815 m, 7806 m/sec, 97506971 t fired, .

Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 215/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1748984 m, 7833 m/sec, 99739160 t fired, .

Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 220/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1787837 m, 7770 m/sec, 101969985 t fired, .

Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 225/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1826834 m, 7799 m/sec, 104207932 t fired, .

Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 230/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1865302 m, 7693 m/sec, 106419082 t fired, .

Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 235/638 8/32 DLCshifumi-PT-4a-CTLFireability-06 1905555 m, 8050 m/sec, 108700160 t fired, .

Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 240/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 1945941 m, 8077 m/sec, 110990059 t fired, .

Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 245/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 1985133 m, 7838 m/sec, 113245412 t fired, .

Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 250/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 2024739 m, 7921 m/sec, 115518827 t fired, .

Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 255/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 2063622 m, 7776 m/sec, 117760015 t fired, .

Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 260/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 2102401 m, 7755 m/sec, 120001824 t fired, .

Time elapsed: 666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 265/638 9/32 DLCshifumi-PT-4a-CTLFireability-06 2144397 m, 8399 m/sec, 122368146 t fired, .

Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 270/638 10/32 DLCshifumi-PT-4a-CTLFireability-06 2186319 m, 8384 m/sec, 124725134 t fired, .

Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 275/638 10/32 DLCshifumi-PT-4a-CTLFireability-06 2227745 m, 8285 m/sec, 127083875 t fired, .

Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 280/638 10/32 DLCshifumi-PT-4a-CTLFireability-06 2269125 m, 8276 m/sec, 129442901 t fired, .

Time elapsed: 686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 285/638 10/32 DLCshifumi-PT-4a-CTLFireability-06 2311205 m, 8416 m/sec, 131820352 t fired, .

Time elapsed: 691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 290/638 10/32 DLCshifumi-PT-4a-CTLFireability-06 2352998 m, 8358 m/sec, 134171604 t fired, .

Time elapsed: 696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 295/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2394258 m, 8252 m/sec, 136517621 t fired, .

Time elapsed: 701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 300/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2433731 m, 7894 m/sec, 138772980 t fired, .

Time elapsed: 706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 305/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2473227 m, 7899 m/sec, 141030986 t fired, .

Time elapsed: 711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 310/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2513265 m, 8007 m/sec, 143309697 t fired, .

Time elapsed: 716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 315/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2555074 m, 8361 m/sec, 145628151 t fired, .

Time elapsed: 721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 320/638 11/32 DLCshifumi-PT-4a-CTLFireability-06 2596352 m, 8255 m/sec, 147927389 t fired, .

Time elapsed: 726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 325/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2636372 m, 8004 m/sec, 150189817 t fired, .

Time elapsed: 731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 330/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2677944 m, 8314 m/sec, 152495862 t fired, .

Time elapsed: 736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 335/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2719527 m, 8316 m/sec, 154796534 t fired, .

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 340/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2759939 m, 8082 m/sec, 157059240 t fired, .

Time elapsed: 746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 345/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2799359 m, 7884 m/sec, 159287766 t fired, .

Time elapsed: 751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 350/638 12/32 DLCshifumi-PT-4a-CTLFireability-06 2838242 m, 7776 m/sec, 161531854 t fired, .

Time elapsed: 756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 355/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 2877608 m, 7873 m/sec, 163800025 t fired, .

Time elapsed: 761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 360/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 2917456 m, 7969 m/sec, 166075798 t fired, .

Time elapsed: 766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 365/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 2956585 m, 7825 m/sec, 168330213 t fired, .

Time elapsed: 771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 371/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 2995611 m, 7805 m/sec, 170581476 t fired, .

Time elapsed: 777 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 376/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 3035181 m, 7914 m/sec, 172843856 t fired, .

Time elapsed: 782 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 381/638 13/32 DLCshifumi-PT-4a-CTLFireability-06 3074427 m, 7849 m/sec, 175099303 t fired, .

Time elapsed: 787 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 386/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3113756 m, 7865 m/sec, 177372867 t fired, .

Time elapsed: 792 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 391/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3153111 m, 7871 m/sec, 179667047 t fired, .

Time elapsed: 797 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 396/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3193150 m, 8007 m/sec, 181958292 t fired, .

Time elapsed: 802 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 401/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3233171 m, 8004 m/sec, 184247356 t fired, .

Time elapsed: 807 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 406/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3273946 m, 8155 m/sec, 186548356 t fired, .

Time elapsed: 812 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 411/638 14/32 DLCshifumi-PT-4a-CTLFireability-06 3314297 m, 8070 m/sec, 188835432 t fired, .

Time elapsed: 817 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 416/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3354097 m, 7960 m/sec, 191100625 t fired, .

Time elapsed: 822 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 421/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3392812 m, 7743 m/sec, 193335507 t fired, .

Time elapsed: 827 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 426/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3431344 m, 7706 m/sec, 195557158 t fired, .

Time elapsed: 832 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 431/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3469883 m, 7707 m/sec, 197786305 t fired, .

Time elapsed: 837 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 436/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3510831 m, 8189 m/sec, 200103504 t fired, .

Time elapsed: 842 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 441/638 15/32 DLCshifumi-PT-4a-CTLFireability-06 3551209 m, 8075 m/sec, 202393524 t fired, .

Time elapsed: 847 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 446/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3592346 m, 8227 m/sec, 204733721 t fired, .

Time elapsed: 852 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 451/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3632691 m, 8069 m/sec, 207044612 t fired, .

Time elapsed: 857 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 456/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3671547 m, 7771 m/sec, 209318606 t fired, .

Time elapsed: 862 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 461/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3710179 m, 7726 m/sec, 211576532 t fired, .

Time elapsed: 867 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 466/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3749418 m, 7847 m/sec, 213852449 t fired, .

Time elapsed: 872 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 471/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3788227 m, 7761 m/sec, 216121468 t fired, .

Time elapsed: 877 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 476/638 16/32 DLCshifumi-PT-4a-CTLFireability-06 3827204 m, 7795 m/sec, 218402298 t fired, .

Time elapsed: 882 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 481/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 3866068 m, 7772 m/sec, 220681878 t fired, .

Time elapsed: 887 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 486/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 3904742 m, 7734 m/sec, 222951285 t fired, .

Time elapsed: 892 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 491/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 3943245 m, 7700 m/sec, 225210909 t fired, .

Time elapsed: 897 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 496/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 3982104 m, 7771 m/sec, 227486328 t fired, .

Time elapsed: 902 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 501/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 4021139 m, 7807 m/sec, 229754769 t fired, .

Time elapsed: 907 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 506/638 17/32 DLCshifumi-PT-4a-CTLFireability-06 4060002 m, 7772 m/sec, 232032410 t fired, .

Time elapsed: 912 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 511/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4099197 m, 7839 m/sec, 234314815 t fired, .

Time elapsed: 917 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 516/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4137651 m, 7690 m/sec, 236583779 t fired, .

Time elapsed: 922 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 521/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4177250 m, 7919 m/sec, 238865379 t fired, .

Time elapsed: 927 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 526/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4215654 m, 7680 m/sec, 241120661 t fired, .

Time elapsed: 932 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 531/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4254206 m, 7710 m/sec, 243381153 t fired, .

Time elapsed: 937 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 536/638 18/32 DLCshifumi-PT-4a-CTLFireability-06 4293147 m, 7788 m/sec, 245629256 t fired, .

Time elapsed: 942 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 541/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4332065 m, 7783 m/sec, 247883101 t fired, .

Time elapsed: 947 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 546/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4370957 m, 7778 m/sec, 250145099 t fired, .

Time elapsed: 952 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 551/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4410809 m, 7970 m/sec, 252461833 t fired, .

Time elapsed: 957 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 556/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4450213 m, 7880 m/sec, 254727764 t fired, .

Time elapsed: 962 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 561/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4489319 m, 7821 m/sec, 257000640 t fired, .

Time elapsed: 967 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 566/638 19/32 DLCshifumi-PT-4a-CTLFireability-06 4528040 m, 7744 m/sec, 259268986 t fired, .

Time elapsed: 972 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 571/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4566960 m, 7784 m/sec, 261540081 t fired, .

Time elapsed: 977 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 576/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4605939 m, 7795 m/sec, 263826389 t fired, .

Time elapsed: 982 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 581/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4643950 m, 7602 m/sec, 266076787 t fired, .

Time elapsed: 987 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 586/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4682241 m, 7658 m/sec, 268331315 t fired, .

Time elapsed: 992 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 591/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4721122 m, 7776 m/sec, 270596289 t fired, .

Time elapsed: 997 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 596/638 20/32 DLCshifumi-PT-4a-CTLFireability-06 4759985 m, 7772 m/sec, 272872312 t fired, .

Time elapsed: 1002 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 601/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4798595 m, 7722 m/sec, 275127326 t fired, .

Time elapsed: 1007 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 606/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4837735 m, 7828 m/sec, 277409361 t fired, .

Time elapsed: 1012 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 611/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4877832 m, 8019 m/sec, 279723099 t fired, .

Time elapsed: 1017 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 616/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4916899 m, 7813 m/sec, 281997432 t fired, .

Time elapsed: 1022 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 621/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4956308 m, 7881 m/sec, 284281866 t fired, .

Time elapsed: 1027 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 626/638 21/32 DLCshifumi-PT-4a-CTLFireability-06 4995905 m, 7919 m/sec, 286548239 t fired, .

Time elapsed: 1032 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 631/638 22/32 DLCshifumi-PT-4a-CTLFireability-06 5036449 m, 8108 m/sec, 288850827 t fired, .

Time elapsed: 1037 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 636/638 22/32 DLCshifumi-PT-4a-CTLFireability-06 5076111 m, 7932 m/sec, 291166400 t fired, .

Time elapsed: 1042 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 20 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-06 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 1 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1047 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 17 (type EXCL) for 16 DLCshifumi-PT-4a-CTLFireability-05
lola: time limit : 638 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 20 (type EXCL) for 19 DLCshifumi-PT-4a-CTLFireability-06
lola: time limit : 2553 sec
lola: memory limit: 5 pages
lola: FINISHED task # 17 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-05
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/638 1/5 DLCshifumi-PT-4a-CTLFireability-06 42695 m, -1006683 m/sec, 2452762 t fired, .

Time elapsed: 1052 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/638 1/5 DLCshifumi-PT-4a-CTLFireability-06 85015 m, 8464 m/sec, 4862908 t fired, .

Time elapsed: 1057 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/638 1/5 DLCshifumi-PT-4a-CTLFireability-06 127136 m, 8424 m/sec, 7266163 t fired, .

Time elapsed: 1062 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/638 1/5 DLCshifumi-PT-4a-CTLFireability-06 168374 m, 8247 m/sec, 9657371 t fired, .

Time elapsed: 1067 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/638 1/5 DLCshifumi-PT-4a-CTLFireability-06 209209 m, 8167 m/sec, 11996968 t fired, .

Time elapsed: 1072 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 250602 m, 8278 m/sec, 14348413 t fired, .

Time elapsed: 1077 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 290823 m, 8044 m/sec, 16671870 t fired, .

Time elapsed: 1082 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 40/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 330401 m, 7915 m/sec, 18967412 t fired, .

Time elapsed: 1087 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 45/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 369854 m, 7890 m/sec, 21275625 t fired, .

Time elapsed: 1092 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 50/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 409673 m, 7963 m/sec, 23592071 t fired, .

Time elapsed: 1097 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 55/638 2/5 DLCshifumi-PT-4a-CTLFireability-06 450613 m, 8188 m/sec, 25923688 t fired, .

Time elapsed: 1102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 60/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 492276 m, 8332 m/sec, 28269038 t fired, .

Time elapsed: 1107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 65/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 532974 m, 8139 m/sec, 30577997 t fired, .

Time elapsed: 1112 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 70/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 573070 m, 8019 m/sec, 32868914 t fired, .

Time elapsed: 1117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 75/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 612677 m, 7921 m/sec, 35147811 t fired, .

Time elapsed: 1122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 80/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 653956 m, 8255 m/sec, 37473448 t fired, .

Time elapsed: 1127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 85/638 3/5 DLCshifumi-PT-4a-CTLFireability-06 695141 m, 8237 m/sec, 39794026 t fired, .

Time elapsed: 1132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 90/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 735312 m, 8034 m/sec, 42082735 t fired, .

Time elapsed: 1137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 95/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 775017 m, 7941 m/sec, 44353731 t fired, .

Time elapsed: 1142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 100/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 814607 m, 7918 m/sec, 46638044 t fired, .

Time elapsed: 1147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 105/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 853465 m, 7771 m/sec, 48898353 t fired, .

Time elapsed: 1152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 110/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 893137 m, 7934 m/sec, 51196070 t fired, .

Time elapsed: 1157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 115/638 4/5 DLCshifumi-PT-4a-CTLFireability-06 932653 m, 7903 m/sec, 53512564 t fired, .

Time elapsed: 1162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 120/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 971892 m, 7847 m/sec, 55800771 t fired, .

Time elapsed: 1167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 125/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 1011534 m, 7928 m/sec, 58102228 t fired, .

Time elapsed: 1172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 130/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 1052627 m, 8218 m/sec, 60436312 t fired, .

Time elapsed: 1177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 135/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 1095357 m, 8546 m/sec, 62809384 t fired, .

Time elapsed: 1182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 140/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 1136894 m, 8307 m/sec, 65132709 t fired, .

Time elapsed: 1187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 145/638 5/5 DLCshifumi-PT-4a-CTLFireability-06 1177660 m, 8153 m/sec, 67432297 t fired, .

Time elapsed: 1192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 20 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 8 (type EXCL) for 7 DLCshifumi-PT-4a-CTLFireability-01
lola: time limit : 801 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/801 2/32 DLCshifumi-PT-4a-CTLFireability-01 231619 m, 46323 m/sec, 2343613 t fired, .

Time elapsed: 1202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/801 3/32 DLCshifumi-PT-4a-CTLFireability-01 484146 m, 50505 m/sec, 4632910 t fired, .

Time elapsed: 1207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 15/801 4/32 DLCshifumi-PT-4a-CTLFireability-01 744483 m, 52067 m/sec, 6914354 t fired, .

Time elapsed: 1212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 20/801 5/32 DLCshifumi-PT-4a-CTLFireability-01 1017445 m, 54592 m/sec, 9165963 t fired, .

Time elapsed: 1217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 25/801 6/32 DLCshifumi-PT-4a-CTLFireability-01 1297767 m, 56064 m/sec, 11414783 t fired, .

Time elapsed: 1222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 30/801 7/32 DLCshifumi-PT-4a-CTLFireability-01 1587201 m, 57886 m/sec, 13642201 t fired, .

Time elapsed: 1227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 35/801 8/32 DLCshifumi-PT-4a-CTLFireability-01 1823324 m, 47224 m/sec, 15946445 t fired, .

Time elapsed: 1232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 40/801 10/32 DLCshifumi-PT-4a-CTLFireability-01 2081185 m, 51572 m/sec, 18230231 t fired, .

Time elapsed: 1237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 45/801 11/32 DLCshifumi-PT-4a-CTLFireability-01 2351716 m, 54106 m/sec, 20497933 t fired, .

Time elapsed: 1242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 50/801 12/32 DLCshifumi-PT-4a-CTLFireability-01 2619442 m, 53545 m/sec, 22763693 t fired, .

Time elapsed: 1247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 55/801 13/32 DLCshifumi-PT-4a-CTLFireability-01 2893392 m, 54790 m/sec, 25016939 t fired, .

Time elapsed: 1252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 60/801 14/32 DLCshifumi-PT-4a-CTLFireability-01 3189569 m, 59235 m/sec, 27220861 t fired, .

Time elapsed: 1257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 65/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 57187 m/sec, 29349506 t fired, .

Time elapsed: 1262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 70/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 31650890 t fired, .

Time elapsed: 1267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 75/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 33948288 t fired, .

Time elapsed: 1272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 80/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 36235217 t fired, .

Time elapsed: 1277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 85/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 38535179 t fired, .

Time elapsed: 1282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 90/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 40836794 t fired, .

Time elapsed: 1287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 95/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 43139811 t fired, .

Time elapsed: 1292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 100/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 45418432 t fired, .

Time elapsed: 1297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 105/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 47720007 t fired, .

Time elapsed: 1302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 110/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 50001386 t fired, .

Time elapsed: 1307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 115/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 52272052 t fired, .

Time elapsed: 1312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 120/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 54543527 t fired, .

Time elapsed: 1317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 125/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 56809165 t fired, .

Time elapsed: 1322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 130/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 59053663 t fired, .

Time elapsed: 1327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 135/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3475507 m, 0 m/sec, 61296191 t fired, .

Time elapsed: 1332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 140/801 16/32 DLCshifumi-PT-4a-CTLFireability-01 3596348 m, 24168 m/sec, 63598758 t fired, .

Time elapsed: 1337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 145/801 17/32 DLCshifumi-PT-4a-CTLFireability-01 3818939 m, 44518 m/sec, 65902008 t fired, .

Time elapsed: 1342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 150/801 18/32 DLCshifumi-PT-4a-CTLFireability-01 4058145 m, 47841 m/sec, 68166265 t fired, .

Time elapsed: 1347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 155/801 19/32 DLCshifumi-PT-4a-CTLFireability-01 4292243 m, 46819 m/sec, 70434475 t fired, .

Time elapsed: 1352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 160/801 20/32 DLCshifumi-PT-4a-CTLFireability-01 4547711 m, 51093 m/sec, 72657679 t fired, .

Time elapsed: 1357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 165/801 21/32 DLCshifumi-PT-4a-CTLFireability-01 4794409 m, 49339 m/sec, 74896904 t fired, .

Time elapsed: 1362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 170/801 22/32 DLCshifumi-PT-4a-CTLFireability-01 5048105 m, 50739 m/sec, 77127252 t fired, .

Time elapsed: 1367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 175/801 23/32 DLCshifumi-PT-4a-CTLFireability-01 5269794 m, 44337 m/sec, 79338169 t fired, .

Time elapsed: 1372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 180/801 24/32 DLCshifumi-PT-4a-CTLFireability-01 5457987 m, 37638 m/sec, 81498996 t fired, .

Time elapsed: 1377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 185/801 25/32 DLCshifumi-PT-4a-CTLFireability-01 5667691 m, 41940 m/sec, 83598649 t fired, .

Time elapsed: 1382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 190/801 26/32 DLCshifumi-PT-4a-CTLFireability-01 5874653 m, 41392 m/sec, 85702891 t fired, .

Time elapsed: 1387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 195/801 27/32 DLCshifumi-PT-4a-CTLFireability-01 6073825 m, 39834 m/sec, 87841879 t fired, .

Time elapsed: 1392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 200/801 28/32 DLCshifumi-PT-4a-CTLFireability-01 6279458 m, 41126 m/sec, 89984076 t fired, .

Time elapsed: 1397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 205/801 29/32 DLCshifumi-PT-4a-CTLFireability-01 6487644 m, 41637 m/sec, 92118467 t fired, .

Time elapsed: 1402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 210/801 30/32 DLCshifumi-PT-4a-CTLFireability-01 6699764 m, 42424 m/sec, 94235240 t fired, .

Time elapsed: 1407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 215/801 31/32 DLCshifumi-PT-4a-CTLFireability-01 6914283 m, 42903 m/sec, 96346436 t fired, .

Time elapsed: 1412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 220/801 32/32 DLCshifumi-PT-4a-CTLFireability-01 7154218 m, 47987 m/sec, 98459305 t fired, .

Time elapsed: 1417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 8 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-10: AGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 32 (type EXCL) for 31 DLCshifumi-PT-4a-CTLFireability-10
lola: time limit : 1089 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-10
lola: result : true
lola: markings : 6
lola: fired transitions : 166
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DLCshifumi-PT-4a-CTLFireability-03
lola: time limit : 2178 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for DLCshifumi-PT-4a-CTLFireability-03
lola: result : true
lola: markings : 17
lola: fired transitions : 1109
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4a-CTLFireability-00: DISJ true findpath
DLCshifumi-PT-4a-CTLFireability-01: CTL unknown AGGR
DLCshifumi-PT-4a-CTLFireability-02: CTL unknown AGGR
DLCshifumi-PT-4a-CTLFireability-03: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-05: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-06: CTL unknown AGGR
DLCshifumi-PT-4a-CTLFireability-07: EXEF true state space /EXEF
DLCshifumi-PT-4a-CTLFireability-08: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-09: CTL false CTL model checker
DLCshifumi-PT-4a-CTLFireability-10: AGEF true tscc_search
DLCshifumi-PT-4a-CTLFireability-11: CTL unknown AGGR
DLCshifumi-PT-4a-CTLFireability-12: CTL unknown AGGR
DLCshifumi-PT-4a-CTLFireability-13: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-14: CTL true CTL model checker
DLCshifumi-PT-4a-CTLFireability-15: CTL false CTL model checker


Time elapsed: 1422 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-4a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCshifumi-PT-4a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478800826"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-4a.tgz
mv DLCshifumi-PT-4a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;