Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478800786.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-13b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478800786
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.5M
-rw-r--r-- 1 mcc users 6.3K Feb 25 18:45 CTLCardinality.txt
-rw-r--r-- 1 mcc users 63K Feb 25 18:45 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 25 18:45 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 18:45 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 18:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 18:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 18:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 18:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 2.1M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-13b-CTLFireability-00
FORMULA_NAME DLCround-PT-13b-CTLFireability-01
FORMULA_NAME DLCround-PT-13b-CTLFireability-02
FORMULA_NAME DLCround-PT-13b-CTLFireability-03
FORMULA_NAME DLCround-PT-13b-CTLFireability-04
FORMULA_NAME DLCround-PT-13b-CTLFireability-05
FORMULA_NAME DLCround-PT-13b-CTLFireability-06
FORMULA_NAME DLCround-PT-13b-CTLFireability-07
FORMULA_NAME DLCround-PT-13b-CTLFireability-08
FORMULA_NAME DLCround-PT-13b-CTLFireability-09
FORMULA_NAME DLCround-PT-13b-CTLFireability-10
FORMULA_NAME DLCround-PT-13b-CTLFireability-11
FORMULA_NAME DLCround-PT-13b-CTLFireability-12
FORMULA_NAME DLCround-PT-13b-CTLFireability-13
FORMULA_NAME DLCround-PT-13b-CTLFireability-14
FORMULA_NAME DLCround-PT-13b-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678279396884

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-13b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:43:18] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:43:18] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:43:18] [INFO ] Load time of PNML (sax parser for PT used): 222 ms
[2023-03-08 12:43:18] [INFO ] Transformed 5343 places.
[2023-03-08 12:43:18] [INFO ] Transformed 8727 transitions.
[2023-03-08 12:43:18] [INFO ] Found NUPN structural information;
[2023-03-08 12:43:18] [INFO ] Parsed PT model containing 5343 places and 8727 transitions and 24849 arcs in 420 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 157 out of 5343 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 5343/5343 places, 8727/8727 transitions.
Discarding 944 places :
Symmetric choice reduction at 0 with 944 rule applications. Total rules 944 place count 4399 transition count 7783
Iterating global reduction 0 with 944 rules applied. Total rules applied 1888 place count 4399 transition count 7783
Discarding 773 places :
Symmetric choice reduction at 0 with 773 rule applications. Total rules 2661 place count 3626 transition count 7010
Iterating global reduction 0 with 773 rules applied. Total rules applied 3434 place count 3626 transition count 7010
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 0 with 14 rules applied. Total rules applied 3448 place count 3626 transition count 6996
Discarding 67 places :
Symmetric choice reduction at 1 with 67 rule applications. Total rules 3515 place count 3559 transition count 6816
Iterating global reduction 1 with 67 rules applied. Total rules applied 3582 place count 3559 transition count 6816
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 3618 place count 3523 transition count 6780
Iterating global reduction 1 with 36 rules applied. Total rules applied 3654 place count 3523 transition count 6780
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3655 place count 3523 transition count 6779
Discarding 23 places :
Symmetric choice reduction at 2 with 23 rule applications. Total rules 3678 place count 3500 transition count 6756
Iterating global reduction 2 with 23 rules applied. Total rules applied 3701 place count 3500 transition count 6756
Discarding 21 places :
Symmetric choice reduction at 2 with 21 rule applications. Total rules 3722 place count 3479 transition count 6735
Iterating global reduction 2 with 21 rules applied. Total rules applied 3743 place count 3479 transition count 6735
Discarding 21 places :
Symmetric choice reduction at 2 with 21 rule applications. Total rules 3764 place count 3458 transition count 6714
Iterating global reduction 2 with 21 rules applied. Total rules applied 3785 place count 3458 transition count 6714
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 3796 place count 3447 transition count 6703
Iterating global reduction 2 with 11 rules applied. Total rules applied 3807 place count 3447 transition count 6703
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 3814 place count 3440 transition count 6696
Iterating global reduction 2 with 7 rules applied. Total rules applied 3821 place count 3440 transition count 6696
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 3828 place count 3433 transition count 6689
Iterating global reduction 2 with 7 rules applied. Total rules applied 3835 place count 3433 transition count 6689
Applied a total of 3835 rules in 3396 ms. Remains 3433 /5343 variables (removed 1910) and now considering 6689/8727 (removed 2038) transitions.
// Phase 1: matrix 6689 rows 3433 cols
[2023-03-08 12:43:22] [INFO ] Computed 312 place invariants in 51 ms
[2023-03-08 12:43:23] [INFO ] Implicit Places using invariants in 1074 ms returned []
[2023-03-08 12:43:23] [INFO ] Invariant cache hit.
[2023-03-08 12:43:25] [INFO ] Implicit Places using invariants and state equation in 1819 ms returned []
Implicit Place search using SMT with State Equation took 2931 ms to find 0 implicit places.
[2023-03-08 12:43:25] [INFO ] Invariant cache hit.
[2023-03-08 12:43:29] [INFO ] Dead Transitions using invariants and state equation in 3841 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 3433/5343 places, 6689/8727 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10172 ms. Remains : 3433/5343 places, 6689/8727 transitions.
Support contains 157 out of 3433 places after structural reductions.
[2023-03-08 12:43:29] [INFO ] Flatten gal took : 329 ms
[2023-03-08 12:43:30] [INFO ] Flatten gal took : 212 ms
[2023-03-08 12:43:30] [INFO ] Input system was already deterministic with 6689 transitions.
Support contains 155 out of 3433 places (down from 157) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 573 ms. (steps per millisecond=17 ) properties (out of 85) seen :43
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0
Running SMT prover for 42 properties.
[2023-03-08 12:43:31] [INFO ] Invariant cache hit.
[2023-03-08 12:43:34] [INFO ] [Real]Absence check using 312 positive place invariants in 298 ms returned sat
[2023-03-08 12:43:34] [INFO ] After 3313ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:42
[2023-03-08 12:43:37] [INFO ] [Nat]Absence check using 312 positive place invariants in 316 ms returned sat
[2023-03-08 12:43:47] [INFO ] After 8571ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :41
[2023-03-08 12:44:00] [INFO ] After 20669ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :41
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-08 12:44:00] [INFO ] After 25141ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :41
Fused 42 Parikh solutions to 37 different solutions.
Parikh walk visited 28 properties in 3590 ms.
Support contains 27 out of 3433 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2916 edges and 3433 vertex of which 718 / 3433 are part of one of the 61 SCC in 11 ms
Free SCC test removed 657 places
Drop transitions removed 748 transitions
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 767 transitions.
Drop transitions removed 516 transitions
Trivial Post-agglo rules discarded 516 transitions
Performed 516 trivial Post agglomeration. Transition count delta: 516
Iterating post reduction 0 with 516 rules applied. Total rules applied 517 place count 2776 transition count 5406
Reduce places removed 516 places and 0 transitions.
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Drop transitions removed 35 transitions
Trivial Post-agglo rules discarded 35 transitions
Performed 35 trivial Post agglomeration. Transition count delta: 35
Iterating post reduction 1 with 569 rules applied. Total rules applied 1086 place count 2260 transition count 5353
Reduce places removed 35 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 37 rules applied. Total rules applied 1123 place count 2225 transition count 5351
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 4 rules applied. Total rules applied 1127 place count 2223 transition count 5349
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 1128 place count 2222 transition count 5349
Performed 306 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 306 Pre rules applied. Total rules applied 1128 place count 2222 transition count 5043
Deduced a syphon composed of 306 places in 37 ms
Reduce places removed 306 places and 0 transitions.
Iterating global reduction 5 with 612 rules applied. Total rules applied 1740 place count 1916 transition count 5043
Discarding 109 places :
Symmetric choice reduction at 5 with 109 rule applications. Total rules 1849 place count 1807 transition count 4002
Iterating global reduction 5 with 109 rules applied. Total rules applied 1958 place count 1807 transition count 4002
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 5 with 4 rules applied. Total rules applied 1962 place count 1807 transition count 3998
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 16 Pre rules applied. Total rules applied 1962 place count 1807 transition count 3982
Deduced a syphon composed of 16 places in 31 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 6 with 32 rules applied. Total rules applied 1994 place count 1791 transition count 3982
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 1995 place count 1790 transition count 3965
Iterating global reduction 6 with 1 rules applied. Total rules applied 1996 place count 1790 transition count 3965
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 1997 place count 1790 transition count 3964
Performed 684 Post agglomeration using F-continuation condition with reduction of 14 identical transitions.
Deduced a syphon composed of 684 places in 1 ms
Reduce places removed 684 places and 0 transitions.
Iterating global reduction 7 with 1368 rules applied. Total rules applied 3365 place count 1106 transition count 3266
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 7 with 13 rules applied. Total rules applied 3378 place count 1106 transition count 3253
Renaming transitions due to excessive name length > 1024 char.
Discarding 28 places :
Symmetric choice reduction at 8 with 28 rule applications. Total rules 3406 place count 1078 transition count 2786
Iterating global reduction 8 with 28 rules applied. Total rules applied 3434 place count 1078 transition count 2786
Ensure Unique test removed 25 transitions
Reduce isomorphic transitions removed 25 transitions.
Iterating post reduction 8 with 25 rules applied. Total rules applied 3459 place count 1078 transition count 2761
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3461 place count 1077 transition count 2760
Performed 14 Post agglomeration using F-continuation condition.Transition count delta: -158
Deduced a syphon composed of 14 places in 1 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 9 with 28 rules applied. Total rules applied 3489 place count 1063 transition count 2918
Drop transitions removed 7 transitions
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 9 with 10 rules applied. Total rules applied 3499 place count 1063 transition count 2908
Discarding 4 places :
Symmetric choice reduction at 10 with 4 rule applications. Total rules 3503 place count 1059 transition count 2794
Iterating global reduction 10 with 4 rules applied. Total rules applied 3507 place count 1059 transition count 2794
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 10 with 3 rules applied. Total rules applied 3510 place count 1059 transition count 2791
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -37
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 11 with 6 rules applied. Total rules applied 3516 place count 1056 transition count 2828
Drop transitions removed 50 transitions
Redundant transition composition rules discarded 50 transitions
Iterating global reduction 11 with 50 rules applied. Total rules applied 3566 place count 1056 transition count 2778
Discarding 16 places :
Symmetric choice reduction at 11 with 16 rule applications. Total rules 3582 place count 1040 transition count 2762
Iterating global reduction 11 with 16 rules applied. Total rules applied 3598 place count 1040 transition count 2762
Discarding 16 places :
Symmetric choice reduction at 11 with 16 rule applications. Total rules 3614 place count 1024 transition count 2488
Iterating global reduction 11 with 16 rules applied. Total rules applied 3630 place count 1024 transition count 2488
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Iterating post reduction 11 with 16 rules applied. Total rules applied 3646 place count 1024 transition count 2472
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 12 with 30 rules applied. Total rules applied 3676 place count 1009 transition count 2457
Discarding 14 places :
Symmetric choice reduction at 12 with 14 rule applications. Total rules 3690 place count 995 transition count 2218
Iterating global reduction 12 with 14 rules applied. Total rules applied 3704 place count 995 transition count 2218
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 12 with 13 rules applied. Total rules applied 3717 place count 995 transition count 2205
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -25
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 13 with 6 rules applied. Total rules applied 3723 place count 992 transition count 2230
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 13 with 4 rules applied. Total rules applied 3727 place count 992 transition count 2226
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 14 with 21 rules applied. Total rules applied 3748 place count 992 transition count 2205
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 14 with 6 rules applied. Total rules applied 3754 place count 989 transition count 2228
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 14 with 5 rules applied. Total rules applied 3759 place count 989 transition count 2223
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 15 with 18 rules applied. Total rules applied 3777 place count 989 transition count 2205
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -28
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 15 with 6 rules applied. Total rules applied 3783 place count 986 transition count 2233
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 15 with 4 rules applied. Total rules applied 3787 place count 986 transition count 2229
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 16 with 21 rules applied. Total rules applied 3808 place count 986 transition count 2208
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 16 with 6 rules applied. Total rules applied 3814 place count 983 transition count 2235
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 16 with 5 rules applied. Total rules applied 3819 place count 983 transition count 2230
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 17 with 20 rules applied. Total rules applied 3839 place count 983 transition count 2210
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 17 with 6 rules applied. Total rules applied 3845 place count 980 transition count 2233
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 17 with 5 rules applied. Total rules applied 3850 place count 980 transition count 2228
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 18 with 17 rules applied. Total rules applied 3867 place count 980 transition count 2211
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -28
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 18 with 6 rules applied. Total rules applied 3873 place count 977 transition count 2239
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 18 with 5 rules applied. Total rules applied 3878 place count 977 transition count 2234
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 19 with 19 rules applied. Total rules applied 3897 place count 977 transition count 2215
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -31
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 19 with 6 rules applied. Total rules applied 3903 place count 974 transition count 2246
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 19 with 4 rules applied. Total rules applied 3907 place count 974 transition count 2242
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 20 with 18 rules applied. Total rules applied 3925 place count 974 transition count 2224
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -25
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 20 with 6 rules applied. Total rules applied 3931 place count 971 transition count 2249
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 20 with 4 rules applied. Total rules applied 3935 place count 971 transition count 2245
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 21 with 20 rules applied. Total rules applied 3955 place count 971 transition count 2225
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -24
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 21 with 6 rules applied. Total rules applied 3961 place count 968 transition count 2249
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 21 with 5 rules applied. Total rules applied 3966 place count 968 transition count 2244
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 22 with 18 rules applied. Total rules applied 3984 place count 968 transition count 2226
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -22
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 22 with 6 rules applied. Total rules applied 3990 place count 965 transition count 2248
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 22 with 5 rules applied. Total rules applied 3995 place count 965 transition count 2243
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 23 with 17 rules applied. Total rules applied 4012 place count 965 transition count 2226
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -27
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 23 with 6 rules applied. Total rules applied 4018 place count 962 transition count 2253
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 23 with 5 rules applied. Total rules applied 4023 place count 962 transition count 2248
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 24 with 18 rules applied. Total rules applied 4041 place count 962 transition count 2230
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 24 with 6 rules applied. Total rules applied 4047 place count 959 transition count 2259
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 24 with 4 rules applied. Total rules applied 4051 place count 959 transition count 2255
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 25 with 18 rules applied. Total rules applied 4069 place count 959 transition count 2237
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 25 with 6 rules applied. Total rules applied 4075 place count 956 transition count 2263
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 25 with 5 rules applied. Total rules applied 4080 place count 956 transition count 2258
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 26 with 18 rules applied. Total rules applied 4098 place count 956 transition count 2240
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 26 with 6 rules applied. Total rules applied 4104 place count 953 transition count 2269
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 26 with 4 rules applied. Total rules applied 4108 place count 953 transition count 2265
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 27 with 20 rules applied. Total rules applied 4128 place count 953 transition count 2245
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -25
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 27 with 6 rules applied. Total rules applied 4134 place count 950 transition count 2270
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 27 with 4 rules applied. Total rules applied 4138 place count 950 transition count 2266
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 28 with 18 rules applied. Total rules applied 4156 place count 950 transition count 2248
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -24
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 28 with 6 rules applied. Total rules applied 4162 place count 947 transition count 2272
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 28 with 5 rules applied. Total rules applied 4167 place count 947 transition count 2267
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 29 with 19 rules applied. Total rules applied 4186 place count 947 transition count 2248
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 29 with 6 rules applied. Total rules applied 4192 place count 944 transition count 2271
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 29 with 4 rules applied. Total rules applied 4196 place count 944 transition count 2267
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 30 with 18 rules applied. Total rules applied 4214 place count 944 transition count 2249
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 30 with 6 rules applied. Total rules applied 4220 place count 941 transition count 2278
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 30 with 5 rules applied. Total rules applied 4225 place count 941 transition count 2273
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 31 with 12 rules applied. Total rules applied 4237 place count 941 transition count 2261
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -12
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 31 with 2 rules applied. Total rules applied 4239 place count 940 transition count 2273
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 31 with 2 rules applied. Total rules applied 4241 place count 940 transition count 2271
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 32 with 1 rules applied. Total rules applied 4242 place count 940 transition count 2270
Free-agglomeration rule applied 511 times with reduction of 253 identical transitions.
Iterating global reduction 32 with 511 rules applied. Total rules applied 4753 place count 940 transition count 1506
Reduce places removed 511 places and 0 transitions.
Drop transitions removed 606 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 611 transitions.
Graph (complete) has 1189 edges and 429 vertex of which 366 are kept as prefixes of interest. Removing 63 places using SCC suffix rule.1 ms
Discarding 63 places :
Also discarding 0 output transitions
Iterating post reduction 32 with 1123 rules applied. Total rules applied 5876 place count 366 transition count 895
Discarding 110 places :
Symmetric choice reduction at 33 with 110 rule applications. Total rules 5986 place count 256 transition count 673
Iterating global reduction 33 with 110 rules applied. Total rules applied 6096 place count 256 transition count 673
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: -28
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 33 with 10 rules applied. Total rules applied 6106 place count 251 transition count 701
Drop transitions removed 37 transitions
Reduce isomorphic transitions removed 37 transitions.
Iterating post reduction 33 with 37 rules applied. Total rules applied 6143 place count 251 transition count 664
Discarding 4 places :
Symmetric choice reduction at 34 with 4 rule applications. Total rules 6147 place count 247 transition count 634
Iterating global reduction 34 with 4 rules applied. Total rules applied 6151 place count 247 transition count 634
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 34 with 4 rules applied. Total rules applied 6155 place count 247 transition count 630
Drop transitions removed 68 transitions
Redundant transition composition rules discarded 68 transitions
Iterating global reduction 35 with 68 rules applied. Total rules applied 6223 place count 247 transition count 562
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 35 with 1 rules applied. Total rules applied 6224 place count 246 transition count 562
Discarding 8 places :
Symmetric choice reduction at 36 with 8 rule applications. Total rules 6232 place count 238 transition count 547
Iterating global reduction 36 with 8 rules applied. Total rules applied 6240 place count 238 transition count 547
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 36 with 1 rules applied. Total rules applied 6241 place count 238 transition count 555
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 36 with 7 rules applied. Total rules applied 6248 place count 237 transition count 549
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 37 with 4 rules applied. Total rules applied 6252 place count 237 transition count 545
Applied a total of 6252 rules in 3590 ms. Remains 237 /3433 variables (removed 3196) and now considering 545/6689 (removed 6144) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3590 ms. Remains : 237/3433 places, 545/6689 transitions.
Finished random walk after 8678 steps, including 2 resets, run visited all 13 properties in 105 ms. (steps per millisecond=82 )
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 12:44:07] [INFO ] Flatten gal took : 156 ms
[2023-03-08 12:44:07] [INFO ] Flatten gal took : 171 ms
[2023-03-08 12:44:08] [INFO ] Input system was already deterministic with 6689 transitions.
Computed a total of 629 stabilizing places and 629 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2953 edges and 3433 vertex of which 732 / 3433 are part of one of the 60 SCC in 2 ms
Free SCC test removed 672 places
Ensure Unique test removed 724 transitions
Reduce isomorphic transitions removed 724 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 522 transitions
Trivial Post-agglo rules discarded 522 transitions
Performed 522 trivial Post agglomeration. Transition count delta: 522
Iterating post reduction 0 with 522 rules applied. Total rules applied 523 place count 2760 transition count 5442
Reduce places removed 522 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 1 with 582 rules applied. Total rules applied 1105 place count 2238 transition count 5382
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 41 rules applied. Total rules applied 1146 place count 2199 transition count 5380
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 1147 place count 2198 transition count 5380
Performed 301 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 301 Pre rules applied. Total rules applied 1147 place count 2198 transition count 5079
Deduced a syphon composed of 301 places in 38 ms
Reduce places removed 301 places and 0 transitions.
Iterating global reduction 4 with 602 rules applied. Total rules applied 1749 place count 1897 transition count 5079
Discarding 121 places :
Symmetric choice reduction at 4 with 121 rule applications. Total rules 1870 place count 1776 transition count 3930
Iterating global reduction 4 with 121 rules applied. Total rules applied 1991 place count 1776 transition count 3930
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 1995 place count 1776 transition count 3926
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 17 Pre rules applied. Total rules applied 1995 place count 1776 transition count 3909
Deduced a syphon composed of 17 places in 29 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 2029 place count 1759 transition count 3909
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 2030 place count 1758 transition count 3892
Iterating global reduction 5 with 1 rules applied. Total rules applied 2031 place count 1758 transition count 3892
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2032 place count 1758 transition count 3891
Performed 636 Post agglomeration using F-continuation condition.Transition count delta: 636
Deduced a syphon composed of 636 places in 1 ms
Reduce places removed 636 places and 0 transitions.
Iterating global reduction 6 with 1272 rules applied. Total rules applied 3304 place count 1122 transition count 3255
Renaming transitions due to excessive name length > 1024 char.
Discarding 33 places :
Symmetric choice reduction at 6 with 33 rule applications. Total rules 3337 place count 1089 transition count 2706
Iterating global reduction 6 with 33 rules applied. Total rules applied 3370 place count 1089 transition count 2706
Ensure Unique test removed 31 transitions
Reduce isomorphic transitions removed 31 transitions.
Iterating post reduction 6 with 31 rules applied. Total rules applied 3401 place count 1089 transition count 2675
Drop transitions removed 28 transitions
Redundant transition composition rules discarded 28 transitions
Iterating global reduction 7 with 28 rules applied. Total rules applied 3429 place count 1089 transition count 2647
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 7 with 14 rules applied. Total rules applied 3443 place count 1089 transition count 2633
Reduce places removed 14 places and 0 transitions.
Iterating post reduction 8 with 14 rules applied. Total rules applied 3457 place count 1075 transition count 2633
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3459 place count 1073 transition count 2631
Applied a total of 3459 rules in 650 ms. Remains 1073 /3433 variables (removed 2360) and now considering 2631/6689 (removed 4058) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 651 ms. Remains : 1073/3433 places, 2631/6689 transitions.
[2023-03-08 12:44:09] [INFO ] Flatten gal took : 58 ms
[2023-03-08 12:44:09] [INFO ] Flatten gal took : 62 ms
[2023-03-08 12:44:09] [INFO ] Input system was already deterministic with 2631 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 41 places :
Symmetric choice reduction at 0 with 41 rule applications. Total rules 41 place count 3392 transition count 6550
Iterating global reduction 0 with 41 rules applied. Total rules applied 82 place count 3392 transition count 6550
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 97 place count 3377 transition count 6535
Iterating global reduction 0 with 15 rules applied. Total rules applied 112 place count 3377 transition count 6535
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 114 place count 3377 transition count 6533
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 117 place count 3374 transition count 6529
Iterating global reduction 1 with 3 rules applied. Total rules applied 120 place count 3374 transition count 6529
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 123 place count 3371 transition count 6526
Iterating global reduction 1 with 3 rules applied. Total rules applied 126 place count 3371 transition count 6526
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 127 place count 3371 transition count 6525
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 129 place count 3369 transition count 6523
Iterating global reduction 2 with 2 rules applied. Total rules applied 131 place count 3369 transition count 6523
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 132 place count 3368 transition count 6522
Iterating global reduction 2 with 1 rules applied. Total rules applied 133 place count 3368 transition count 6522
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 134 place count 3367 transition count 6521
Iterating global reduction 2 with 1 rules applied. Total rules applied 135 place count 3367 transition count 6521
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 136 place count 3366 transition count 6520
Iterating global reduction 2 with 1 rules applied. Total rules applied 137 place count 3366 transition count 6520
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 138 place count 3365 transition count 6519
Iterating global reduction 2 with 1 rules applied. Total rules applied 139 place count 3365 transition count 6519
Applied a total of 139 rules in 1579 ms. Remains 3365 /3433 variables (removed 68) and now considering 6519/6689 (removed 170) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1580 ms. Remains : 3365/3433 places, 6519/6689 transitions.
[2023-03-08 12:44:10] [INFO ] Flatten gal took : 141 ms
[2023-03-08 12:44:11] [INFO ] Flatten gal took : 146 ms
[2023-03-08 12:44:11] [INFO ] Input system was already deterministic with 6519 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 42 places :
Symmetric choice reduction at 0 with 42 rule applications. Total rules 42 place count 3391 transition count 6549
Iterating global reduction 0 with 42 rules applied. Total rules applied 84 place count 3391 transition count 6549
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 98 place count 3377 transition count 6535
Iterating global reduction 0 with 14 rules applied. Total rules applied 112 place count 3377 transition count 6535
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 114 place count 3377 transition count 6533
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 118 place count 3373 transition count 6528
Iterating global reduction 1 with 4 rules applied. Total rules applied 122 place count 3373 transition count 6528
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 126 place count 3369 transition count 6524
Iterating global reduction 1 with 4 rules applied. Total rules applied 130 place count 3369 transition count 6524
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 131 place count 3369 transition count 6523
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 134 place count 3366 transition count 6520
Iterating global reduction 2 with 3 rules applied. Total rules applied 137 place count 3366 transition count 6520
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 138 place count 3365 transition count 6519
Iterating global reduction 2 with 1 rules applied. Total rules applied 139 place count 3365 transition count 6519
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 140 place count 3364 transition count 6518
Iterating global reduction 2 with 1 rules applied. Total rules applied 141 place count 3364 transition count 6518
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 142 place count 3363 transition count 6517
Iterating global reduction 2 with 1 rules applied. Total rules applied 143 place count 3363 transition count 6517
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 144 place count 3362 transition count 6516
Iterating global reduction 2 with 1 rules applied. Total rules applied 145 place count 3362 transition count 6516
Applied a total of 145 rules in 1609 ms. Remains 3362 /3433 variables (removed 71) and now considering 6516/6689 (removed 173) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1610 ms. Remains : 3362/3433 places, 6516/6689 transitions.
[2023-03-08 12:44:13] [INFO ] Flatten gal took : 124 ms
[2023-03-08 12:44:13] [INFO ] Flatten gal took : 136 ms
[2023-03-08 12:44:13] [INFO ] Input system was already deterministic with 6516 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 3389 transition count 6547
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 3389 transition count 6547
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 104 place count 3373 transition count 6531
Iterating global reduction 0 with 16 rules applied. Total rules applied 120 place count 3373 transition count 6531
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 122 place count 3373 transition count 6529
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 126 place count 3369 transition count 6524
Iterating global reduction 1 with 4 rules applied. Total rules applied 130 place count 3369 transition count 6524
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 134 place count 3365 transition count 6520
Iterating global reduction 1 with 4 rules applied. Total rules applied 138 place count 3365 transition count 6520
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 139 place count 3365 transition count 6519
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 142 place count 3362 transition count 6516
Iterating global reduction 2 with 3 rules applied. Total rules applied 145 place count 3362 transition count 6516
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 146 place count 3361 transition count 6515
Iterating global reduction 2 with 1 rules applied. Total rules applied 147 place count 3361 transition count 6515
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 148 place count 3360 transition count 6514
Iterating global reduction 2 with 1 rules applied. Total rules applied 149 place count 3360 transition count 6514
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 150 place count 3359 transition count 6513
Iterating global reduction 2 with 1 rules applied. Total rules applied 151 place count 3359 transition count 6513
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 152 place count 3358 transition count 6512
Iterating global reduction 2 with 1 rules applied. Total rules applied 153 place count 3358 transition count 6512
Applied a total of 153 rules in 1641 ms. Remains 3358 /3433 variables (removed 75) and now considering 6512/6689 (removed 177) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1642 ms. Remains : 3358/3433 places, 6512/6689 transitions.
[2023-03-08 12:44:15] [INFO ] Flatten gal took : 116 ms
[2023-03-08 12:44:15] [INFO ] Flatten gal took : 120 ms
[2023-03-08 12:44:15] [INFO ] Input system was already deterministic with 6512 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2952 edges and 3433 vertex of which 732 / 3433 are part of one of the 60 SCC in 2 ms
Free SCC test removed 672 places
Ensure Unique test removed 724 transitions
Reduce isomorphic transitions removed 724 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 523 transitions
Trivial Post-agglo rules discarded 523 transitions
Performed 523 trivial Post agglomeration. Transition count delta: 523
Iterating post reduction 0 with 523 rules applied. Total rules applied 524 place count 2760 transition count 5441
Reduce places removed 523 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 1 with 583 rules applied. Total rules applied 1107 place count 2237 transition count 5381
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 41 rules applied. Total rules applied 1148 place count 2198 transition count 5379
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 1149 place count 2197 transition count 5379
Performed 301 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 301 Pre rules applied. Total rules applied 1149 place count 2197 transition count 5078
Deduced a syphon composed of 301 places in 36 ms
Reduce places removed 301 places and 0 transitions.
Iterating global reduction 4 with 602 rules applied. Total rules applied 1751 place count 1896 transition count 5078
Discarding 120 places :
Symmetric choice reduction at 4 with 120 rule applications. Total rules 1871 place count 1776 transition count 3930
Iterating global reduction 4 with 120 rules applied. Total rules applied 1991 place count 1776 transition count 3930
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 1995 place count 1776 transition count 3926
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 17 Pre rules applied. Total rules applied 1995 place count 1776 transition count 3909
Deduced a syphon composed of 17 places in 29 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 2029 place count 1759 transition count 3909
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 2030 place count 1758 transition count 3892
Iterating global reduction 5 with 1 rules applied. Total rules applied 2031 place count 1758 transition count 3892
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2032 place count 1758 transition count 3891
Performed 635 Post agglomeration using F-continuation condition.Transition count delta: 635
Deduced a syphon composed of 635 places in 1 ms
Reduce places removed 635 places and 0 transitions.
Iterating global reduction 6 with 1270 rules applied. Total rules applied 3302 place count 1123 transition count 3256
Renaming transitions due to excessive name length > 1024 char.
Discarding 32 places :
Symmetric choice reduction at 6 with 32 rule applications. Total rules 3334 place count 1091 transition count 2724
Iterating global reduction 6 with 32 rules applied. Total rules applied 3366 place count 1091 transition count 2724
Ensure Unique test removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 6 with 30 rules applied. Total rules applied 3396 place count 1091 transition count 2694
Drop transitions removed 28 transitions
Redundant transition composition rules discarded 28 transitions
Iterating global reduction 7 with 28 rules applied. Total rules applied 3424 place count 1091 transition count 2666
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 7 with 14 rules applied. Total rules applied 3438 place count 1091 transition count 2652
Reduce places removed 14 places and 0 transitions.
Iterating post reduction 8 with 14 rules applied. Total rules applied 3452 place count 1077 transition count 2652
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3454 place count 1075 transition count 2650
Applied a total of 3454 rules in 572 ms. Remains 1075 /3433 variables (removed 2358) and now considering 2650/6689 (removed 4039) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 572 ms. Remains : 1075/3433 places, 2650/6689 transitions.
[2023-03-08 12:44:16] [INFO ] Flatten gal took : 53 ms
[2023-03-08 12:44:16] [INFO ] Flatten gal took : 78 ms
[2023-03-08 12:44:16] [INFO ] Input system was already deterministic with 2650 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 45 places :
Symmetric choice reduction at 0 with 45 rule applications. Total rules 45 place count 3388 transition count 6531
Iterating global reduction 0 with 45 rules applied. Total rules applied 90 place count 3388 transition count 6531
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 105 place count 3373 transition count 6516
Iterating global reduction 0 with 15 rules applied. Total rules applied 120 place count 3373 transition count 6516
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 121 place count 3373 transition count 6515
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 125 place count 3369 transition count 6510
Iterating global reduction 1 with 4 rules applied. Total rules applied 129 place count 3369 transition count 6510
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 133 place count 3365 transition count 6506
Iterating global reduction 1 with 4 rules applied. Total rules applied 137 place count 3365 transition count 6506
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 138 place count 3365 transition count 6505
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 141 place count 3362 transition count 6502
Iterating global reduction 2 with 3 rules applied. Total rules applied 144 place count 3362 transition count 6502
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 145 place count 3361 transition count 6501
Iterating global reduction 2 with 1 rules applied. Total rules applied 146 place count 3361 transition count 6501
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 147 place count 3360 transition count 6500
Iterating global reduction 2 with 1 rules applied. Total rules applied 148 place count 3360 transition count 6500
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 149 place count 3359 transition count 6499
Iterating global reduction 2 with 1 rules applied. Total rules applied 150 place count 3359 transition count 6499
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 151 place count 3358 transition count 6498
Iterating global reduction 2 with 1 rules applied. Total rules applied 152 place count 3358 transition count 6498
Applied a total of 152 rules in 1620 ms. Remains 3358 /3433 variables (removed 75) and now considering 6498/6689 (removed 191) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1620 ms. Remains : 3358/3433 places, 6498/6689 transitions.
[2023-03-08 12:44:18] [INFO ] Flatten gal took : 106 ms
[2023-03-08 12:44:18] [INFO ] Flatten gal took : 114 ms
[2023-03-08 12:44:18] [INFO ] Input system was already deterministic with 6498 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2945 edges and 3433 vertex of which 732 / 3433 are part of one of the 60 SCC in 1 ms
Free SCC test removed 672 places
Ensure Unique test removed 724 transitions
Reduce isomorphic transitions removed 724 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 521 transitions
Trivial Post-agglo rules discarded 521 transitions
Performed 521 trivial Post agglomeration. Transition count delta: 521
Iterating post reduction 0 with 521 rules applied. Total rules applied 522 place count 2760 transition count 5443
Reduce places removed 521 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 1 with 581 rules applied. Total rules applied 1103 place count 2239 transition count 5383
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 41 rules applied. Total rules applied 1144 place count 2200 transition count 5381
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 1145 place count 2199 transition count 5381
Performed 301 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 301 Pre rules applied. Total rules applied 1145 place count 2199 transition count 5080
Deduced a syphon composed of 301 places in 35 ms
Reduce places removed 301 places and 0 transitions.
Iterating global reduction 4 with 602 rules applied. Total rules applied 1747 place count 1898 transition count 5080
Discarding 118 places :
Symmetric choice reduction at 4 with 118 rule applications. Total rules 1865 place count 1780 transition count 3982
Iterating global reduction 4 with 118 rules applied. Total rules applied 1983 place count 1780 transition count 3982
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 1987 place count 1780 transition count 3978
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 17 Pre rules applied. Total rules applied 1987 place count 1780 transition count 3961
Deduced a syphon composed of 17 places in 29 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 2021 place count 1763 transition count 3961
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 2022 place count 1762 transition count 3944
Iterating global reduction 5 with 1 rules applied. Total rules applied 2023 place count 1762 transition count 3944
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2024 place count 1762 transition count 3943
Performed 632 Post agglomeration using F-continuation condition.Transition count delta: 632
Deduced a syphon composed of 632 places in 1 ms
Reduce places removed 632 places and 0 transitions.
Iterating global reduction 6 with 1264 rules applied. Total rules applied 3288 place count 1130 transition count 3311
Renaming transitions due to excessive name length > 1024 char.
Discarding 32 places :
Symmetric choice reduction at 6 with 32 rule applications. Total rules 3320 place count 1098 transition count 2779
Iterating global reduction 6 with 32 rules applied. Total rules applied 3352 place count 1098 transition count 2779
Ensure Unique test removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 6 with 30 rules applied. Total rules applied 3382 place count 1098 transition count 2749
Drop transitions removed 26 transitions
Redundant transition composition rules discarded 26 transitions
Iterating global reduction 7 with 26 rules applied. Total rules applied 3408 place count 1098 transition count 2723
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded 12 transitions
Performed 12 trivial Post agglomeration. Transition count delta: 12
Iterating post reduction 7 with 12 rules applied. Total rules applied 3420 place count 1098 transition count 2711
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 8 with 12 rules applied. Total rules applied 3432 place count 1086 transition count 2711
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 9 with 1 rules applied. Total rules applied 3433 place count 1086 transition count 2711
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3435 place count 1084 transition count 2709
Applied a total of 3435 rules in 592 ms. Remains 1084 /3433 variables (removed 2349) and now considering 2709/6689 (removed 3980) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 592 ms. Remains : 1084/3433 places, 2709/6689 transitions.
[2023-03-08 12:44:19] [INFO ] Flatten gal took : 56 ms
[2023-03-08 12:44:19] [INFO ] Flatten gal took : 60 ms
[2023-03-08 12:44:19] [INFO ] Input system was already deterministic with 2709 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 3389 transition count 6531
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 3389 transition count 6531
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 103 place count 3374 transition count 6516
Iterating global reduction 0 with 15 rules applied. Total rules applied 118 place count 3374 transition count 6516
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 120 place count 3374 transition count 6514
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 124 place count 3370 transition count 6509
Iterating global reduction 1 with 4 rules applied. Total rules applied 128 place count 3370 transition count 6509
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 132 place count 3366 transition count 6505
Iterating global reduction 1 with 4 rules applied. Total rules applied 136 place count 3366 transition count 6505
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 137 place count 3366 transition count 6504
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 140 place count 3363 transition count 6501
Iterating global reduction 2 with 3 rules applied. Total rules applied 143 place count 3363 transition count 6501
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 144 place count 3362 transition count 6500
Iterating global reduction 2 with 1 rules applied. Total rules applied 145 place count 3362 transition count 6500
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 146 place count 3361 transition count 6499
Iterating global reduction 2 with 1 rules applied. Total rules applied 147 place count 3361 transition count 6499
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 148 place count 3360 transition count 6498
Iterating global reduction 2 with 1 rules applied. Total rules applied 149 place count 3360 transition count 6498
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 150 place count 3359 transition count 6497
Iterating global reduction 2 with 1 rules applied. Total rules applied 151 place count 3359 transition count 6497
Applied a total of 151 rules in 1568 ms. Remains 3359 /3433 variables (removed 74) and now considering 6497/6689 (removed 192) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1569 ms. Remains : 3359/3433 places, 6497/6689 transitions.
[2023-03-08 12:44:21] [INFO ] Flatten gal took : 117 ms
[2023-03-08 12:44:21] [INFO ] Flatten gal took : 130 ms
[2023-03-08 12:44:21] [INFO ] Input system was already deterministic with 6497 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 3389 transition count 6547
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 3389 transition count 6547
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 102 place count 3375 transition count 6533
Iterating global reduction 0 with 14 rules applied. Total rules applied 116 place count 3375 transition count 6533
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 118 place count 3375 transition count 6531
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 121 place count 3372 transition count 6527
Iterating global reduction 1 with 3 rules applied. Total rules applied 124 place count 3372 transition count 6527
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 127 place count 3369 transition count 6524
Iterating global reduction 1 with 3 rules applied. Total rules applied 130 place count 3369 transition count 6524
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 131 place count 3369 transition count 6523
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 133 place count 3367 transition count 6521
Iterating global reduction 2 with 2 rules applied. Total rules applied 135 place count 3367 transition count 6521
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 136 place count 3366 transition count 6520
Iterating global reduction 2 with 1 rules applied. Total rules applied 137 place count 3366 transition count 6520
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 138 place count 3365 transition count 6519
Iterating global reduction 2 with 1 rules applied. Total rules applied 139 place count 3365 transition count 6519
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 140 place count 3364 transition count 6518
Iterating global reduction 2 with 1 rules applied. Total rules applied 141 place count 3364 transition count 6518
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 142 place count 3363 transition count 6517
Iterating global reduction 2 with 1 rules applied. Total rules applied 143 place count 3363 transition count 6517
Applied a total of 143 rules in 1522 ms. Remains 3363 /3433 variables (removed 70) and now considering 6517/6689 (removed 172) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1523 ms. Remains : 3363/3433 places, 6517/6689 transitions.
[2023-03-08 12:44:23] [INFO ] Flatten gal took : 113 ms
[2023-03-08 12:44:23] [INFO ] Flatten gal took : 120 ms
[2023-03-08 12:44:23] [INFO ] Input system was already deterministic with 6517 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2951 edges and 3433 vertex of which 732 / 3433 are part of one of the 60 SCC in 1 ms
Free SCC test removed 672 places
Ensure Unique test removed 724 transitions
Reduce isomorphic transitions removed 724 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 522 transitions
Trivial Post-agglo rules discarded 522 transitions
Performed 522 trivial Post agglomeration. Transition count delta: 522
Iterating post reduction 0 with 522 rules applied. Total rules applied 523 place count 2760 transition count 5442
Reduce places removed 522 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 1 with 582 rules applied. Total rules applied 1105 place count 2238 transition count 5382
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 41 rules applied. Total rules applied 1146 place count 2199 transition count 5380
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 1147 place count 2198 transition count 5380
Performed 301 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 301 Pre rules applied. Total rules applied 1147 place count 2198 transition count 5079
Deduced a syphon composed of 301 places in 35 ms
Reduce places removed 301 places and 0 transitions.
Iterating global reduction 4 with 602 rules applied. Total rules applied 1749 place count 1897 transition count 5079
Discarding 120 places :
Symmetric choice reduction at 4 with 120 rule applications. Total rules 1869 place count 1777 transition count 3947
Iterating global reduction 4 with 120 rules applied. Total rules applied 1989 place count 1777 transition count 3947
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 1993 place count 1777 transition count 3943
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 17 Pre rules applied. Total rules applied 1993 place count 1777 transition count 3926
Deduced a syphon composed of 17 places in 28 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 2027 place count 1760 transition count 3926
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 2028 place count 1759 transition count 3909
Iterating global reduction 5 with 1 rules applied. Total rules applied 2029 place count 1759 transition count 3909
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 2030 place count 1759 transition count 3908
Performed 634 Post agglomeration using F-continuation condition.Transition count delta: 634
Deduced a syphon composed of 634 places in 1 ms
Reduce places removed 634 places and 0 transitions.
Iterating global reduction 6 with 1268 rules applied. Total rules applied 3298 place count 1125 transition count 3274
Renaming transitions due to excessive name length > 1024 char.
Discarding 33 places :
Symmetric choice reduction at 6 with 33 rule applications. Total rules 3331 place count 1092 transition count 2725
Iterating global reduction 6 with 33 rules applied. Total rules applied 3364 place count 1092 transition count 2725
Ensure Unique test removed 31 transitions
Reduce isomorphic transitions removed 31 transitions.
Iterating post reduction 6 with 31 rules applied. Total rules applied 3395 place count 1092 transition count 2694
Drop transitions removed 27 transitions
Redundant transition composition rules discarded 27 transitions
Iterating global reduction 7 with 27 rules applied. Total rules applied 3422 place count 1092 transition count 2667
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 7 with 13 rules applied. Total rules applied 3435 place count 1092 transition count 2654
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 8 with 13 rules applied. Total rules applied 3448 place count 1079 transition count 2654
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 9 with 1 rules applied. Total rules applied 3449 place count 1079 transition count 2654
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3451 place count 1077 transition count 2652
Applied a total of 3451 rules in 545 ms. Remains 1077 /3433 variables (removed 2356) and now considering 2652/6689 (removed 4037) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 546 ms. Remains : 1077/3433 places, 2652/6689 transitions.
[2023-03-08 12:44:24] [INFO ] Flatten gal took : 61 ms
[2023-03-08 12:44:24] [INFO ] Flatten gal took : 69 ms
[2023-03-08 12:44:24] [INFO ] Input system was already deterministic with 2652 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Graph (trivial) has 2931 edges and 3433 vertex of which 703 / 3433 are part of one of the 59 SCC in 1 ms
Free SCC test removed 644 places
Ensure Unique test removed 692 transitions
Reduce isomorphic transitions removed 692 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 527 transitions
Trivial Post-agglo rules discarded 527 transitions
Performed 527 trivial Post agglomeration. Transition count delta: 527
Iterating post reduction 0 with 527 rules applied. Total rules applied 528 place count 2788 transition count 5469
Reduce places removed 527 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Drop transitions removed 39 transitions
Trivial Post-agglo rules discarded 39 transitions
Performed 39 trivial Post agglomeration. Transition count delta: 39
Iterating post reduction 1 with 587 rules applied. Total rules applied 1115 place count 2261 transition count 5409
Reduce places removed 39 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 41 rules applied. Total rules applied 1156 place count 2222 transition count 5407
Reduce places removed 1 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 3 rules applied. Total rules applied 1159 place count 2221 transition count 5405
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 1161 place count 2219 transition count 5405
Performed 305 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 305 Pre rules applied. Total rules applied 1161 place count 2219 transition count 5100
Deduced a syphon composed of 305 places in 35 ms
Reduce places removed 305 places and 0 transitions.
Iterating global reduction 5 with 610 rules applied. Total rules applied 1771 place count 1914 transition count 5100
Discarding 111 places :
Symmetric choice reduction at 5 with 111 rule applications. Total rules 1882 place count 1803 transition count 4038
Iterating global reduction 5 with 111 rules applied. Total rules applied 1993 place count 1803 transition count 4038
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 1996 place count 1803 transition count 4035
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 14 Pre rules applied. Total rules applied 1996 place count 1803 transition count 4021
Deduced a syphon composed of 14 places in 27 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 6 with 28 rules applied. Total rules applied 2024 place count 1789 transition count 4021
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 2025 place count 1788 transition count 4004
Iterating global reduction 6 with 1 rules applied. Total rules applied 2026 place count 1788 transition count 4004
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 2027 place count 1788 transition count 4003
Performed 645 Post agglomeration using F-continuation condition.Transition count delta: 645
Deduced a syphon composed of 645 places in 1 ms
Reduce places removed 645 places and 0 transitions.
Iterating global reduction 7 with 1290 rules applied. Total rules applied 3317 place count 1143 transition count 3358
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 3318 place count 1143 transition count 3357
Renaming transitions due to excessive name length > 1024 char.
Discarding 31 places :
Symmetric choice reduction at 8 with 31 rule applications. Total rules 3349 place count 1112 transition count 2842
Iterating global reduction 8 with 31 rules applied. Total rules applied 3380 place count 1112 transition count 2842
Ensure Unique test removed 27 transitions
Reduce isomorphic transitions removed 27 transitions.
Iterating post reduction 8 with 27 rules applied. Total rules applied 3407 place count 1112 transition count 2815
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 3409 place count 1111 transition count 2814
Drop transitions removed 27 transitions
Redundant transition composition rules discarded 27 transitions
Iterating global reduction 9 with 27 rules applied. Total rules applied 3436 place count 1111 transition count 2787
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 9 with 14 rules applied. Total rules applied 3450 place count 1111 transition count 2773
Reduce places removed 14 places and 0 transitions.
Iterating post reduction 10 with 14 rules applied. Total rules applied 3464 place count 1097 transition count 2773
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 11 with 1 rules applied. Total rules applied 3465 place count 1097 transition count 2773
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 3467 place count 1095 transition count 2771
Applied a total of 3467 rules in 581 ms. Remains 1095 /3433 variables (removed 2338) and now considering 2771/6689 (removed 3918) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 581 ms. Remains : 1095/3433 places, 2771/6689 transitions.
[2023-03-08 12:44:25] [INFO ] Flatten gal took : 48 ms
[2023-03-08 12:44:25] [INFO ] Flatten gal took : 52 ms
[2023-03-08 12:44:25] [INFO ] Input system was already deterministic with 2771 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 45 places :
Symmetric choice reduction at 0 with 45 rule applications. Total rules 45 place count 3388 transition count 6530
Iterating global reduction 0 with 45 rules applied. Total rules applied 90 place count 3388 transition count 6530
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 106 place count 3372 transition count 6514
Iterating global reduction 0 with 16 rules applied. Total rules applied 122 place count 3372 transition count 6514
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 124 place count 3372 transition count 6512
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 128 place count 3368 transition count 6507
Iterating global reduction 1 with 4 rules applied. Total rules applied 132 place count 3368 transition count 6507
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 136 place count 3364 transition count 6503
Iterating global reduction 1 with 4 rules applied. Total rules applied 140 place count 3364 transition count 6503
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 141 place count 3364 transition count 6502
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 144 place count 3361 transition count 6499
Iterating global reduction 2 with 3 rules applied. Total rules applied 147 place count 3361 transition count 6499
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 148 place count 3360 transition count 6498
Iterating global reduction 2 with 1 rules applied. Total rules applied 149 place count 3360 transition count 6498
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 150 place count 3359 transition count 6497
Iterating global reduction 2 with 1 rules applied. Total rules applied 151 place count 3359 transition count 6497
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 152 place count 3358 transition count 6496
Iterating global reduction 2 with 1 rules applied. Total rules applied 153 place count 3358 transition count 6496
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 154 place count 3357 transition count 6495
Iterating global reduction 2 with 1 rules applied. Total rules applied 155 place count 3357 transition count 6495
Applied a total of 155 rules in 1532 ms. Remains 3357 /3433 variables (removed 76) and now considering 6495/6689 (removed 194) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1533 ms. Remains : 3357/3433 places, 6495/6689 transitions.
[2023-03-08 12:44:27] [INFO ] Flatten gal took : 119 ms
[2023-03-08 12:44:27] [INFO ] Flatten gal took : 135 ms
[2023-03-08 12:44:27] [INFO ] Input system was already deterministic with 6495 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 40 places :
Symmetric choice reduction at 0 with 40 rule applications. Total rules 40 place count 3393 transition count 6552
Iterating global reduction 0 with 40 rules applied. Total rules applied 80 place count 3393 transition count 6552
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 95 place count 3378 transition count 6537
Iterating global reduction 0 with 15 rules applied. Total rules applied 110 place count 3378 transition count 6537
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 111 place count 3378 transition count 6536
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 115 place count 3374 transition count 6531
Iterating global reduction 1 with 4 rules applied. Total rules applied 119 place count 3374 transition count 6531
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 123 place count 3370 transition count 6527
Iterating global reduction 1 with 4 rules applied. Total rules applied 127 place count 3370 transition count 6527
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 128 place count 3370 transition count 6526
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 131 place count 3367 transition count 6523
Iterating global reduction 2 with 3 rules applied. Total rules applied 134 place count 3367 transition count 6523
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 135 place count 3366 transition count 6522
Iterating global reduction 2 with 1 rules applied. Total rules applied 136 place count 3366 transition count 6522
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 137 place count 3365 transition count 6521
Iterating global reduction 2 with 1 rules applied. Total rules applied 138 place count 3365 transition count 6521
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 139 place count 3364 transition count 6520
Iterating global reduction 2 with 1 rules applied. Total rules applied 140 place count 3364 transition count 6520
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 141 place count 3363 transition count 6519
Iterating global reduction 2 with 1 rules applied. Total rules applied 142 place count 3363 transition count 6519
Applied a total of 142 rules in 1470 ms. Remains 3363 /3433 variables (removed 70) and now considering 6519/6689 (removed 170) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1471 ms. Remains : 3363/3433 places, 6519/6689 transitions.
[2023-03-08 12:44:29] [INFO ] Flatten gal took : 106 ms
[2023-03-08 12:44:29] [INFO ] Flatten gal took : 114 ms
[2023-03-08 12:44:29] [INFO ] Input system was already deterministic with 6519 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 43 places :
Symmetric choice reduction at 0 with 43 rule applications. Total rules 43 place count 3390 transition count 6532
Iterating global reduction 0 with 43 rules applied. Total rules applied 86 place count 3390 transition count 6532
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 98 place count 3378 transition count 6520
Iterating global reduction 0 with 12 rules applied. Total rules applied 110 place count 3378 transition count 6520
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 112 place count 3378 transition count 6518
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 114 place count 3376 transition count 6516
Iterating global reduction 1 with 2 rules applied. Total rules applied 116 place count 3376 transition count 6516
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 118 place count 3374 transition count 6514
Iterating global reduction 1 with 2 rules applied. Total rules applied 120 place count 3374 transition count 6514
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 122 place count 3372 transition count 6512
Iterating global reduction 1 with 2 rules applied. Total rules applied 124 place count 3372 transition count 6512
Applied a total of 124 rules in 867 ms. Remains 3372 /3433 variables (removed 61) and now considering 6512/6689 (removed 177) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 868 ms. Remains : 3372/3433 places, 6512/6689 transitions.
[2023-03-08 12:44:30] [INFO ] Flatten gal took : 105 ms
[2023-03-08 12:44:30] [INFO ] Flatten gal took : 112 ms
[2023-03-08 12:44:30] [INFO ] Input system was already deterministic with 6512 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 45 places :
Symmetric choice reduction at 0 with 45 rule applications. Total rules 45 place count 3388 transition count 6530
Iterating global reduction 0 with 45 rules applied. Total rules applied 90 place count 3388 transition count 6530
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 105 place count 3373 transition count 6515
Iterating global reduction 0 with 15 rules applied. Total rules applied 120 place count 3373 transition count 6515
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 122 place count 3373 transition count 6513
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 126 place count 3369 transition count 6508
Iterating global reduction 1 with 4 rules applied. Total rules applied 130 place count 3369 transition count 6508
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 134 place count 3365 transition count 6504
Iterating global reduction 1 with 4 rules applied. Total rules applied 138 place count 3365 transition count 6504
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 139 place count 3365 transition count 6503
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 142 place count 3362 transition count 6500
Iterating global reduction 2 with 3 rules applied. Total rules applied 145 place count 3362 transition count 6500
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 146 place count 3361 transition count 6499
Iterating global reduction 2 with 1 rules applied. Total rules applied 147 place count 3361 transition count 6499
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 148 place count 3360 transition count 6498
Iterating global reduction 2 with 1 rules applied. Total rules applied 149 place count 3360 transition count 6498
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 150 place count 3359 transition count 6497
Iterating global reduction 2 with 1 rules applied. Total rules applied 151 place count 3359 transition count 6497
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 152 place count 3358 transition count 6496
Iterating global reduction 2 with 1 rules applied. Total rules applied 153 place count 3358 transition count 6496
Applied a total of 153 rules in 1493 ms. Remains 3358 /3433 variables (removed 75) and now considering 6496/6689 (removed 193) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1493 ms. Remains : 3358/3433 places, 6496/6689 transitions.
[2023-03-08 12:44:32] [INFO ] Flatten gal took : 104 ms
[2023-03-08 12:44:32] [INFO ] Flatten gal took : 111 ms
[2023-03-08 12:44:32] [INFO ] Input system was already deterministic with 6496 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3433/3433 places, 6689/6689 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 3386 transition count 6528
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 3386 transition count 6528
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 110 place count 3370 transition count 6512
Iterating global reduction 0 with 16 rules applied. Total rules applied 126 place count 3370 transition count 6512
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 128 place count 3370 transition count 6510
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 132 place count 3366 transition count 6505
Iterating global reduction 1 with 4 rules applied. Total rules applied 136 place count 3366 transition count 6505
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 140 place count 3362 transition count 6501
Iterating global reduction 1 with 4 rules applied. Total rules applied 144 place count 3362 transition count 6501
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 145 place count 3362 transition count 6500
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 148 place count 3359 transition count 6497
Iterating global reduction 2 with 3 rules applied. Total rules applied 151 place count 3359 transition count 6497
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 152 place count 3358 transition count 6496
Iterating global reduction 2 with 1 rules applied. Total rules applied 153 place count 3358 transition count 6496
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 154 place count 3357 transition count 6495
Iterating global reduction 2 with 1 rules applied. Total rules applied 155 place count 3357 transition count 6495
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 156 place count 3356 transition count 6494
Iterating global reduction 2 with 1 rules applied. Total rules applied 157 place count 3356 transition count 6494
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 158 place count 3355 transition count 6493
Iterating global reduction 2 with 1 rules applied. Total rules applied 159 place count 3355 transition count 6493
Applied a total of 159 rules in 1562 ms. Remains 3355 /3433 variables (removed 78) and now considering 6493/6689 (removed 196) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1562 ms. Remains : 3355/3433 places, 6493/6689 transitions.
[2023-03-08 12:44:34] [INFO ] Flatten gal took : 112 ms
[2023-03-08 12:44:34] [INFO ] Flatten gal took : 125 ms
[2023-03-08 12:44:35] [INFO ] Input system was already deterministic with 6493 transitions.
[2023-03-08 12:44:35] [INFO ] Flatten gal took : 115 ms
[2023-03-08 12:44:35] [INFO ] Flatten gal took : 118 ms
[2023-03-08 12:44:35] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 12:44:35] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 3433 places, 6689 transitions and 20535 arcs took 26 ms.
Total runtime 77076 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-13b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA DLCround-PT-13b-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-13b-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678280290002

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-03: DISJ 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-04: EF 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-11: DISJ 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 40 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 62 (type EXCL) for 16 DLCround-PT-13b-CTLFireability-04
lola: time limit : 127 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 60 (type FNDP) for 16 DLCround-PT-13b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type EQUN) for 16 DLCround-PT-13b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SRCH) for 16 DLCround-PT-13b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 63 (type SRCH) for DLCround-PT-13b-CTLFireability-04
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 62 (type EXCL) for DLCround-PT-13b-CTLFireability-04
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 60 (type FNDP) for DLCround-PT-13b-CTLFireability-04 (obsolete)
lola: CANCELED task # 61 (type EQUN) for DLCround-PT-13b-CTLFireability-04 (obsolete)
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-13b-CTLFireability-00
lola: time limit : 136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type FNDP) for DLCround-PT-13b-CTLFireability-04
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 61 (type EQUN) for DLCround-PT-13b-CTLFireability-04
lola: result : unknown
lola: Created skeleton in 2.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-CTLFireability-04: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-03: DISJ 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-06: CTL 1 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCround-PT-13b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-10: CTL 1 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-11: DISJ 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/142 1/32 DLCround-PT-13b-CTLFireability-00 20597 m, 4119 m/sec, 105443 t fired, .

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lola: Created skeleton in 1.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-CTLFireability-04: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13b-CTLFireability-01: CTL 1 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-03: DISJ 0 2 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-11: DISJ 0 3 0 0 3 0 0 0
DLCround-PT-13b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/187 2/32 DLCround-PT-13b-CTLFireability-00 97991 m, 15478 m/sec, 513401 t fired, .

Time elapsed: 50 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13b-CTLFireability-04: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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1 CTL EXCL 13/197 3/32 DLCround-PT-13b-CTLFireability-00 225260 m, 25453 m/sec, 1213975 t fired, .

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1 CTL EXCL 18/197 4/32 DLCround-PT-13b-CTLFireability-00 351096 m, 25167 m/sec, 1925622 t fired, .

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1 CTL EXCL 23/197 6/32 DLCround-PT-13b-CTLFireability-00 476524 m, 25085 m/sec, 2637310 t fired, .

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1 CTL EXCL 28/197 7/32 DLCround-PT-13b-CTLFireability-00 598884 m, 24472 m/sec, 3344112 t fired, .

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1 CTL EXCL 33/197 8/32 DLCround-PT-13b-CTLFireability-00 721107 m, 24444 m/sec, 4046704 t fired, .

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1 CTL EXCL 38/197 9/32 DLCround-PT-13b-CTLFireability-00 841172 m, 24013 m/sec, 4750190 t fired, .

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1 CTL EXCL 43/197 10/32 DLCround-PT-13b-CTLFireability-00 964511 m, 24667 m/sec, 5438684 t fired, .

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1 CTL EXCL 48/197 12/32 DLCround-PT-13b-CTLFireability-00 1086800 m, 24457 m/sec, 6135594 t fired, .

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1 CTL EXCL 53/197 13/32 DLCround-PT-13b-CTLFireability-00 1206140 m, 23868 m/sec, 6837411 t fired, .

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1 CTL EXCL 58/197 14/32 DLCround-PT-13b-CTLFireability-00 1329931 m, 24758 m/sec, 7523384 t fired, .

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55 CTL EXCL 10/213 5/32 DLCround-PT-13b-CTLFireability-14 246767 m, 24725 m/sec, 521081 t fired, .

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55 CTL EXCL 15/213 7/32 DLCround-PT-13b-CTLFireability-14 369924 m, 24631 m/sec, 780301 t fired, .

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55 CTL EXCL 20/213 9/32 DLCround-PT-13b-CTLFireability-14 493581 m, 24731 m/sec, 1041265 t fired, .

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55 CTL EXCL 25/213 11/32 DLCround-PT-13b-CTLFireability-14 613930 m, 24069 m/sec, 1298851 t fired, .

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55 CTL EXCL 80/213 32/32 DLCround-PT-13b-CTLFireability-14 1910201 m, 23439 m/sec, 4117916 t fired, .

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29 CTL EXCL 10/294 6/32 DLCround-PT-13b-CTLFireability-08 267177 m, 26597 m/sec, 559218 t fired, .

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14 CTL EXCL 20/383 10/32 DLCround-PT-13b-CTLFireability-03 577666 m, 28393 m/sec, 644571 t fired, .

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14 CTL EXCL 25/383 12/32 DLCround-PT-13b-CTLFireability-03 721223 m, 28711 m/sec, 805349 t fired, .

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4 CTL EXCL 15/500 6/32 DLCround-PT-13b-CTLFireability-01 270576 m, 18267 m/sec, 836960 t fired, .

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4 CTL EXCL 20/500 8/32 DLCround-PT-13b-CTLFireability-01 361052 m, 18095 m/sec, 1119304 t fired, .

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4 CTL EXCL 25/500 9/32 DLCround-PT-13b-CTLFireability-01 453084 m, 18406 m/sec, 1406963 t fired, .

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4 CTL EXCL 30/500 10/32 DLCround-PT-13b-CTLFireability-01 546556 m, 18694 m/sec, 1698857 t fired, .

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4 CTL EXCL 35/500 11/32 DLCround-PT-13b-CTLFireability-01 641817 m, 19052 m/sec, 1997123 t fired, .

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4 CTL EXCL 40/500 12/32 DLCround-PT-13b-CTLFireability-01 736086 m, 18853 m/sec, 2292828 t fired, .

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12 CTL EXCL 25/717 11/32 DLCround-PT-13b-CTLFireability-03 981413 m, 28499 m/sec, 2589596 t fired, .

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12 CTL EXCL 30/717 12/32 DLCround-PT-13b-CTLFireability-03 1136399 m, 30997 m/sec, 3015948 t fired, .

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12 CTL EXCL 35/717 14/32 DLCround-PT-13b-CTLFireability-03 1301635 m, 33047 m/sec, 3461055 t fired, .

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/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 488 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-13b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-13b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478800786"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-13b.tgz
mv DLCround-PT-13b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;