About the Execution of LoLa+red for DLCround-PT-13a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16225.735 | 347913.00 | 656766.00 | 6802.90 | T?TTT???F????TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478700778.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-13a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478700778
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 7.3K Feb 25 20:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 25 20:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 25 19:32 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 19:32 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.9K Feb 25 22:08 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 22:08 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 21:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 25 21:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 987K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-13a-CTLFireability-00
FORMULA_NAME DLCround-PT-13a-CTLFireability-01
FORMULA_NAME DLCround-PT-13a-CTLFireability-02
FORMULA_NAME DLCround-PT-13a-CTLFireability-03
FORMULA_NAME DLCround-PT-13a-CTLFireability-04
FORMULA_NAME DLCround-PT-13a-CTLFireability-05
FORMULA_NAME DLCround-PT-13a-CTLFireability-06
FORMULA_NAME DLCround-PT-13a-CTLFireability-07
FORMULA_NAME DLCround-PT-13a-CTLFireability-08
FORMULA_NAME DLCround-PT-13a-CTLFireability-09
FORMULA_NAME DLCround-PT-13a-CTLFireability-10
FORMULA_NAME DLCround-PT-13a-CTLFireability-11
FORMULA_NAME DLCround-PT-13a-CTLFireability-12
FORMULA_NAME DLCround-PT-13a-CTLFireability-13
FORMULA_NAME DLCround-PT-13a-CTLFireability-14
FORMULA_NAME DLCround-PT-13a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678279263070
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-13a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:41:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:41:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:41:04] [INFO ] Load time of PNML (sax parser for PT used): 156 ms
[2023-03-08 12:41:04] [INFO ] Transformed 463 places.
[2023-03-08 12:41:04] [INFO ] Transformed 3847 transitions.
[2023-03-08 12:41:04] [INFO ] Found NUPN structural information;
[2023-03-08 12:41:04] [INFO ] Parsed PT model containing 463 places and 3847 transitions and 15089 arcs in 250 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 18 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 352 transitions
Reduce redundant transitions removed 352 transitions.
FORMULA DLCround-PT-13a-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 186 out of 463 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 463/463 places, 3495/3495 transitions.
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 9 place count 454 transition count 3344
Iterating global reduction 0 with 9 rules applied. Total rules applied 18 place count 454 transition count 3344
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 20 place count 454 transition count 3342
Drop transitions removed 1234 transitions
Redundant transition composition rules discarded 1234 transitions
Iterating global reduction 1 with 1234 rules applied. Total rules applied 1254 place count 454 transition count 2108
Applied a total of 1254 rules in 320 ms. Remains 454 /463 variables (removed 9) and now considering 2108/3495 (removed 1387) transitions.
[2023-03-08 12:41:05] [INFO ] Flow matrix only has 255 transitions (discarded 1853 similar events)
// Phase 1: matrix 255 rows 454 cols
[2023-03-08 12:41:05] [INFO ] Computed 312 place invariants in 20 ms
[2023-03-08 12:41:06] [INFO ] Implicit Places using invariants in 1100 ms returned [160, 161, 162, 164, 165, 166, 167, 168, 170, 172, 173, 174, 176, 177, 179, 180, 182, 183, 184, 185, 186, 190, 194, 197, 198, 199, 200, 201, 202, 203, 204, 206, 208, 210, 211, 212, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 226, 228, 229, 230, 233, 234, 236, 237, 238, 239, 240, 244, 247, 248, 251, 252, 253, 255, 256, 257, 258, 260, 261, 263, 264, 268, 269, 270, 271, 272, 273, 274, 275, 277, 279, 280, 281, 282, 283, 284, 286, 287, 288, 290, 292, 293, 294, 295, 297, 299, 300, 301, 303, 304, 305, 306, 307, 309, 310, 311, 312, 313, 315, 318, 319, 320, 321, 325, 326, 328, 329, 330, 331, 333, 335, 336, 338, 339, 340, 341, 342, 344, 346, 347, 350, 353, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 368, 369, 371, 373, 376, 377, 378, 381, 382, 383, 384, 388, 392, 393, 396, 397, 399, 400, 401, 402, 404, 405, 406, 407, 408, 411, 412, 413, 415, 417, 418, 419, 420, 421, 422, 424, 425, 426, 427, 429, 430, 431, 432, 436, 439, 440, 441, 443, 447, 448, 449, 451, 453]
Discarding 197 places :
Ensure Unique test removed 1117 transitions
Reduce isomorphic transitions removed 1117 transitions.
Implicit Place search using SMT only with invariants took 1134 ms to find 197 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 257/463 places, 991/3495 transitions.
Drop transitions removed 646 transitions
Redundant transition composition rules discarded 646 transitions
Iterating global reduction 0 with 646 rules applied. Total rules applied 646 place count 257 transition count 345
Applied a total of 646 rules in 7 ms. Remains 257 /257 variables (removed 0) and now considering 345/991 (removed 646) transitions.
[2023-03-08 12:41:06] [INFO ] Flow matrix only has 255 transitions (discarded 90 similar events)
// Phase 1: matrix 255 rows 257 cols
[2023-03-08 12:41:06] [INFO ] Computed 115 place invariants in 3 ms
[2023-03-08 12:41:06] [INFO ] Implicit Places using invariants in 66 ms returned []
[2023-03-08 12:41:06] [INFO ] Flow matrix only has 255 transitions (discarded 90 similar events)
[2023-03-08 12:41:06] [INFO ] Invariant cache hit.
[2023-03-08 12:41:06] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 12:41:06] [INFO ] Implicit Places using invariants and state equation in 121 ms returned []
Implicit Place search using SMT with State Equation took 188 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 257/463 places, 345/3495 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1650 ms. Remains : 257/463 places, 345/3495 transitions.
Support contains 186 out of 257 places after structural reductions.
[2023-03-08 12:41:06] [INFO ] Flatten gal took : 47 ms
[2023-03-08 12:41:06] [INFO ] Flatten gal took : 19 ms
[2023-03-08 12:41:06] [INFO ] Input system was already deterministic with 345 transitions.
Support contains 183 out of 257 places (down from 186) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 418 ms. (steps per millisecond=23 ) properties (out of 99) seen :96
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-08 12:41:07] [INFO ] Flow matrix only has 255 transitions (discarded 90 similar events)
[2023-03-08 12:41:07] [INFO ] Invariant cache hit.
[2023-03-08 12:41:07] [INFO ] [Real]Absence check using 115 positive place invariants in 18 ms returned sat
[2023-03-08 12:41:07] [INFO ] After 148ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0
Fused 3 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 3 atomic propositions for a total of 15 simplifications.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 16 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 16 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 345 transitions.
Computed a total of 98 stabilizing places and 1 stable transitions
Graph (complete) has 459 edges and 257 vertex of which 160 are kept as prefixes of interest. Removing 97 places using SCC suffix rule.11 ms
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 90 places and 0 transitions.
Iterating post reduction 0 with 90 rules applied. Total rules applied 90 place count 167 transition count 345
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 115 place count 142 transition count 295
Iterating global reduction 1 with 25 rules applied. Total rules applied 140 place count 142 transition count 295
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 142 place count 142 transition count 293
Applied a total of 142 rules in 15 ms. Remains 142 /257 variables (removed 115) and now considering 293/345 (removed 52) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 142/257 places, 293/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 16 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 293 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 89 places and 0 transitions.
Iterating post reduction 0 with 89 rules applied. Total rules applied 89 place count 168 transition count 345
Discarding 23 places :
Symmetric choice reduction at 1 with 23 rule applications. Total rules 112 place count 145 transition count 299
Iterating global reduction 1 with 23 rules applied. Total rules applied 135 place count 145 transition count 299
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 137 place count 145 transition count 297
Applied a total of 137 rules in 4 ms. Remains 145 /257 variables (removed 112) and now considering 297/345 (removed 48) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 145/257 places, 297/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 12 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 297 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 319 edges and 257 vertex of which 138 / 257 are part of one of the 16 SCC in 3 ms
Free SCC test removed 122 places
Ensure Unique test removed 283 transitions
Reduce isomorphic transitions removed 283 transitions.
Graph (complete) has 176 edges and 135 vertex of which 41 are kept as prefixes of interest. Removing 94 places using SCC suffix rule.0 ms
Discarding 94 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 41 transition count 61
Reduce places removed 1 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 3 rules applied. Total rules applied 6 place count 40 transition count 59
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 8 place count 38 transition count 59
Discarding 18 places :
Symmetric choice reduction at 3 with 18 rule applications. Total rules 26 place count 20 transition count 37
Iterating global reduction 3 with 18 rules applied. Total rules applied 44 place count 20 transition count 37
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 48 place count 20 transition count 33
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 52 place count 18 transition count 31
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 53 place count 18 transition count 30
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 54 place count 18 transition count 30
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 55 place count 17 transition count 29
Iterating global reduction 5 with 1 rules applied. Total rules applied 56 place count 17 transition count 29
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 57 place count 17 transition count 28
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 6 with 1 rules applied. Total rules applied 58 place count 17 transition count 27
Applied a total of 58 rules in 16 ms. Remains 17 /257 variables (removed 240) and now considering 27/345 (removed 318) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 17/257 places, 27/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 27 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 331 edges and 257 vertex of which 147 / 257 are part of one of the 18 SCC in 1 ms
Free SCC test removed 129 places
Ensure Unique test removed 297 transitions
Reduce isomorphic transitions removed 297 transitions.
Graph (complete) has 162 edges and 128 vertex of which 33 are kept as prefixes of interest. Removing 95 places using SCC suffix rule.1 ms
Discarding 95 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 33 transition count 46
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 31 transition count 46
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 21 place count 16 transition count 31
Iterating global reduction 2 with 15 rules applied. Total rules applied 36 place count 16 transition count 31
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 2 with 3 rules applied. Total rules applied 39 place count 16 transition count 28
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 40 place count 16 transition count 28
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 15 transition count 27
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 15 transition count 27
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 43 place count 15 transition count 26
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 44 place count 15 transition count 25
Applied a total of 44 rules in 7 ms. Remains 15 /257 variables (removed 242) and now considering 25/345 (removed 320) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 15/257 places, 25/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 342 edges and 257 vertex of which 157 / 257 are part of one of the 18 SCC in 1 ms
Free SCC test removed 139 places
Ensure Unique test removed 322 transitions
Reduce isomorphic transitions removed 322 transitions.
Graph (complete) has 137 edges and 118 vertex of which 22 are kept as prefixes of interest. Removing 96 places using SCC suffix rule.1 ms
Discarding 96 places :
Also discarding 0 output transitions
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 18 place count 6 transition count 7
Iterating global reduction 0 with 16 rules applied. Total rules applied 34 place count 6 transition count 7
Applied a total of 34 rules in 2 ms. Remains 6 /257 variables (removed 251) and now considering 7/345 (removed 338) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 6/257 places, 7/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 7 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
FORMULA DLCround-PT-13a-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 88 places and 0 transitions.
Iterating post reduction 0 with 88 rules applied. Total rules applied 88 place count 169 transition count 345
Discarding 24 places :
Symmetric choice reduction at 1 with 24 rule applications. Total rules 112 place count 145 transition count 297
Iterating global reduction 1 with 24 rules applied. Total rules applied 136 place count 145 transition count 297
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 138 place count 145 transition count 295
Applied a total of 138 rules in 4 ms. Remains 145 /257 variables (removed 112) and now considering 295/345 (removed 50) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 145/257 places, 295/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 295 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 74 places and 0 transitions.
Iterating post reduction 0 with 74 rules applied. Total rules applied 74 place count 183 transition count 345
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 94 place count 163 transition count 305
Iterating global reduction 1 with 20 rules applied. Total rules applied 114 place count 163 transition count 305
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 115 place count 163 transition count 304
Applied a total of 115 rules in 4 ms. Remains 163 /257 variables (removed 94) and now considering 304/345 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 163/257 places, 304/345 transitions.
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:41:07] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:41:07] [INFO ] Input system was already deterministic with 304 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 313 edges and 257 vertex of which 137 / 257 are part of one of the 18 SCC in 1 ms
Free SCC test removed 119 places
Ensure Unique test removed 274 transitions
Reduce isomorphic transitions removed 274 transitions.
Graph (complete) has 185 edges and 138 vertex of which 47 are kept as prefixes of interest. Removing 91 places using SCC suffix rule.1 ms
Discarding 91 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 47 transition count 69
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 45 transition count 69
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 19 place count 32 transition count 54
Iterating global reduction 2 with 13 rules applied. Total rules applied 32 place count 32 transition count 54
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 32 transition count 52
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 36 place count 32 transition count 52
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 38 place count 30 transition count 50
Iterating global reduction 2 with 2 rules applied. Total rules applied 40 place count 30 transition count 50
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 42 place count 30 transition count 48
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 44 place count 30 transition count 46
Applied a total of 44 rules in 18 ms. Remains 30 /257 variables (removed 227) and now considering 46/345 (removed 299) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 30/257 places, 46/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 89 places and 0 transitions.
Iterating post reduction 0 with 89 rules applied. Total rules applied 89 place count 168 transition count 345
Discarding 24 places :
Symmetric choice reduction at 1 with 24 rule applications. Total rules 113 place count 144 transition count 297
Iterating global reduction 1 with 24 rules applied. Total rules applied 137 place count 144 transition count 297
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 139 place count 144 transition count 295
Applied a total of 139 rules in 4 ms. Remains 144 /257 variables (removed 113) and now considering 295/345 (removed 50) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 144/257 places, 295/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 295 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 97 places and 0 transitions.
Iterating post reduction 0 with 97 rules applied. Total rules applied 97 place count 160 transition count 345
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 124 place count 133 transition count 291
Iterating global reduction 1 with 27 rules applied. Total rules applied 151 place count 133 transition count 291
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 153 place count 133 transition count 289
Applied a total of 153 rules in 9 ms. Remains 133 /257 variables (removed 124) and now considering 289/345 (removed 56) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 133/257 places, 289/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 289 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 74 places and 0 transitions.
Iterating post reduction 0 with 74 rules applied. Total rules applied 74 place count 183 transition count 345
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 92 place count 165 transition count 309
Iterating global reduction 1 with 18 rules applied. Total rules applied 110 place count 165 transition count 309
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 111 place count 165 transition count 308
Applied a total of 111 rules in 17 ms. Remains 165 /257 variables (removed 92) and now considering 308/345 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 165/257 places, 308/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 21 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 308 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 338 edges and 257 vertex of which 155 / 257 are part of one of the 18 SCC in 1 ms
Free SCC test removed 137 places
Ensure Unique test removed 318 transitions
Reduce isomorphic transitions removed 318 transitions.
Graph (complete) has 141 edges and 120 vertex of which 24 are kept as prefixes of interest. Removing 96 places using SCC suffix rule.1 ms
Discarding 96 places :
Also discarding 0 output transitions
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 17 place count 9 transition count 12
Iterating global reduction 0 with 15 rules applied. Total rules applied 32 place count 9 transition count 12
Applied a total of 32 rules in 3 ms. Remains 9 /257 variables (removed 248) and now considering 12/345 (removed 333) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 9/257 places, 12/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 80 places and 0 transitions.
Iterating post reduction 0 with 80 rules applied. Total rules applied 80 place count 177 transition count 345
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 102 place count 155 transition count 301
Iterating global reduction 1 with 22 rules applied. Total rules applied 124 place count 155 transition count 301
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 126 place count 155 transition count 299
Applied a total of 126 rules in 4 ms. Remains 155 /257 variables (removed 102) and now considering 299/345 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 155/257 places, 299/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 11 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 299 transitions.
Starting structural reductions in LTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Reduce places removed 95 places and 0 transitions.
Iterating post reduction 0 with 95 rules applied. Total rules applied 95 place count 162 transition count 345
Discarding 26 places :
Symmetric choice reduction at 1 with 26 rule applications. Total rules 121 place count 136 transition count 293
Iterating global reduction 1 with 26 rules applied. Total rules applied 147 place count 136 transition count 293
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 149 place count 136 transition count 291
Applied a total of 149 rules in 14 ms. Remains 136 /257 variables (removed 121) and now considering 291/345 (removed 54) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 136/257 places, 291/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 19 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 291 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 257/257 places, 345/345 transitions.
Graph (trivial) has 341 edges and 257 vertex of which 157 / 257 are part of one of the 18 SCC in 1 ms
Free SCC test removed 139 places
Ensure Unique test removed 322 transitions
Reduce isomorphic transitions removed 322 transitions.
Graph (complete) has 137 edges and 118 vertex of which 22 are kept as prefixes of interest. Removing 96 places using SCC suffix rule.1 ms
Discarding 96 places :
Also discarding 0 output transitions
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 22 transition count 22
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 21 transition count 21
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 21 place count 5 transition count 5
Iterating global reduction 2 with 16 rules applied. Total rules applied 37 place count 5 transition count 5
Applied a total of 37 rules in 3 ms. Remains 5 /257 variables (removed 252) and now considering 5/345 (removed 340) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 5/257 places, 5/345 transitions.
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 0 ms
[2023-03-08 12:41:08] [INFO ] Input system was already deterministic with 5 transitions.
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
FORMULA DLCround-PT-13a-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:41:08] [INFO ] Flatten gal took : 9 ms
[2023-03-08 12:41:08] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 12:41:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 257 places, 345 transitions and 804 arcs took 2 ms.
Total runtime 3904 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-13a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/366
CTLFireability
FORMULA DLCround-PT-13a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-13a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-13a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-13a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-13a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678279610983
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/366/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/366/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/366/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 43 (type SKEL/SRCH) for 6 DLCround-PT-13a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 43 (type SKEL/SRCH) for DLCround-PT-13a-CTLFireability-02
lola: result : true
lola: markings : 14
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 11 (type EXCL) for 6 DLCround-PT-13a-CTLFireability-02
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 11 (type EXCL) for DLCround-PT-13a-CTLFireability-02
lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DLCround-PT-13a-CTLFireability-03
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 14 (type EXCL) for DLCround-PT-13a-CTLFireability-03
lola: result : true
lola: markings : 36
lola: fired transitions : 997
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-13a-CTLFireability-00
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 45 (type FNDP) for 28 DLCround-PT-13a-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-13a-CTLFireability-00
lola: result : true
lola: markings : 970467
lola: fired transitions : 3238149
lola: time used : 5.000000
lola: memory pages used : 5
lola: LAUNCH task # 41 (type EXCL) for 40 DLCround-PT-13a-CTLFireability-13
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for DLCround-PT-13a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 DLCround-PT-13a-CTLFireability-12
lola: time limit : 399 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 0/399 1/32 DLCround-PT-13a-CTLFireability-12 132616 m, 26523 m/sec, 435875 t fired, .
45 EF DL FNDP 5/3600 0/5 DLCround-PT-13a-CTLFireability-09 102353572 t fired, 103 attempts, .
Time elapsed: 5 secs. Pages in use: 5
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/399 6/32 DLCround-PT-13a-CTLFireability-12 1229255 m, 219327 m/sec, 4118253 t fired, .
45 EF DL FNDP 10/3600 0/5 DLCround-PT-13a-CTLFireability-09 206888304 t fired, 207 attempts, .
Time elapsed: 10 secs. Pages in use: 6
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/399 10/32 DLCround-PT-13a-CTLFireability-12 2290304 m, 212209 m/sec, 7734889 t fired, .
45 EF DL FNDP 15/3600 0/5 DLCround-PT-13a-CTLFireability-09 311879537 t fired, 312 attempts, .
Time elapsed: 15 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/399 15/32 DLCround-PT-13a-CTLFireability-12 3336458 m, 209230 m/sec, 11318186 t fired, .
45 EF DL FNDP 20/3600 0/5 DLCround-PT-13a-CTLFireability-09 416588696 t fired, 417 attempts, .
Time elapsed: 20 secs. Pages in use: 15
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/399 19/32 DLCround-PT-13a-CTLFireability-12 4373092 m, 207326 m/sec, 14887445 t fired, .
45 EF DL FNDP 25/3600 0/5 DLCround-PT-13a-CTLFireability-09 521003873 t fired, 522 attempts, .
Time elapsed: 25 secs. Pages in use: 19
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/399 24/32 DLCround-PT-13a-CTLFireability-12 5378145 m, 201010 m/sec, 18391677 t fired, .
45 EF DL FNDP 30/3600 0/5 DLCround-PT-13a-CTLFireability-09 625750480 t fired, 626 attempts, .
Time elapsed: 30 secs. Pages in use: 24
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/399 28/32 DLCround-PT-13a-CTLFireability-12 6414777 m, 207326 m/sec, 21948904 t fired, .
45 EF DL FNDP 35/3600 0/5 DLCround-PT-13a-CTLFireability-09 730765967 t fired, 731 attempts, .
Time elapsed: 35 secs. Pages in use: 28
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/399 32/32 DLCround-PT-13a-CTLFireability-12 7373451 m, 191734 m/sec, 25312414 t fired, .
45 EF DL FNDP 40/3600 0/5 DLCround-PT-13a-CTLFireability-09 835662525 t fired, 836 attempts, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: CANCELED task # 38 (type EXCL) for DLCround-PT-13a-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EF DL FNDP 45/3600 0/5 DLCround-PT-13a-CTLFireability-09 942850982 t fired, 943 attempts, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-13a-CTLFireability-10
lola: time limit : 444 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/444 3/32 DLCround-PT-13a-CTLFireability-10 636770 m, 127354 m/sec, 3358583 t fired, .
45 EF DL FNDP 50/3600 0/5 DLCround-PT-13a-CTLFireability-09 1048306357 t fired, 1049 attempts, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/444 6/32 DLCround-PT-13a-CTLFireability-10 1267788 m, 126203 m/sec, 6537924 t fired, .
45 EF DL FNDP 55/3600 0/5 DLCround-PT-13a-CTLFireability-09 1153281085 t fired, 1154 attempts, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/444 9/32 DLCround-PT-13a-CTLFireability-10 1910561 m, 128554 m/sec, 9753899 t fired, .
45 EF DL FNDP 60/3600 0/5 DLCround-PT-13a-CTLFireability-09 1260187988 t fired, 1261 attempts, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/444 11/32 DLCround-PT-13a-CTLFireability-10 2557084 m, 129304 m/sec, 13003495 t fired, .
45 EF DL FNDP 65/3600 0/5 DLCround-PT-13a-CTLFireability-09 1367177134 t fired, 1368 attempts, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/444 14/32 DLCround-PT-13a-CTLFireability-10 3139334 m, 116450 m/sec, 16148980 t fired, .
45 EF DL FNDP 70/3600 0/5 DLCround-PT-13a-CTLFireability-09 1473944337 t fired, 1474 attempts, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/444 16/32 DLCround-PT-13a-CTLFireability-10 3734051 m, 118943 m/sec, 19289200 t fired, .
45 EF DL FNDP 75/3600 0/5 DLCround-PT-13a-CTLFireability-09 1580856990 t fired, 1581 attempts, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/444 19/32 DLCround-PT-13a-CTLFireability-10 4357517 m, 124693 m/sec, 22532545 t fired, .
45 EF DL FNDP 80/3600 0/5 DLCround-PT-13a-CTLFireability-09 1688002770 t fired, 1689 attempts, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/444 21/32 DLCround-PT-13a-CTLFireability-10 4935731 m, 115642 m/sec, 25790605 t fired, .
45 EF DL FNDP 85/3600 0/5 DLCround-PT-13a-CTLFireability-09 1794355785 t fired, 1795 attempts, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/444 24/32 DLCround-PT-13a-CTLFireability-10 5564122 m, 125678 m/sec, 28882930 t fired, .
45 EF DL FNDP 90/3600 0/5 DLCround-PT-13a-CTLFireability-09 1900227935 t fired, 1901 attempts, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/444 27/32 DLCround-PT-13a-CTLFireability-10 6146090 m, 116393 m/sec, 32030376 t fired, .
45 EF DL FNDP 95/3600 0/5 DLCround-PT-13a-CTLFireability-09 2009838112 t fired, 2010 attempts, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 55/444 29/32 DLCround-PT-13a-CTLFireability-10 6672989 m, 105379 m/sec, 35141391 t fired, .
45 EF DL FNDP 100/3600 0/5 DLCround-PT-13a-CTLFireability-09 2116723395 t fired, 2117 attempts, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 60/444 31/32 DLCround-PT-13a-CTLFireability-10 7230122 m, 111426 m/sec, 38278287 t fired, .
45 EF DL FNDP 105/3600 0/5 DLCround-PT-13a-CTLFireability-09 -2071329794 t fired, 2224 attempts, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: CANCELED task # 32 (type EXCL) for DLCround-PT-13a-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EF DL FNDP 110/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1962710617 t fired, 2333 attempts, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-13a-CTLFireability-08
lola: time limit : 498 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for DLCround-PT-13a-CTLFireability-08
lola: result : false
lola: markings : 48
lola: fired transitions : 150
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-13a-CTLFireability-06
lola: time limit : 581 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/581 6/32 DLCround-PT-13a-CTLFireability-06 1191440 m, 238288 m/sec, 3990779 t fired, .
45 EF DL FNDP 115/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1855042264 t fired, 2440 attempts, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/581 10/32 DLCround-PT-13a-CTLFireability-06 2275721 m, 216856 m/sec, 7682804 t fired, .
45 EF DL FNDP 120/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1748775149 t fired, 2547 attempts, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/581 15/32 DLCround-PT-13a-CTLFireability-06 3341248 m, 213105 m/sec, 11333943 t fired, .
45 EF DL FNDP 125/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1643061003 t fired, 2652 attempts, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/581 19/32 DLCround-PT-13a-CTLFireability-06 4397720 m, 211294 m/sec, 14975203 t fired, .
45 EF DL FNDP 130/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1537960417 t fired, 2758 attempts, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/581 24/32 DLCround-PT-13a-CTLFireability-06 5430272 m, 206510 m/sec, 18564509 t fired, .
45 EF DL FNDP 135/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1432042670 t fired, 2863 attempts, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/581 28/32 DLCround-PT-13a-CTLFireability-06 6490253 m, 211996 m/sec, 22213287 t fired, .
45 EF DL FNDP 140/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1326277217 t fired, 2969 attempts, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/581 32/32 DLCround-PT-13a-CTLFireability-06 7475563 m, 197062 m/sec, 25656719 t fired, .
45 EF DL FNDP 145/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1221094102 t fired, 3074 attempts, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: CANCELED task # 20 (type EXCL) for DLCround-PT-13a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EF DL FNDP 150/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1112433964 t fired, 3183 attempts, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: LAUNCH task # 17 (type EXCL) for 16 DLCround-PT-13a-CTLFireability-05
lola: time limit : 690 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/690 3/32 DLCround-PT-13a-CTLFireability-05 554893 m, 110978 m/sec, 2855760 t fired, .
45 EF DL FNDP 155/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1005250332 t fired, 3290 attempts, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/690 5/32 DLCround-PT-13a-CTLFireability-05 1044848 m, 97991 m/sec, 5561335 t fired, .
45 EF DL FNDP 160/3600 0/5 DLCround-PT-13a-CTLFireability-09 -897533652 t fired, 3398 attempts, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/690 7/32 DLCround-PT-13a-CTLFireability-05 1534560 m, 97942 m/sec, 8065425 t fired, .
45 EF DL FNDP 165/3600 0/5 DLCround-PT-13a-CTLFireability-09 -791593957 t fired, 3504 attempts, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/690 9/32 DLCround-PT-13a-CTLFireability-05 2028805 m, 98849 m/sec, 10637063 t fired, .
45 EF DL FNDP 170/3600 0/5 DLCround-PT-13a-CTLFireability-09 -685698593 t fired, 3610 attempts, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/690 11/32 DLCround-PT-13a-CTLFireability-05 2465990 m, 87437 m/sec, 13056389 t fired, .
45 EF DL FNDP 175/3600 0/5 DLCround-PT-13a-CTLFireability-09 -581433806 t fired, 3714 attempts, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/690 13/32 DLCround-PT-13a-CTLFireability-05 2912856 m, 89373 m/sec, 15545285 t fired, .
45 EF DL FNDP 180/3600 0/5 DLCround-PT-13a-CTLFireability-09 -476443629 t fired, 3819 attempts, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 35/690 15/32 DLCround-PT-13a-CTLFireability-05 3362229 m, 89874 m/sec, 18001380 t fired, .
45 EF DL FNDP 185/3600 0/5 DLCround-PT-13a-CTLFireability-09 -370685024 t fired, 3925 attempts, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 40/690 17/32 DLCround-PT-13a-CTLFireability-05 3838281 m, 95210 m/sec, 20590526 t fired, .
45 EF DL FNDP 190/3600 0/5 DLCround-PT-13a-CTLFireability-09 -264465558 t fired, 4031 attempts, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 45/690 19/32 DLCround-PT-13a-CTLFireability-05 4298193 m, 91982 m/sec, 23001441 t fired, .
45 EF DL FNDP 195/3600 0/5 DLCround-PT-13a-CTLFireability-09 -159226738 t fired, 4136 attempts, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 50/690 21/32 DLCround-PT-13a-CTLFireability-05 4726851 m, 85731 m/sec, 25441078 t fired, .
45 EF DL FNDP 200/3600 0/5 DLCround-PT-13a-CTLFireability-09 -52044734 t fired, 4243 attempts, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 55/690 23/32 DLCround-PT-13a-CTLFireability-05 5144403 m, 83510 m/sec, 27825982 t fired, .
45 EF DL FNDP 205/3600 0/5 DLCround-PT-13a-CTLFireability-09 55318590 t fired, 4351 attempts, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 60/690 25/32 DLCround-PT-13a-CTLFireability-05 5599309 m, 90981 m/sec, 30258336 t fired, .
45 EF DL FNDP 210/3600 0/5 DLCround-PT-13a-CTLFireability-09 163259788 t fired, 4459 attempts, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 65/690 27/32 DLCround-PT-13a-CTLFireability-05 6030214 m, 86181 m/sec, 32749877 t fired, .
45 EF DL FNDP 215/3600 0/5 DLCround-PT-13a-CTLFireability-09 270930474 t fired, 4566 attempts, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 70/690 29/32 DLCround-PT-13a-CTLFireability-05 6461043 m, 86165 m/sec, 35225743 t fired, .
45 EF DL FNDP 220/3600 0/5 DLCround-PT-13a-CTLFireability-09 378993357 t fired, 4674 attempts, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 75/690 31/32 DLCround-PT-13a-CTLFireability-05 6909975 m, 89786 m/sec, 37719279 t fired, .
45 EF DL FNDP 225/3600 0/5 DLCround-PT-13a-CTLFireability-09 486805733 t fired, 4782 attempts, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: CANCELED task # 17 (type EXCL) for DLCround-PT-13a-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EF DL FNDP 230/3600 0/5 DLCround-PT-13a-CTLFireability-09 592097426 t fired, 4888 attempts, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-13a-CTLFireability-01
lola: time limit : 842 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/842 5/32 DLCround-PT-13a-CTLFireability-01 941001 m, 188200 m/sec, 4082142 t fired, .
45 EF DL FNDP 235/3600 0/5 DLCround-PT-13a-CTLFireability-09 696513210 t fired, 4992 attempts, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/842 8/32 DLCround-PT-13a-CTLFireability-01 1818054 m, 175410 m/sec, 7948642 t fired, .
45 EF DL FNDP 240/3600 0/5 DLCround-PT-13a-CTLFireability-09 800989837 t fired, 5096 attempts, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/842 12/32 DLCround-PT-13a-CTLFireability-01 2671016 m, 170592 m/sec, 11692970 t fired, .
45 EF DL FNDP 245/3600 0/5 DLCround-PT-13a-CTLFireability-09 906295828 t fired, 5202 attempts, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/842 16/32 DLCround-PT-13a-CTLFireability-01 3499240 m, 165644 m/sec, 15382868 t fired, .
45 EF DL FNDP 250/3600 0/5 DLCround-PT-13a-CTLFireability-09 1010801863 t fired, 5306 attempts, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/842 19/32 DLCround-PT-13a-CTLFireability-01 4315388 m, 163229 m/sec, 19005366 t fired, .
45 EF DL FNDP 255/3600 0/5 DLCround-PT-13a-CTLFireability-09 1115670366 t fired, 5411 attempts, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/842 23/32 DLCround-PT-13a-CTLFireability-01 5162902 m, 169502 m/sec, 22804821 t fired, .
45 EF DL FNDP 260/3600 0/5 DLCround-PT-13a-CTLFireability-09 1222888694 t fired, 5518 attempts, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/842 27/32 DLCround-PT-13a-CTLFireability-01 6016239 m, 170667 m/sec, 26612492 t fired, .
45 EF DL FNDP 265/3600 0/5 DLCround-PT-13a-CTLFireability-09 1330134637 t fired, 5626 attempts, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/842 30/32 DLCround-PT-13a-CTLFireability-01 6818107 m, 160373 m/sec, 30167860 t fired, .
45 EF DL FNDP 270/3600 0/5 DLCround-PT-13a-CTLFireability-09 1436648087 t fired, 5732 attempts, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: CANCELED task # 4 (type EXCL) for DLCround-PT-13a-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 1 1 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 EF DL FNDP 275/3600 0/5 DLCround-PT-13a-CTLFireability-09 1542511442 t fired, 5838 attempts, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
lola: LAUNCH task # 44 (type EXCL) for 28 DLCround-PT-13a-CTLFireability-09
lola: time limit : 1108 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 5/1108 1/32 DLCround-PT-13a-CTLFireability-09 35115753 m, 7023150 m/sec, 35115752 t fired, .
45 EF DL FNDP 280/3600 0/5 DLCround-PT-13a-CTLFireability-09 1647349542 t fired, 5943 attempts, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 10/1108 1/32 DLCround-PT-13a-CTLFireability-09 69549094 m, 6886668 m/sec, 69549094 t fired, .
45 EF DL FNDP 285/3600 0/5 DLCround-PT-13a-CTLFireability-09 1752258519 t fired, 6048 attempts, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 15/1108 1/32 DLCround-PT-13a-CTLFireability-09 103896799 m, 6869541 m/sec, 103896799 t fired, .
45 EF DL FNDP 290/3600 0/5 DLCround-PT-13a-CTLFireability-09 1856927213 t fired, 6152 attempts, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 20/1108 1/32 DLCround-PT-13a-CTLFireability-09 138272855 m, 6875211 m/sec, 138272855 t fired, .
45 EF DL FNDP 295/3600 0/5 DLCround-PT-13a-CTLFireability-09 1961579111 t fired, 6257 attempts, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 25/1108 1/32 DLCround-PT-13a-CTLFireability-09 172465663 m, 6838561 m/sec, 172465663 t fired, .
45 EF DL FNDP 300/3600 0/5 DLCround-PT-13a-CTLFireability-09 2066126838 t fired, 6362 attempts, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 30/1108 1/32 DLCround-PT-13a-CTLFireability-09 193432214 m, 4193310 m/sec, 193432214 t fired, .
45 EF DL FNDP 305/3600 0/5 DLCround-PT-13a-CTLFireability-09 -2125393431 t fired, 6465 attempts, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 35/1108 1/32 DLCround-PT-13a-CTLFireability-09 205251309 m, 2363819 m/sec, 205251308 t fired, .
45 EF DL FNDP 310/3600 0/5 DLCround-PT-13a-CTLFireability-09 -2027820380 t fired, 6563 attempts, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 40/1108 1/32 DLCround-PT-13a-CTLFireability-09 216371196 m, 2223977 m/sec, 216371195 t fired, .
45 EF DL FNDP 315/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1931512505 t fired, 6659 attempts, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 45/1108 1/32 DLCround-PT-13a-CTLFireability-09 227492734 m, 2224307 m/sec, 227492733 t fired, .
45 EF DL FNDP 320/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1836365403 t fired, 6754 attempts, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 50/1108 1/32 DLCround-PT-13a-CTLFireability-09 239790757 m, 2459604 m/sec, 239790756 t fired, .
45 EF DL FNDP 325/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1741809822 t fired, 6849 attempts, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 55/1108 1/32 DLCround-PT-13a-CTLFireability-09 256646830 m, 3371214 m/sec, 256646829 t fired, .
45 EF DL FNDP 330/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1650728094 t fired, 6940 attempts, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-13a-CTLFireability-00: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-02: DISJ true state space /EFEG
DLCround-PT-13a-CTLFireability-03: CTL true CTL model checker
DLCround-PT-13a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-13a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-13a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-09: EF DL 0 0 2 0 1 0 0 0
DLCround-PT-13a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-13a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-13a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 EF DL EXCL 60/1108 1/32 DLCround-PT-13a-CTLFireability-09 268629631 m, 2396560 m/sec, 268629630 t fired, .
45 EF DL FNDP 335/3600 0/5 DLCround-PT-13a-CTLFireability-09 -1552543484 t fired, 7038 attempts, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 13
/home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 461 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-13a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-13a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478700778"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-13a.tgz
mv DLCround-PT-13a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;