Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478700746.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-11a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478700746
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.7K Feb 25 20:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 20:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 19:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 19:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 21:07 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Feb 25 21:07 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 20:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 25 20:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 762K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-11a-CTLFireability-00
FORMULA_NAME DLCround-PT-11a-CTLFireability-01
FORMULA_NAME DLCround-PT-11a-CTLFireability-02
FORMULA_NAME DLCround-PT-11a-CTLFireability-03
FORMULA_NAME DLCround-PT-11a-CTLFireability-04
FORMULA_NAME DLCround-PT-11a-CTLFireability-05
FORMULA_NAME DLCround-PT-11a-CTLFireability-06
FORMULA_NAME DLCround-PT-11a-CTLFireability-07
FORMULA_NAME DLCround-PT-11a-CTLFireability-08
FORMULA_NAME DLCround-PT-11a-CTLFireability-09
FORMULA_NAME DLCround-PT-11a-CTLFireability-10
FORMULA_NAME DLCround-PT-11a-CTLFireability-11
FORMULA_NAME DLCround-PT-11a-CTLFireability-12
FORMULA_NAME DLCround-PT-11a-CTLFireability-13
FORMULA_NAME DLCround-PT-11a-CTLFireability-14
FORMULA_NAME DLCround-PT-11a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678277868764

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-11a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:17:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:17:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:17:50] [INFO ] Load time of PNML (sax parser for PT used): 121 ms
[2023-03-08 12:17:50] [INFO ] Transformed 377 places.
[2023-03-08 12:17:50] [INFO ] Transformed 2993 transitions.
[2023-03-08 12:17:50] [INFO ] Found NUPN structural information;
[2023-03-08 12:17:50] [INFO ] Parsed PT model containing 377 places and 2993 transitions and 11677 arcs in 197 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
Ensure Unique test removed 280 transitions
Reduce redundant transitions removed 280 transitions.
FORMULA DLCround-PT-11a-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-11a-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 136 out of 377 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 377/377 places, 2713/2713 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 365 transition count 2529
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 365 transition count 2529
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 27 place count 365 transition count 2526
Drop transitions removed 891 transitions
Redundant transition composition rules discarded 891 transitions
Iterating global reduction 1 with 891 rules applied. Total rules applied 918 place count 365 transition count 1635
Applied a total of 918 rules in 106 ms. Remains 365 /377 variables (removed 12) and now considering 1635/2713 (removed 1078) transitions.
[2023-03-08 12:17:50] [INFO ] Flow matrix only has 219 transitions (discarded 1416 similar events)
// Phase 1: matrix 219 rows 365 cols
[2023-03-08 12:17:50] [INFO ] Computed 244 place invariants in 20 ms
[2023-03-08 12:17:51] [INFO ] Implicit Places using invariants in 889 ms returned [137, 139, 141, 143, 145, 147, 148, 151, 152, 153, 154, 156, 157, 159, 161, 162, 163, 164, 165, 166, 167, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 183, 185, 186, 187, 189, 191, 193, 195, 196, 197, 198, 200, 201, 203, 205, 208, 209, 210, 211, 213, 215, 216, 217, 221, 224, 225, 226, 227, 229, 231, 232, 233, 235, 237, 240, 241, 242, 244, 245, 246, 248, 249, 250, 251, 253, 254, 256, 257, 258, 259, 261, 264, 265, 266, 268, 269, 270, 272, 274, 277, 278, 279, 280, 282, 285, 286, 287, 288, 289, 292, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 309, 310, 312, 313, 314, 315, 316, 317, 319, 320, 321, 322, 323, 324, 325, 327, 331, 334, 335, 336, 337, 340, 343, 344, 345, 346, 347, 348, 350, 351, 352, 353, 355, 357, 358, 359, 360, 361, 363, 364]
Discarding 157 places :
Ensure Unique test removed 864 transitions
Reduce isomorphic transitions removed 864 transitions.
Implicit Place search using SMT only with invariants took 920 ms to find 157 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 208/377 places, 771/2713 transitions.
Drop transitions removed 477 transitions
Redundant transition composition rules discarded 477 transitions
Iterating global reduction 0 with 477 rules applied. Total rules applied 477 place count 208 transition count 294
Applied a total of 477 rules in 8 ms. Remains 208 /208 variables (removed 0) and now considering 294/771 (removed 477) transitions.
[2023-03-08 12:17:51] [INFO ] Flow matrix only has 219 transitions (discarded 75 similar events)
// Phase 1: matrix 219 rows 208 cols
[2023-03-08 12:17:51] [INFO ] Computed 87 place invariants in 1 ms
[2023-03-08 12:17:51] [INFO ] Implicit Places using invariants in 64 ms returned []
[2023-03-08 12:17:51] [INFO ] Flow matrix only has 219 transitions (discarded 75 similar events)
[2023-03-08 12:17:51] [INFO ] Invariant cache hit.
[2023-03-08 12:17:51] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 12:17:51] [INFO ] Implicit Places using invariants and state equation in 111 ms returned []
Implicit Place search using SMT with State Equation took 178 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 208/377 places, 294/2713 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1213 ms. Remains : 208/377 places, 294/2713 transitions.
Support contains 136 out of 208 places after structural reductions.
[2023-03-08 12:17:51] [INFO ] Flatten gal took : 36 ms
[2023-03-08 12:17:51] [INFO ] Flatten gal took : 15 ms
[2023-03-08 12:17:51] [INFO ] Input system was already deterministic with 294 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 174 ms. (steps per millisecond=57 ) properties (out of 69) seen :68
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 12:17:52] [INFO ] Flow matrix only has 219 transitions (discarded 75 similar events)
[2023-03-08 12:17:52] [INFO ] Invariant cache hit.
[2023-03-08 12:17:52] [INFO ] After 57ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 12:17:52] [INFO ] [Nat]Absence check using 87 positive place invariants in 19 ms returned sat
[2023-03-08 12:17:52] [INFO ] After 81ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 14 simplifications.
FORMULA DLCround-PT-11a-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 19 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 12 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 294 transitions.
Computed a total of 72 stabilizing places and 1 stable transitions
Graph (complete) has 380 edges and 208 vertex of which 137 are kept as prefixes of interest. Removing 71 places using SCC suffix rule.3 ms
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 142 transition count 294
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 83 place count 125 transition count 260
Iterating global reduction 1 with 17 rules applied. Total rules applied 100 place count 125 transition count 260
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 101 place count 125 transition count 259
Applied a total of 101 rules in 5 ms. Remains 125 /208 variables (removed 83) and now considering 259/294 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 125/208 places, 259/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 13 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 259 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 63 places and 0 transitions.
Iterating post reduction 0 with 63 rules applied. Total rules applied 63 place count 145 transition count 294
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 79 place count 129 transition count 262
Iterating global reduction 1 with 16 rules applied. Total rules applied 95 place count 129 transition count 262
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 96 place count 129 transition count 261
Applied a total of 96 rules in 5 ms. Remains 129 /208 variables (removed 79) and now considering 261/294 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 129/208 places, 261/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 261 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Graph (trivial) has 247 edges and 208 vertex of which 106 / 208 are part of one of the 14 SCC in 3 ms
Free SCC test removed 92 places
Ensure Unique test removed 209 transitions
Reduce isomorphic transitions removed 209 transitions.
Graph (complete) has 171 edges and 116 vertex of which 52 are kept as prefixes of interest. Removing 64 places using SCC suffix rule.1 ms
Discarding 64 places :
Also discarding 0 output transitions
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 5 place count 52 transition count 82
Reduce places removed 3 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 5 rules applied. Total rules applied 10 place count 49 transition count 80
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 13 place count 47 transition count 79
Discarding 9 places :
Symmetric choice reduction at 3 with 9 rule applications. Total rules 22 place count 38 transition count 69
Iterating global reduction 3 with 9 rules applied. Total rules applied 31 place count 38 transition count 69
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 3 with 5 rules applied. Total rules applied 36 place count 38 transition count 64
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 3 with 3 rules applied. Total rules applied 39 place count 38 transition count 64
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 42 place count 35 transition count 61
Iterating global reduction 3 with 3 rules applied. Total rules applied 45 place count 35 transition count 61
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 3 with 3 rules applied. Total rules applied 48 place count 35 transition count 58
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 49 place count 35 transition count 57
Applied a total of 49 rules in 19 ms. Remains 35 /208 variables (removed 173) and now considering 57/294 (removed 237) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 35/208 places, 57/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 57 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 62 places and 0 transitions.
Iterating post reduction 0 with 62 rules applied. Total rules applied 62 place count 146 transition count 294
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 80 place count 128 transition count 258
Iterating global reduction 1 with 18 rules applied. Total rules applied 98 place count 128 transition count 258
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 99 place count 128 transition count 257
Applied a total of 99 rules in 6 ms. Remains 128 /208 variables (removed 80) and now considering 257/294 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 128/208 places, 257/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 257 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 70 places and 0 transitions.
Iterating post reduction 0 with 70 rules applied. Total rules applied 70 place count 138 transition count 294
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 89 place count 119 transition count 256
Iterating global reduction 1 with 19 rules applied. Total rules applied 108 place count 119 transition count 256
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 109 place count 119 transition count 255
Applied a total of 109 rules in 4 ms. Remains 119 /208 variables (removed 89) and now considering 255/294 (removed 39) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 119/208 places, 255/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 68 places and 0 transitions.
Iterating post reduction 0 with 68 rules applied. Total rules applied 68 place count 140 transition count 294
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 87 place count 121 transition count 256
Iterating global reduction 1 with 19 rules applied. Total rules applied 106 place count 121 transition count 256
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 107 place count 121 transition count 255
Applied a total of 107 rules in 4 ms. Remains 121 /208 variables (removed 87) and now considering 255/294 (removed 39) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 121/208 places, 255/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 14 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 61 places and 0 transitions.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 147 transition count 294
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 79 place count 129 transition count 258
Iterating global reduction 1 with 18 rules applied. Total rules applied 97 place count 129 transition count 258
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 98 place count 129 transition count 257
Applied a total of 98 rules in 4 ms. Remains 129 /208 variables (removed 79) and now considering 257/294 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 129/208 places, 257/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 257 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 65 places and 0 transitions.
Iterating post reduction 0 with 65 rules applied. Total rules applied 65 place count 143 transition count 294
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 82 place count 126 transition count 260
Iterating global reduction 1 with 17 rules applied. Total rules applied 99 place count 126 transition count 260
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 100 place count 126 transition count 259
Applied a total of 100 rules in 4 ms. Remains 126 /208 variables (removed 82) and now considering 259/294 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 126/208 places, 259/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 259 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 70 places and 0 transitions.
Iterating post reduction 0 with 70 rules applied. Total rules applied 70 place count 138 transition count 294
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 89 place count 119 transition count 256
Iterating global reduction 1 with 19 rules applied. Total rules applied 108 place count 119 transition count 256
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 109 place count 119 transition count 255
Applied a total of 109 rules in 4 ms. Remains 119 /208 variables (removed 89) and now considering 255/294 (removed 39) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 119/208 places, 255/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 142 transition count 294
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 83 place count 125 transition count 260
Iterating global reduction 1 with 17 rules applied. Total rules applied 100 place count 125 transition count 260
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 101 place count 125 transition count 259
Applied a total of 101 rules in 3 ms. Remains 125 /208 variables (removed 83) and now considering 259/294 (removed 35) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 125/208 places, 259/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 259 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 61 places and 0 transitions.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 147 transition count 294
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 77 place count 131 transition count 262
Iterating global reduction 1 with 16 rules applied. Total rules applied 93 place count 131 transition count 262
Applied a total of 93 rules in 3 ms. Remains 131 /208 variables (removed 77) and now considering 262/294 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 131/208 places, 262/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 262 transitions.
Starting structural reductions in LTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 142 transition count 294
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 84 place count 124 transition count 258
Iterating global reduction 1 with 18 rules applied. Total rules applied 102 place count 124 transition count 258
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 103 place count 124 transition count 257
Applied a total of 103 rules in 3 ms. Remains 124 /208 variables (removed 84) and now considering 257/294 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 124/208 places, 257/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 4 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 4 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 257 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 208/208 places, 294/294 transitions.
Graph (trivial) has 243 edges and 208 vertex of which 102 / 208 are part of one of the 15 SCC in 1 ms
Free SCC test removed 87 places
Ensure Unique test removed 201 transitions
Reduce isomorphic transitions removed 201 transitions.
Graph (complete) has 179 edges and 121 vertex of which 59 are kept as prefixes of interest. Removing 62 places using SCC suffix rule.1 ms
Discarding 62 places :
Also discarding 0 output transitions
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 5 place count 59 transition count 90
Reduce places removed 3 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 1 with 7 rules applied. Total rules applied 12 place count 56 transition count 86
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 17 place count 52 transition count 85
Discarding 11 places :
Symmetric choice reduction at 3 with 11 rule applications. Total rules 28 place count 41 transition count 71
Iterating global reduction 3 with 11 rules applied. Total rules applied 39 place count 41 transition count 71
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 40 place count 41 transition count 70
Drop transitions removed 5 transitions
Redundant transition composition rules discarded 5 transitions
Iterating global reduction 4 with 5 rules applied. Total rules applied 45 place count 41 transition count 65
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 4 with 3 rules applied. Total rules applied 48 place count 41 transition count 65
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 51 place count 38 transition count 62
Iterating global reduction 4 with 3 rules applied. Total rules applied 54 place count 38 transition count 62
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 57 place count 38 transition count 59
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 58 place count 38 transition count 58
Applied a total of 58 rules in 12 ms. Remains 38 /208 variables (removed 170) and now considering 58/294 (removed 236) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 38/208 places, 58/294 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:17:52] [INFO ] Input system was already deterministic with 58 transitions.
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:17:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 12:17:52] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 12:17:52] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 208 places, 294 transitions and 674 arcs took 1 ms.
Total runtime 2694 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-11a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA DLCround-PT-11a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-11a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678278139702

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 6 (type EXCL) for 3 DLCround-PT-11a-CTLFireability-01
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 6 (type EXCL) for DLCround-PT-11a-CTLFireability-01
lola: result : false
lola: markings : 145
lola: fired transitions : 5031
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-11a-CTLFireability-00
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:714
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/199 6/32 DLCround-PT-11a-CTLFireability-00 1266841 m, 253368 m/sec, 4122649 t fired, .

Time elapsed: 6 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/199 11/32 DLCround-PT-11a-CTLFireability-00 2440886 m, 234809 m/sec, 8004555 t fired, .

Time elapsed: 11 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/199 16/32 DLCround-PT-11a-CTLFireability-00 3570836 m, 225990 m/sec, 11806087 t fired, .

Time elapsed: 16 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/199 22/32 DLCround-PT-11a-CTLFireability-00 4725372 m, 230907 m/sec, 15712623 t fired, .

Time elapsed: 21 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/199 26/32 DLCround-PT-11a-CTLFireability-00 5835992 m, 222124 m/sec, 19436198 t fired, .

Time elapsed: 26 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/199 32/32 DLCround-PT-11a-CTLFireability-00 6977072 m, 228216 m/sec, 23246547 t fired, .

Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 1 (type EXCL) for DLCround-PT-11a-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-11a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 58 (type EXCL) for 57 DLCround-PT-11a-CTLFireability-14
lola: time limit : 209 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for DLCround-PT-11a-CTLFireability-14
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 50 DLCround-PT-11a-CTLFireability-12
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for DLCround-PT-11a-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 DLCround-PT-11a-CTLFireability-10
lola: time limit : 237 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/237 6/32 DLCround-PT-11a-CTLFireability-10 1331930 m, 266386 m/sec, 4335910 t fired, .

Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/237 12/32 DLCround-PT-11a-CTLFireability-10 2515058 m, 236625 m/sec, 8246479 t fired, .

Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 15/237 17/32 DLCround-PT-11a-CTLFireability-10 3662555 m, 229499 m/sec, 12117685 t fired, .

Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 20/237 22/32 DLCround-PT-11a-CTLFireability-10 4815201 m, 230529 m/sec, 16023555 t fired, .

Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 25/237 27/32 DLCround-PT-11a-CTLFireability-10 5914922 m, 219944 m/sec, 19704912 t fired, .

Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 30/237 32/32 DLCround-PT-11a-CTLFireability-10 7077059 m, 232427 m/sec, 23574297 t fired, .

Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 48 (type EXCL) for DLCround-PT-11a-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 4 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 45 (type EXCL) for 44 DLCround-PT-11a-CTLFireability-09
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for DLCround-PT-11a-CTLFireability-09
lola: result : true
lola: markings : 1288
lola: fired transitions : 1981
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 29 DLCround-PT-11a-CTLFireability-08
lola: time limit : 271 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/271 7/32 DLCround-PT-11a-CTLFireability-08 1321727 m, 264345 m/sec, 4302722 t fired, .

Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/271 12/32 DLCround-PT-11a-CTLFireability-08 2492428 m, 234140 m/sec, 8169247 t fired, .

Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/271 17/32 DLCround-PT-11a-CTLFireability-08 3603416 m, 222197 m/sec, 11913654 t fired, .

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/271 22/32 DLCround-PT-11a-CTLFireability-08 4741414 m, 227599 m/sec, 15768490 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/271 27/32 DLCround-PT-11a-CTLFireability-08 5853787 m, 222474 m/sec, 19497241 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 1 0 4 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 30/271 32/32 DLCround-PT-11a-CTLFireability-08 6981446 m, 225531 m/sec, 23260519 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 42 (type EXCL) for DLCround-PT-11a-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-08: DISJ 0 3 0 0 4 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 40 (type EXCL) for 29 DLCround-PT-11a-CTLFireability-08
lola: time limit : 291 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for DLCround-PT-11a-CTLFireability-08
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 DLCround-PT-11a-CTLFireability-07
lola: time limit : 388 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/388 5/32 DLCround-PT-11a-CTLFireability-07 1071306 m, 214261 m/sec, 4551551 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/388 10/32 DLCround-PT-11a-CTLFireability-07 2036963 m, 193131 m/sec, 8761244 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/388 14/32 DLCround-PT-11a-CTLFireability-07 2994694 m, 191546 m/sec, 12899632 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 20/388 18/32 DLCround-PT-11a-CTLFireability-07 3923522 m, 185765 m/sec, 16997004 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 25/388 22/32 DLCround-PT-11a-CTLFireability-07 4865817 m, 188459 m/sec, 21149077 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 30/388 26/32 DLCround-PT-11a-CTLFireability-07 5777100 m, 182256 m/sec, 25122515 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 35/388 30/32 DLCround-PT-11a-CTLFireability-07 6689473 m, 182474 m/sec, 29139713 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 27 (type EXCL) for DLCround-PT-11a-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 24 (type EXCL) for 23 DLCround-PT-11a-CTLFireability-06
lola: time limit : 431 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 5/431 4/32 DLCround-PT-11a-CTLFireability-06 721571 m, 144314 m/sec, 3885793 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 10/431 7/32 DLCround-PT-11a-CTLFireability-06 1396609 m, 135007 m/sec, 7314580 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 15/431 10/32 DLCround-PT-11a-CTLFireability-06 2065522 m, 133782 m/sec, 10587827 t fired, .

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 20/431 13/32 DLCround-PT-11a-CTLFireability-06 2705720 m, 128039 m/sec, 13897776 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 25/431 16/32 DLCround-PT-11a-CTLFireability-06 3322939 m, 123443 m/sec, 17132001 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 30/431 19/32 DLCround-PT-11a-CTLFireability-06 3968067 m, 129025 m/sec, 20211903 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 35/431 21/32 DLCround-PT-11a-CTLFireability-06 4558180 m, 118022 m/sec, 23392916 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 40/431 24/32 DLCround-PT-11a-CTLFireability-06 5144582 m, 117280 m/sec, 26601354 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 45/431 27/32 DLCround-PT-11a-CTLFireability-06 5737584 m, 118600 m/sec, 29770142 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 50/431 29/32 DLCround-PT-11a-CTLFireability-06 6327354 m, 117954 m/sec, 32900294 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 55/431 32/32 DLCround-PT-11a-CTLFireability-06 6916210 m, 117771 m/sec, 35950698 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 24 (type EXCL) for DLCround-PT-11a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 21 (type EXCL) for 20 DLCround-PT-11a-CTLFireability-05
lola: time limit : 484 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for DLCround-PT-11a-CTLFireability-05
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 DLCround-PT-11a-CTLFireability-04
lola: time limit : 565 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 5/565 4/32 DLCround-PT-11a-CTLFireability-04 812969 m, 162593 m/sec, 4116378 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 10/565 7/32 DLCround-PT-11a-CTLFireability-04 1498492 m, 137104 m/sec, 7752714 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 15/565 10/32 DLCround-PT-11a-CTLFireability-04 2137807 m, 127863 m/sec, 11309926 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 20/565 13/32 DLCround-PT-11a-CTLFireability-04 2789011 m, 130240 m/sec, 14698385 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 25/565 16/32 DLCround-PT-11a-CTLFireability-04 3384337 m, 119065 m/sec, 18194891 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 30/565 18/32 DLCround-PT-11a-CTLFireability-04 3983915 m, 119915 m/sec, 21606225 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 35/565 21/32 DLCround-PT-11a-CTLFireability-04 4585249 m, 120266 m/sec, 24965768 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 40/565 23/32 DLCround-PT-11a-CTLFireability-04 5162506 m, 115451 m/sec, 28261196 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 45/565 26/32 DLCround-PT-11a-CTLFireability-04 5741322 m, 115763 m/sec, 31484749 t fired, .

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 50/565 28/32 DLCround-PT-11a-CTLFireability-04 6313579 m, 114451 m/sec, 34736823 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 55/565 31/32 DLCround-PT-11a-CTLFireability-04 6953384 m, 127961 m/sec, 38255466 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: CANCELED task # 18 (type EXCL) for DLCround-PT-11a-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-11a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-01: DISJ 0 2 0 0 4 0 0 0
DLCround-PT-11a-CTLFireability-02: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-11a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DLCround-PT-11a-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
DLCround-PT-11a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 13
lola: LAUNCH task # 12 (type EXCL) for 3 DLCround-PT-11a-CTLFireability-01
lola: time limit : 666 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for DLCround-PT-11a-CTLFireability-01
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 15 (type EXCL) for 14 DLCround-PT-11a-CTLFireability-02
lola: time limit : 1111 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for DLCround-PT-11a-CTLFireability-02
lola: result : true
lola: markings : 50
lola: fired transitions : 373
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 50 DLCround-PT-11a-CTLFireability-12
lola: time limit : 1667 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for DLCround-PT-11a-CTLFireability-12
lola: result : false
lola: markings : 3
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 DLCround-PT-11a-CTLFireability-15
lola: time limit : 3334 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for DLCround-PT-11a-CTLFireability-15
lola: result : false
lola: markings : 18817
lola: fired transitions : 535203
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 13

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-11a-CTLFireability-00: CTL unknown AGGR
DLCround-PT-11a-CTLFireability-01: DISJ true state space /EXEF
DLCround-PT-11a-CTLFireability-02: AGEF true tscc_search
DLCround-PT-11a-CTLFireability-04: CTL unknown AGGR
DLCround-PT-11a-CTLFireability-05: EXEF true state space /EXEF
DLCround-PT-11a-CTLFireability-06: CTL unknown AGGR
DLCround-PT-11a-CTLFireability-07: CTL unknown AGGR
DLCround-PT-11a-CTLFireability-08: DISJ true CTL model checker
DLCround-PT-11a-CTLFireability-09: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-10: CTL unknown AGGR
DLCround-PT-11a-CTLFireability-12: CONJ false CTL model checker
DLCround-PT-11a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-11a-CTLFireability-15: CTL false CTL model checker


Time elapsed: 266 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-11a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-11a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478700746"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-11a.tgz
mv DLCround-PT-11a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;