About the Execution of LoLa+red for DLCround-PT-10b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2156.088 | 76449.00 | 163492.00 | 528.10 | TFFFFTTFTFTFTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478700742.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-10b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478700742
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 5.4K Feb 25 18:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 52K Feb 25 18:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 18:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 18:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.9K Feb 25 18:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 103K Feb 25 18:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 18:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Feb 25 18:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.5M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-10b-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678277782762
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-10b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:16:24] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 12:16:24] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:16:24] [INFO ] Load time of PNML (sax parser for PT used): 192 ms
[2023-03-08 12:16:24] [INFO ] Transformed 3924 places.
[2023-03-08 12:16:24] [INFO ] Transformed 6192 transitions.
[2023-03-08 12:16:24] [INFO ] Found NUPN structural information;
[2023-03-08 12:16:24] [INFO ] Parsed PT model containing 3924 places and 6192 transitions and 17304 arcs in 339 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 17 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-10b-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-10b-ReachabilityCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 497 ms. (steps per millisecond=20 ) properties (out of 14) seen :8
FORMULA DLCround-PT-10b-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
// Phase 1: matrix 6192 rows 3924 cols
[2023-03-08 12:16:25] [INFO ] Computed 213 place invariants in 54 ms
[2023-03-08 12:16:26] [INFO ] After 1188ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-08 12:16:27] [INFO ] [Nat]Absence check using 213 positive place invariants in 187 ms returned sat
[2023-03-08 12:16:31] [INFO ] After 3393ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :6
[2023-03-08 12:16:32] [INFO ] Deduced a trap composed of 184 places in 1003 ms of which 9 ms to minimize.
[2023-03-08 12:16:33] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1431 ms
[2023-03-08 12:16:34] [INFO ] Deduced a trap composed of 200 places in 759 ms of which 2 ms to minimize.
[2023-03-08 12:16:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1175 ms
[2023-03-08 12:16:35] [INFO ] Deduced a trap composed of 266 places in 636 ms of which 2 ms to minimize.
[2023-03-08 12:16:36] [INFO ] Deduced a trap composed of 186 places in 508 ms of which 1 ms to minimize.
[2023-03-08 12:16:36] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 1665 ms
[2023-03-08 12:16:37] [INFO ] After 9095ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :6
Attempting to minimize the solution found.
Minimization took 939 ms.
[2023-03-08 12:16:38] [INFO ] After 11347ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :6
FORMULA DLCround-PT-10b-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 4 properties in 172 ms.
Support contains 19 out of 3924 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3924/3924 places, 6192/6192 transitions.
Graph (trivial) has 3588 edges and 3924 vertex of which 657 / 3924 are part of one of the 49 SCC in 14 ms
Free SCC test removed 608 places
Drop transitions removed 681 transitions
Reduce isomorphic transitions removed 681 transitions.
Drop transitions removed 1400 transitions
Trivial Post-agglo rules discarded 1400 transitions
Performed 1400 trivial Post agglomeration. Transition count delta: 1400
Iterating post reduction 0 with 1400 rules applied. Total rules applied 1401 place count 3316 transition count 4111
Reduce places removed 1400 places and 0 transitions.
Ensure Unique test removed 45 transitions
Reduce isomorphic transitions removed 45 transitions.
Drop transitions removed 34 transitions
Trivial Post-agglo rules discarded 34 transitions
Performed 34 trivial Post agglomeration. Transition count delta: 34
Iterating post reduction 1 with 1479 rules applied. Total rules applied 2880 place count 1916 transition count 4032
Reduce places removed 34 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 42 rules applied. Total rules applied 2922 place count 1882 transition count 4024
Reduce places removed 4 places and 0 transitions.
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Iterating post reduction 3 with 12 rules applied. Total rules applied 2934 place count 1878 transition count 4016
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 4 with 8 rules applied. Total rules applied 2942 place count 1870 transition count 4016
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 12 Pre rules applied. Total rules applied 2942 place count 1870 transition count 4004
Deduced a syphon composed of 12 places in 19 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 5 with 24 rules applied. Total rules applied 2966 place count 1858 transition count 4004
Discarding 516 places :
Symmetric choice reduction at 5 with 516 rule applications. Total rules 3482 place count 1342 transition count 3488
Iterating global reduction 5 with 516 rules applied. Total rules applied 3998 place count 1342 transition count 3488
Performed 223 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 223 Pre rules applied. Total rules applied 3998 place count 1342 transition count 3265
Deduced a syphon composed of 223 places in 17 ms
Reduce places removed 223 places and 0 transitions.
Iterating global reduction 5 with 446 rules applied. Total rules applied 4444 place count 1119 transition count 3265
Discarding 82 places :
Symmetric choice reduction at 5 with 82 rule applications. Total rules 4526 place count 1037 transition count 2141
Iterating global reduction 5 with 82 rules applied. Total rules applied 4608 place count 1037 transition count 2141
Ensure Unique test removed 28 transitions
Reduce isomorphic transitions removed 28 transitions.
Iterating post reduction 5 with 28 rules applied. Total rules applied 4636 place count 1037 transition count 2113
Performed 277 Post agglomeration using F-continuation condition with reduction of 10 identical transitions.
Deduced a syphon composed of 277 places in 1 ms
Reduce places removed 277 places and 0 transitions.
Iterating global reduction 6 with 554 rules applied. Total rules applied 5190 place count 760 transition count 1826
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 6 with 10 rules applied. Total rules applied 5200 place count 760 transition count 1816
Renaming transitions due to excessive name length > 1024 char.
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules 5201 place count 759 transition count 1802
Iterating global reduction 7 with 1 rules applied. Total rules applied 5202 place count 759 transition count 1802
Performed 46 Post agglomeration using F-continuation condition.Transition count delta: -518
Deduced a syphon composed of 46 places in 3 ms
Reduce places removed 46 places and 0 transitions.
Iterating global reduction 7 with 92 rules applied. Total rules applied 5294 place count 713 transition count 2320
Drop transitions removed 22 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 24 transitions.
Iterating post reduction 7 with 24 rules applied. Total rules applied 5318 place count 713 transition count 2296
Discarding 23 places :
Symmetric choice reduction at 8 with 23 rule applications. Total rules 5341 place count 690 transition count 1657
Iterating global reduction 8 with 23 rules applied. Total rules applied 5364 place count 690 transition count 1657
Ensure Unique test removed 22 transitions
Reduce isomorphic transitions removed 22 transitions.
Iterating post reduction 8 with 22 rules applied. Total rules applied 5386 place count 690 transition count 1635
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -18
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 9 with 4 rules applied. Total rules applied 5390 place count 688 transition count 1653
Drop transitions removed 186 transitions
Redundant transition composition rules discarded 186 transitions
Iterating global reduction 9 with 186 rules applied. Total rules applied 5576 place count 688 transition count 1467
Discarding 11 places :
Symmetric choice reduction at 9 with 11 rule applications. Total rules 5587 place count 677 transition count 1310
Iterating global reduction 9 with 11 rules applied. Total rules applied 5598 place count 677 transition count 1310
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 9 with 10 rules applied. Total rules applied 5608 place count 677 transition count 1300
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -32
Deduced a syphon composed of 3 places in 2 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 10 with 6 rules applied. Total rules applied 5614 place count 674 transition count 1332
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 10 with 1 rules applied. Total rules applied 5615 place count 674 transition count 1331
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 11 with 10 rules applied. Total rules applied 5625 place count 674 transition count 1321
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -10
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 5627 place count 673 transition count 1331
Free-agglomeration rule applied 408 times with reduction of 206 identical transitions.
Iterating global reduction 11 with 408 rules applied. Total rules applied 6035 place count 673 transition count 717
Reduce places removed 408 places and 0 transitions.
Drop transitions removed 411 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 416 transitions.
Graph (complete) has 536 edges and 265 vertex of which 175 are kept as prefixes of interest. Removing 90 places using SCC suffix rule.1 ms
Discarding 90 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Iterating post reduction 11 with 825 rules applied. Total rules applied 6860 place count 175 transition count 299
Drop transitions removed 2 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 12 with 4 rules applied. Total rules applied 6864 place count 175 transition count 295
Discarding 86 places :
Symmetric choice reduction at 13 with 86 rule applications. Total rules 6950 place count 89 transition count 156
Iterating global reduction 13 with 86 rules applied. Total rules applied 7036 place count 89 transition count 156
Drop transitions removed 27 transitions
Redundant transition composition rules discarded 27 transitions
Iterating global reduction 13 with 27 rules applied. Total rules applied 7063 place count 89 transition count 129
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 7064 place count 88 transition count 129
Discarding 1 places :
Symmetric choice reduction at 14 with 1 rule applications. Total rules 7065 place count 87 transition count 128
Iterating global reduction 14 with 1 rules applied. Total rules applied 7066 place count 87 transition count 128
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -7
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 14 with 2 rules applied. Total rules applied 7068 place count 86 transition count 135
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 14 with 5 rules applied. Total rules applied 7073 place count 86 transition count 130
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 15 with 1 rules applied. Total rules applied 7074 place count 86 transition count 129
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 15 with 1 rules applied. Total rules applied 7075 place count 86 transition count 129
Applied a total of 7075 rules in 1113 ms. Remains 86 /3924 variables (removed 3838) and now considering 129/6192 (removed 6063) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1114 ms. Remains : 86/3924 places, 129/6192 transitions.
Finished random walk after 68 steps, including 0 resets, run visited all 2 properties in 2 ms. (steps per millisecond=34 )
FORMULA DLCround-PT-10b-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-10b-ReachabilityCardinality-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
All properties solved without resorting to model-checking.
Total runtime 15459 ms.
starting LoLA
BK_INPUT DLCround-PT-10b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCround-PT-10b-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-10b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678277859211
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 39 DLCround-PT-10b-ReachabilityCardinality-13
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 39 DLCround-PT-10b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 39 DLCround-PT-10b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 39 DLCround-PT-10b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 48 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-13
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 49 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 51 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 52 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-13 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
lola: FINISHED task # 49 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type EXCL) for 36 DLCround-PT-10b-ReachabilityCardinality-12
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 54 (type FNDP) for 36 DLCround-PT-10b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 36 DLCround-PT-10b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SRCH) for 36 DLCround-PT-10b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 57 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 58 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 54 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 55 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 65 (type EXCL) for 12 DLCround-PT-10b-ReachabilityCardinality-04
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 61 (type FNDP) for 12 DLCround-PT-10b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 12 DLCround-PT-10b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 12 DLCround-PT-10b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 65 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-04
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 61 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 62 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 64 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-04 (obsolete)
lola: FINISHED task # 54 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-55.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-62.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 71 (type EXCL) for 30 DLCround-PT-10b-ReachabilityCardinality-10
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 67 (type FNDP) for 30 DLCround-PT-10b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 30 DLCround-PT-10b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SRCH) for 30 DLCround-PT-10b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 62 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-04
lola: result : true
lola: FINISHED task # 55 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-12
lola: result : true
lola: FINISHED task # 70 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 67 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 68 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 71 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-10 (obsolete)
lola: FINISHED task # 67 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 78 (type EXCL) for 9 DLCround-PT-10b-ReachabilityCardinality-03
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 74 (type FNDP) for 9 DLCround-PT-10b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 9 DLCround-PT-10b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SRCH) for 9 DLCround-PT-10b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-68.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 74 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 75 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 77 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 78 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 85 (type EXCL) for 27 DLCround-PT-10b-ReachabilityCardinality-09
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 81 (type FNDP) for 27 DLCround-PT-10b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 82 (type EQUN) for 27 DLCround-PT-10b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SRCH) for 27 DLCround-PT-10b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 84 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-09
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 81 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 82 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 85 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 68 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-10
lola: result : true
lola: LAUNCH task # 91 (type EXCL) for 24 DLCround-PT-10b-ReachabilityCardinality-08
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 87 (type FNDP) for 24 DLCround-PT-10b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 24 DLCround-PT-10b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 24 DLCround-PT-10b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-09
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 87 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 90 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-08
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 88 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 91 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-08 (obsolete)
lola: FINISHED task # 82 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-09
lola: result : true
lola: FINISHED task # 88 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-08
lola: result : unknown
lola: FINISHED task # 75 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-03
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 97 (type EXCL) for 15 DLCround-PT-10b-ReachabilityCardinality-05
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 93 (type FNDP) for 15 DLCround-PT-10b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 15 DLCround-PT-10b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SRCH) for 15 DLCround-PT-10b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 97 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-05
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 93 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 94 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 96 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-05 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 93 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 94 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-05
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 103 (type EXCL) for 18 DLCround-PT-10b-ReachabilityCardinality-06
lola: time limit : 445 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 99 (type FNDP) for 18 DLCround-PT-10b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 18 DLCround-PT-10b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type SRCH) for 18 DLCround-PT-10b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-06
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 99 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 100 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 102 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-06 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 99 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-100.sara.
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 100 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 109 (type EXCL) for 42 DLCround-PT-10b-ReachabilityCardinality-14
lola: time limit : 509 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 105 (type FNDP) for 42 DLCround-PT-10b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type EQUN) for 42 DLCround-PT-10b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type SRCH) for 42 DLCround-PT-10b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 109 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-14
lola: result : true
lola: markings : 64
lola: fired transitions : 85
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 105 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 106 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 108 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-14 (obsolete)
lola: FINISHED task # 105 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 116 (type EXCL) for 33 DLCround-PT-10b-ReachabilityCardinality-11
lola: time limit : 594 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 112 (type FNDP) for 33 DLCround-PT-10b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type EQUN) for 33 DLCround-PT-10b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type SRCH) for 33 DLCround-PT-10b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-106.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 106 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-14
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-113.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-11: AG 0 1 4 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
112 EF FNDP 0/1783 0/5 DLCround-PT-10b-ReachabilityCardinality-11 1094 t fired, 1 attempts, .
113 EF STEQ 0/3566 0/5 DLCround-PT-10b-ReachabilityCardinality-11 sara is running.
115 EF SRCH 0/3566 1/5 DLCround-PT-10b-ReachabilityCardinality-11 1105 m, 221 m/sec, 2728 t fired, .
116 EF EXCL 0/594 1/32 DLCround-PT-10b-ReachabilityCardinality-11 199 m, 39 m/sec, 261 t fired, .
Time elapsed: 34 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 112 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 3326
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 113 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 115 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 116 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 135 (type EXCL) for 0 DLCround-PT-10b-ReachabilityCardinality-00
lola: time limit : 713 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 137 (type FNDP) for 45 DLCround-PT-10b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type EQUN) for 45 DLCround-PT-10b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type SRCH) for 45 DLCround-PT-10b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-11
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 137 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 138 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 140 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 118 (type FNDP) for 3 DLCround-PT-10b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 119 (type EQUN) for 3 DLCround-PT-10b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type SRCH) for 3 DLCround-PT-10b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-119.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-138.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-15: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-ReachabilityCardinality-00: EF 0 4 1 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-01: EF 0 2 3 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
118 EF FNDP 4/594 0/5 DLCround-PT-10b-ReachabilityCardinality-01 1976553 t fired, 2 attempts, .
119 EF STEQ 4/713 0/5 DLCround-PT-10b-ReachabilityCardinality-01 sara is running.
121 EF SRCH 4/713 5/5 DLCround-PT-10b-ReachabilityCardinality-01 1039848 m, 207969 m/sec, 1963373 t fired, .
135 EF EXCL 4/891 1/32 DLCround-PT-10b-ReachabilityCardinality-00 11405 m, 2281 m/sec, 18317 t fired, .
Time elapsed: 39 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 119 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-01
lola: result : false
lola: CANCELED task # 118 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 121 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 125 (type FNDP) for 21 DLCround-PT-10b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type EQUN) for 21 DLCround-PT-10b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 128 (type SRCH) for 21 DLCround-PT-10b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 118 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 2251602
lola: tried executions : 4
lola: time used : 5.000000
lola: memory pages used : 0
lola: FINISHED task # 125 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-07
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 126 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 128 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 143 (type FNDP) for 6 DLCround-PT-10b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 144 (type EQUN) for 6 DLCround-PT-10b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 146 (type SRCH) for 6 DLCround-PT-10b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-126.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-144.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-01: EF false state equation
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-15: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-ReachabilityCardinality-00: EF 0 4 1 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-02: EF 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
135 EF EXCL 9/1782 1/32 DLCround-PT-10b-ReachabilityCardinality-00 22727 m, 2264 m/sec, 36863 t fired, .
143 EF FNDP 4/1186 0/5 DLCround-PT-10b-ReachabilityCardinality-02 52946 t fired, 4 attempts, .
144 EF STEQ 4/1186 0/5 DLCround-PT-10b-ReachabilityCardinality-02 sara is running.
146 EF SRCH 4/1780 2/5 DLCround-PT-10b-ReachabilityCardinality-02 219875 m, 43975 m/sec, 345925 t fired, .
Time elapsed: 44 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-01: EF false state equation
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-15: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-ReachabilityCardinality-00: EF 0 4 1 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-02: EF 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
135 EF EXCL 14/1782 1/32 DLCround-PT-10b-ReachabilityCardinality-00 32084 m, 1871 m/sec, 52246 t fired, .
143 EF FNDP 9/1182 0/5 DLCround-PT-10b-ReachabilityCardinality-02 117663 t fired, 8 attempts, .
144 EF STEQ 9/1182 0/5 DLCround-PT-10b-ReachabilityCardinality-02 sara is running.
146 EF SRCH 9/1776 3/5 DLCround-PT-10b-ReachabilityCardinality-02 502219 m, 56468 m/sec, 722566 t fired, .
Time elapsed: 49 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-01: EF false state equation
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-15: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-10b-ReachabilityCardinality-00: EF 0 4 1 0 1 0 0 0
DLCround-PT-10b-ReachabilityCardinality-02: EF 0 2 3 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
135 EF EXCL 19/1782 1/32 DLCround-PT-10b-ReachabilityCardinality-00 42431 m, 2069 m/sec, 69277 t fired, .
143 EF FNDP 14/1177 0/5 DLCround-PT-10b-ReachabilityCardinality-02 180946 t fired, 11 attempts, .
144 EF STEQ 14/1177 0/5 DLCround-PT-10b-ReachabilityCardinality-02 sara is running.
146 EF SRCH 14/1771 5/5 DLCround-PT-10b-ReachabilityCardinality-02 811120 m, 61780 m/sec, 1150129 t fired, .
Time elapsed: 54 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 146 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-02 (memory limit exceeded)
lola: FINISHED task # 144 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 143 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 131 (type FNDP) for 0 DLCround-PT-10b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 132 (type EQUN) for 0 DLCround-PT-10b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 134 (type SRCH) for 0 DLCround-PT-10b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 143 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 238502
lola: tried executions : 15
lola: time used : 19.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 134 (type SRCH) for DLCround-PT-10b-ReachabilityCardinality-00
lola: result : true
lola: markings : 9
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 131 (type FNDP) for DLCround-PT-10b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 132 (type EQUN) for DLCround-PT-10b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 135 (type EXCL) for DLCround-PT-10b-ReachabilityCardinality-00 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-10b-ReachabilityCardinality-00: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-01: EF false state equation
DLCround-PT-10b-ReachabilityCardinality-02: EF false state equation
DLCround-PT-10b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-05: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-06: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-07: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-09: AG false tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-10: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-10b-ReachabilityCardinality-12: EF true tandem / insertion
DLCround-PT-10b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-10b-ReachabilityCardinality-14: EF true tandem / relaxed
DLCround-PT-10b-ReachabilityCardinality-15: EF true findpath
Time elapsed: 59 secs. Pages in use: 6
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-10b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-10b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478700742"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-10b.tgz
mv DLCround-PT-10b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;