MCC'2023- Execution of r103-tall-167814478700726

About the Execution of LoLa+red for DLCround-PT-09b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
7090.243	216679.00	733889.00	419.60	TTFFTFTFTTTFTTFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478700726.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-09b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478700726
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 5.4K Feb 25 18:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 54K Feb 25 18:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 18:25 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 18:25 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 18:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 154K Feb 25 18:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 25 18:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 25 18:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.3M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-09b-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678277328850

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-09b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 12:08:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 12:08:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:08:50] [INFO ] Load time of PNML (sax parser for PT used): 183 ms
[2023-03-08 12:08:50] [INFO ] Transformed 3495 places.
[2023-03-08 12:08:50] [INFO ] Transformed 5439 transitions.
[2023-03-08 12:08:50] [INFO ] Found NUPN structural information;
[2023-03-08 12:08:50] [INFO ] Parsed PT model containing 3495 places and 5439 transitions and 15081 arcs in 313 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 17 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-09b-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-09b-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-09b-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-09b-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-09b-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 372 ms. (steps per millisecond=26 ) properties (out of 11) seen :9
FORMULA DLCround-PT-09b-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-02 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-09b-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 5439 rows 3495 cols
[2023-03-08 12:08:51] [INFO ] Computed 184 place invariants in 52 ms
[2023-03-08 12:08:52] [INFO ] [Real]Absence check using 184 positive place invariants in 164 ms returned sat
[2023-03-08 12:08:52] [INFO ] After 991ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 12:08:53] [INFO ] [Nat]Absence check using 184 positive place invariants in 141 ms returned sat
[2023-03-08 12:08:55] [INFO ] After 2317ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-08 12:08:56] [INFO ] Deduced a trap composed of 121 places in 788 ms of which 9 ms to minimize.
[2023-03-08 12:08:56] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1149 ms
[2023-03-08 12:08:57] [INFO ] Deduced a trap composed of 176 places in 735 ms of which 1 ms to minimize.
[2023-03-08 12:08:57] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 1088 ms
[2023-03-08 12:08:58] [INFO ] After 4858ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 398 ms.
[2023-03-08 12:08:58] [INFO ] After 5996ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 69 ms.
Support contains 36 out of 3495 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3495/3495 places, 5439/5439 transitions.
Graph (trivial) has 3185 edges and 3495 vertex of which 550 / 3495 are part of one of the 43 SCC in 19 ms
Free SCC test removed 507 places
Drop transitions removed 569 transitions
Reduce isomorphic transitions removed 569 transitions.
Drop transitions removed 1265 transitions
Trivial Post-agglo rules discarded 1265 transitions
Performed 1265 trivial Post agglomeration. Transition count delta: 1265
Iterating post reduction 0 with 1265 rules applied. Total rules applied 1266 place count 2988 transition count 3605
Reduce places removed 1265 places and 0 transitions.
Ensure Unique test removed 41 transitions
Reduce isomorphic transitions removed 41 transitions.
Drop transitions removed 30 transitions
Trivial Post-agglo rules discarded 30 transitions
Performed 30 trivial Post agglomeration. Transition count delta: 30
Iterating post reduction 1 with 1336 rules applied. Total rules applied 2602 place count 1723 transition count 3534
Reduce places removed 30 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 38 rules applied. Total rules applied 2640 place count 1693 transition count 3526
Reduce places removed 4 places and 0 transitions.
Performed 16 Post agglomeration using F-continuation condition.Transition count delta: 16
Iterating post reduction 3 with 20 rules applied. Total rules applied 2660 place count 1689 transition count 3510
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 4 with 16 rules applied. Total rules applied 2676 place count 1673 transition count 3510
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 15 Pre rules applied. Total rules applied 2676 place count 1673 transition count 3495
Deduced a syphon composed of 15 places in 14 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 5 with 30 rules applied. Total rules applied 2706 place count 1658 transition count 3495
Discarding 437 places :
Symmetric choice reduction at 5 with 437 rule applications. Total rules 3143 place count 1221 transition count 3058
Iterating global reduction 5 with 437 rules applied. Total rules applied 3580 place count 1221 transition count 3058
Performed 185 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 185 Pre rules applied. Total rules applied 3580 place count 1221 transition count 2873
Deduced a syphon composed of 185 places in 12 ms
Reduce places removed 185 places and 0 transitions.
Iterating global reduction 5 with 370 rules applied. Total rules applied 3950 place count 1036 transition count 2873
Discarding 61 places :
Symmetric choice reduction at 5 with 61 rule applications. Total rules 4011 place count 975 transition count 2092
Iterating global reduction 5 with 61 rules applied. Total rules applied 4072 place count 975 transition count 2092
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 5 with 19 rules applied. Total rules applied 4091 place count 975 transition count 2073
Performed 262 Post agglomeration using F-continuation condition with reduction of 9 identical transitions.
Deduced a syphon composed of 262 places in 3 ms
Reduce places removed 262 places and 0 transitions.
Iterating global reduction 6 with 524 rules applied. Total rules applied 4615 place count 713 transition count 1802
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 6 with 8 rules applied. Total rules applied 4623 place count 713 transition count 1794
Discarding 3 places :
Symmetric choice reduction at 7 with 3 rule applications. Total rules 4626 place count 710 transition count 1755
Iterating global reduction 7 with 3 rules applied. Total rules applied 4629 place count 710 transition count 1755
Performed 57 Post agglomeration using F-continuation condition.Transition count delta: -565
Deduced a syphon composed of 57 places in 4 ms
Reduce places removed 57 places and 0 transitions.
Iterating global reduction 7 with 114 rules applied. Total rules applied 4743 place count 653 transition count 2320
Drop transitions removed 62 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 67 transitions.
Iterating post reduction 7 with 67 rules applied. Total rules applied 4810 place count 653 transition count 2253
Discarding 19 places :
Symmetric choice reduction at 8 with 19 rule applications. Total rules 4829 place count 634 transition count 1767
Iterating global reduction 8 with 19 rules applied. Total rules applied 4848 place count 634 transition count 1767
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 8 with 13 rules applied. Total rules applied 4861 place count 634 transition count 1754
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -38
Deduced a syphon composed of 4 places in 3 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 9 with 8 rules applied. Total rules applied 4869 place count 630 transition count 1792
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 9 with 2 rules applied. Total rules applied 4871 place count 630 transition count 1790
Drop transitions removed 182 transitions
Redundant transition composition rules discarded 182 transitions
Iterating global reduction 10 with 182 rules applied. Total rules applied 5053 place count 630 transition count 1608
Discarding 10 places :
Symmetric choice reduction at 10 with 10 rule applications. Total rules 5063 place count 620 transition count 1464
Iterating global reduction 10 with 10 rules applied. Total rules applied 5073 place count 620 transition count 1464
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 10 with 10 rules applied. Total rules applied 5083 place count 620 transition count 1454
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -14
Deduced a syphon composed of 2 places in 2 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 11 with 4 rules applied. Total rules applied 5087 place count 618 transition count 1468
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 11 with 2 rules applied. Total rules applied 5089 place count 618 transition count 1466
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 12 with 2 rules applied. Total rules applied 5091 place count 618 transition count 1464
Free-agglomeration rule applied 337 times with reduction of 182 identical transitions.
Iterating global reduction 12 with 337 rules applied. Total rules applied 5428 place count 618 transition count 945
Reduce places removed 337 places and 0 transitions.
Drop transitions removed 376 transitions
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 382 transitions.
Graph (complete) has 755 edges and 281 vertex of which 258 are kept as prefixes of interest. Removing 23 places using SCC suffix rule.1 ms
Discarding 23 places :
Also discarding 0 output transitions
Iterating post reduction 12 with 720 rules applied. Total rules applied 6148 place count 258 transition count 563
Drop transitions removed 6 transitions
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 20 transitions.
Iterating post reduction 13 with 20 rules applied. Total rules applied 6168 place count 258 transition count 543
Discarding 62 places :
Symmetric choice reduction at 14 with 62 rule applications. Total rules 6230 place count 196 transition count 446
Iterating global reduction 14 with 62 rules applied. Total rules applied 6292 place count 196 transition count 446
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 14 with 2 rules applied. Total rules applied 6294 place count 195 transition count 445
Drop transitions removed 55 transitions
Redundant transition composition rules discarded 55 transitions
Iterating global reduction 14 with 55 rules applied. Total rules applied 6349 place count 195 transition count 390
Reduce places removed 2 places and 0 transitions.
Graph (complete) has 524 edges and 193 vertex of which 191 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.0 ms
Discarding 2 places :
Also discarding 0 output transitions
Iterating post reduction 14 with 3 rules applied. Total rules applied 6352 place count 191 transition count 390
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 15 with 2 rules applied. Total rules applied 6354 place count 191 transition count 388
Discarding 20 places :
Symmetric choice reduction at 16 with 20 rule applications. Total rules 6374 place count 171 transition count 359
Iterating global reduction 16 with 20 rules applied. Total rules applied 6394 place count 171 transition count 359
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 16 with 1 rules applied. Total rules applied 6395 place count 171 transition count 364
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 16 with 6 rules applied. Total rules applied 6401 place count 170 transition count 359
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 17 with 1 rules applied. Total rules applied 6402 place count 170 transition count 358
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 17 with 1 rules applied. Total rules applied 6403 place count 170 transition count 358
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 17 with 1 rules applied. Total rules applied 6404 place count 169 transition count 357
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 17 with 1 rules applied. Total rules applied 6405 place count 168 transition count 357
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 18 with 4 rules applied. Total rules applied 6409 place count 166 transition count 355
Drop transitions removed 4 transitions
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 18 with 13 rules applied. Total rules applied 6422 place count 166 transition count 342
Discarding 2 places :
Symmetric choice reduction at 19 with 2 rule applications. Total rules 6424 place count 164 transition count 340
Iterating global reduction 19 with 2 rules applied. Total rules applied 6426 place count 164 transition count 340
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 19 with 3 rules applied. Total rules applied 6429 place count 162 transition count 339
Drop transitions removed 1 transitions
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 5 transitions.
Graph (trivial) has 12 edges and 162 vertex of which 6 / 162 are part of one of the 1 SCC in 0 ms
Free SCC test removed 5 places
Iterating post reduction 19 with 6 rules applied. Total rules applied 6435 place count 157 transition count 334
Drop transitions removed 32 transitions
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 42 transitions.
Iterating post reduction 20 with 42 rules applied. Total rules applied 6477 place count 157 transition count 292
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 21 with 8 rules applied. Total rules applied 6485 place count 157 transition count 284
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 21 with 1 rules applied. Total rules applied 6486 place count 156 transition count 284
Discarding 4 places :
Symmetric choice reduction at 22 with 4 rule applications. Total rules 6490 place count 152 transition count 277
Iterating global reduction 22 with 4 rules applied. Total rules applied 6494 place count 152 transition count 277
Applied a total of 6494 rules in 926 ms. Remains 152 /3495 variables (removed 3343) and now considering 277/5439 (removed 5162) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 926 ms. Remains : 152/3495 places, 277/5439 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 2) seen :1
FORMULA DLCround-PT-09b-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Finished Best-First random walk after 1682 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=420 )
FORMULA DLCround-PT-09b-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
All properties solved without resorting to model-checking.
Total runtime 9234 ms.
starting LoLA
BK_INPUT DLCround-PT-09b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA DLCround-PT-09b-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-09b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678277545529

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 63 (type EXCL) for 12 DLCround-PT-09b-ReachabilityCardinality-04
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 56 (type FNDP) for 12 DLCround-PT-09b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 12 DLCround-PT-09b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 12 DLCround-PT-09b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 62 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-04
lola: result : false
lola: markings : 2
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 63 (type EXCL) for DLCround-PT-09b-ReachabilityCardinality-04
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 56 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 60 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-04 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 80 (type EXCL) for 9 DLCround-PT-09b-ReachabilityCardinality-03
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 75 (type FNDP) for 36 DLCround-PT-09b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type EQUN) for 36 DLCround-PT-09b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SRCH) for 36 DLCround-PT-09b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 89 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-12
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 75 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 87 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 112 (type SRCH) for 6 DLCround-PT-09b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type FNDP) for 24 DLCround-PT-09b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 24 DLCround-PT-09b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-60.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 75 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 28969
lola: tried executions : 14486
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 112 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type FNDP) for 21 DLCround-PT-09b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.

lola: FINISHED task # 60 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-04
lola: result : false
lola: FINISHED task # 74 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 82 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 53 (type FNDP) for 27 DLCround-PT-09b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 27 DLCround-PT-09b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 82 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-08
lola: result : unknown
lola: FINISHED task # 87 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-12
lola: result : false
lola: FINISHED task # 53 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 55 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 73 (type FNDP) for 18 DLCround-PT-09b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 109 (type EQUN) for 18 DLCround-PT-09b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-09
lola: result : unknown
lola: FINISHED task # 73 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 109 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 72 (type FNDP) for 15 DLCround-PT-09b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 15 DLCround-PT-09b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-109.sara.

lola: FINISHED task # 109 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-06
lola: result : true
lola: FINISHED task # 72 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 100 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 113 (type FNDP) for 33 DLCround-PT-09b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type EQUN) for 33 DLCround-PT-09b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 113 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 118 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 71 (type FNDP) for 42 DLCround-PT-09b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type EQUN) for 42 DLCround-PT-09b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-100.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-118.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-102.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 2/323 0/5 DLCround-PT-09b-ReachabilityCardinality-07 2529794 t fired, 1264898 attempts, .
71 EF FNDP 1/296 0/5 DLCround-PT-09b-ReachabilityCardinality-14 93137 t fired, 1 attempts, .
80 EF EXCL 2/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 3588 m, 717 m/sec, 5950 t fired, .
102 EF STEQ 1/296 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

Time elapsed: 38 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 100 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-05
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 7/321 0/5 DLCround-PT-09b-ReachabilityCardinality-07 13854044 t fired, 6927023 attempts, .
71 EF FNDP 6/294 0/5 DLCround-PT-09b-ReachabilityCardinality-14 663845 t fired, 1 attempts, .
80 EF EXCL 7/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 18966 m, 3075 m/sec, 32354 t fired, .
102 EF STEQ 6/294 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

Time elapsed: 43 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 12/317 0/5 DLCround-PT-09b-ReachabilityCardinality-07 26388772 t fired, 13194387 attempts, .
71 EF FNDP 11/290 0/5 DLCround-PT-09b-ReachabilityCardinality-14 959218 t fired, 1 attempts, .
80 EF EXCL 12/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 35621 m, 3331 m/sec, 62626 t fired, .
102 EF STEQ 11/290 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

Time elapsed: 48 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 17/312 0/5 DLCround-PT-09b-ReachabilityCardinality-07 39413490 t fired, 19706746 attempts, .
71 EF FNDP 16/285 0/5 DLCround-PT-09b-ReachabilityCardinality-14 1251557 t fired, 2 attempts, .
80 EF EXCL 17/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 50779 m, 3031 m/sec, 89378 t fired, .
102 EF STEQ 16/285 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

Time elapsed: 53 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 22/307 0/5 DLCround-PT-09b-ReachabilityCardinality-07 52658802 t fired, 26329402 attempts, .
71 EF FNDP 21/280 0/5 DLCround-PT-09b-ReachabilityCardinality-14 1459125 t fired, 2 attempts, .
80 EF EXCL 22/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 66973 m, 3238 m/sec, 118791 t fired, .
102 EF STEQ 21/280 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 27/302 0/5 DLCround-PT-09b-ReachabilityCardinality-07 64453450 t fired, 32226726 attempts, .
71 EF FNDP 26/275 0/5 DLCround-PT-09b-ReachabilityCardinality-14 1637807 t fired, 2 attempts, .
80 EF EXCL 27/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 83856 m, 3376 m/sec, 149363 t fired, .
102 EF STEQ 26/275 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 32/297 0/5 DLCround-PT-09b-ReachabilityCardinality-07 78397584 t fired, 39198793 attempts, .
71 EF FNDP 31/270 0/5 DLCround-PT-09b-ReachabilityCardinality-14 1807853 t fired, 2 attempts, .
80 EF EXCL 32/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 100615 m, 3351 m/sec, 180289 t fired, .
102 EF STEQ 31/270 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-14: AG 0 3 2 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-15: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 37/292 0/5 DLCround-PT-09b-ReachabilityCardinality-07 89682530 t fired, 44841266 attempts, .
71 EF FNDP 36/265 0/5 DLCround-PT-09b-ReachabilityCardinality-14 1966620 t fired, 2 attempts, .
80 EF EXCL 37/396 1/32 DLCround-PT-09b-ReachabilityCardinality-03 117046 m, 3286 m/sec, 210664 t fired, .
102 EF STEQ 36/265 0/5 DLCround-PT-09b-ReachabilityCardinality-14 sara is running.

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lola: FINISHED task # 71 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 2000381
lola: tried executions : 3
lola: time used : 37.000000
lola: memory pages used : 0
lola: CANCELED task # 102 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 106 (type FNDP) for 3 DLCround-PT-09b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 3 DLCround-PT-09b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 102 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-14
lola: result : unknown
lola: FINISHED task # 106 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 116 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 92 (type FNDP) for 45 DLCround-PT-09b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type EQUN) for 45 DLCround-PT-09b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 92 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 93 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 111 (type FNDP) for 30 DLCround-PT-09b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type EQUN) for 30 DLCround-PT-09b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
lola: FINISHED task # 111 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 130 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 99 (type FNDP) for 39 DLCround-PT-09b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type EQUN) for 39 DLCround-PT-09b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-93.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787

lola: FINISHED task # 116 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-01
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-130.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 42/556 0/5 DLCround-PT-09b-ReachabilityCardinality-07 98941174 t fired, 49470588 attempts, .
80 EF EXCL 42/712 1/32 DLCround-PT-09b-ReachabilityCardinality-03 129587 m, 2508 m/sec, 234193 t fired, .
99 EF FNDP 4/587 0/5 DLCround-PT-09b-ReachabilityCardinality-13 213202 t fired, 1 attempts, .
108 EF STEQ 4/503 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 47/552 0/5 DLCround-PT-09b-ReachabilityCardinality-07 106694762 t fired, 53347382 attempts, .
80 EF EXCL 47/712 1/32 DLCround-PT-09b-ReachabilityCardinality-03 141039 m, 2290 m/sec, 255085 t fired, .
99 EF FNDP 9/583 0/5 DLCround-PT-09b-ReachabilityCardinality-13 499433 t fired, 1 attempts, .
108 EF STEQ 9/499 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 52/547 0/5 DLCround-PT-09b-ReachabilityCardinality-07 112866996 t fired, 56433499 attempts, .
80 EF EXCL 52/712 1/32 DLCround-PT-09b-ReachabilityCardinality-03 152795 m, 2351 m/sec, 276769 t fired, .
99 EF FNDP 14/578 0/5 DLCround-PT-09b-ReachabilityCardinality-13 779185 t fired, 1 attempts, .
108 EF STEQ 14/494 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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sara: warning, failure of lp_solve (at job 880)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 57/542 0/5 DLCround-PT-09b-ReachabilityCardinality-07 120360092 t fired, 60180047 attempts, .
80 EF EXCL 57/712 1/32 DLCround-PT-09b-ReachabilityCardinality-03 164148 m, 2270 m/sec, 297821 t fired, .
99 EF FNDP 19/573 0/5 DLCround-PT-09b-ReachabilityCardinality-13 1047978 t fired, 2 attempts, .
108 EF STEQ 19/489 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 62/537 0/5 DLCround-PT-09b-ReachabilityCardinality-07 127747456 t fired, 63873729 attempts, .
80 EF EXCL 62/712 1/32 DLCround-PT-09b-ReachabilityCardinality-03 175387 m, 2247 m/sec, 318661 t fired, .
99 EF FNDP 24/568 0/5 DLCround-PT-09b-ReachabilityCardinality-13 1295032 t fired, 2 attempts, .
108 EF STEQ 24/484 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 67/532 0/5 DLCround-PT-09b-ReachabilityCardinality-07 135169892 t fired, 67584947 attempts, .
80 EF EXCL 67/712 2/32 DLCround-PT-09b-ReachabilityCardinality-03 186568 m, 2236 m/sec, 339658 t fired, .
99 EF FNDP 29/563 0/5 DLCround-PT-09b-ReachabilityCardinality-13 1525885 t fired, 2 attempts, .
108 EF STEQ 29/479 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-02: AG 0 4 0 0 2 0 0 0
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-07: EF 0 4 1 0 1 0 0 0
DLCround-PT-09b-ReachabilityCardinality-13: AG 0 3 2 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 72/527 0/5 DLCround-PT-09b-ReachabilityCardinality-07 143538148 t fired, 71769075 attempts, .
80 EF EXCL 72/712 2/32 DLCround-PT-09b-ReachabilityCardinality-03 197720 m, 2230 m/sec, 360567 t fired, .
99 EF FNDP 34/558 0/5 DLCround-PT-09b-ReachabilityCardinality-13 1675385 t fired, 2 attempts, .
108 EF STEQ 34/474 0/5 DLCround-PT-09b-ReachabilityCardinality-13 sara is running.

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lola: FINISHED task # 108 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-13
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lola: LAUNCH task # 146 (type FNDP) for 0 DLCround-PT-09b-ReachabilityCardinality-00
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lola: LAUNCH task # 147 (type EQUN) for 0 DLCround-PT-09b-ReachabilityCardinality-00
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lola: FINISHED task # 99 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 1703326
lola: tried executions : 3
lola: time used : 35.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 146 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
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lola: memory pages used : 0
lola: CANCELED task # 147 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-00 (obsolete)
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lola: time limit : 32000000 sec
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lola: FINISHED task # 51 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-02
lola: result : true
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lola: CANCELED task # 52 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 49 (type EQUN) for 21 DLCround-PT-09b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
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lola: LAUNCH task # 114 (type SRCH) for 21 DLCround-PT-09b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-52.sara.

lola: FINISHED task # 114 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-07
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
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lola: CANCELED task # 48 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 49 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 65 (type FNDP) for 9 DLCround-PT-09b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
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lola: LAUNCH task # 76 (type EQUN) for 9 DLCround-PT-09b-ReachabilityCardinality-03
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lola: LAUNCH task # 79 (type SRCH) for 9 DLCround-PT-09b-ReachabilityCardinality-03
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lola: FINISHED task # 48 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 145338675
lola: tried executions : 72669339
lola: time used : 73.000000
lola: memory pages used : 0
lola: FINISHED task # 52 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-02
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-07
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-147.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-76.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 4/1745 0/5 DLCround-PT-09b-ReachabilityCardinality-03 324780 t fired, 1 attempts, .
76 EF STEQ 4/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
79 EF SRCH 4/3491 2/5 DLCround-PT-09b-ReachabilityCardinality-03 295771 m, 59154 m/sec, 407366 t fired, .
80 EF EXCL 77/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 207314 m, 1918 m/sec, 378852 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 9/1741 0/5 DLCround-PT-09b-ReachabilityCardinality-03 857422 t fired, 1 attempts, .
76 EF STEQ 9/3487 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
79 EF SRCH 9/3487 3/5 DLCround-PT-09b-ReachabilityCardinality-03 696173 m, 80080 m/sec, 958790 t fired, .
80 EF EXCL 82/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 217098 m, 1956 m/sec, 397237 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 14/1736 0/5 DLCround-PT-09b-ReachabilityCardinality-03 1283414 t fired, 2 attempts, .
76 EF STEQ 14/3482 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
79 EF SRCH 14/3482 5/5 DLCround-PT-09b-ReachabilityCardinality-03 1096771 m, 80119 m/sec, 1510600 t fired, .
80 EF EXCL 87/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 226640 m, 1908 m/sec, 415343 t fired, .

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lola: FINISHED task # 147 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-00
lola: result : true
lola: CANCELED task # 79 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 1 3 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 19/1730 0/5 DLCround-PT-09b-ReachabilityCardinality-03 1466260 t fired, 2 attempts, .
76 EF STEQ 19/3476 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 92/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 238440 m, 2360 m/sec, 437853 t fired, .

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lola: LAUNCH task # 81 (type SRCH) for 9 DLCround-PT-09b-ReachabilityCardinality-03
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lola: FINISHED task # 81 (type SRCH) for DLCround-PT-09b-ReachabilityCardinality-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 24/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 1608345 t fired, 2 attempts, .
76 EF STEQ 24/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 97/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 250140 m, 2340 m/sec, 459688 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 29/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 1759838 t fired, 2 attempts, .
76 EF STEQ 29/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 102/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 262529 m, 2477 m/sec, 482911 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 34/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 1909738 t fired, 2 attempts, .
76 EF STEQ 34/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 107/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 277086 m, 2911 m/sec, 510520 t fired, .

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lola: FINISHED task # 118 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-11
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 39/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2053505 t fired, 3 attempts, .
76 EF STEQ 39/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 112/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 290528 m, 2688 m/sec, 536288 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 44/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2210303 t fired, 3 attempts, .
76 EF STEQ 44/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 117/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 305743 m, 3043 m/sec, 565111 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 49/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2367881 t fired, 3 attempts, .
76 EF STEQ 49/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 122/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 321846 m, 3220 m/sec, 595899 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 54/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2513365 t fired, 3 attempts, .
76 EF STEQ 54/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 127/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 336456 m, 2922 m/sec, 623284 t fired, .

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DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 59/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2691169 t fired, 3 attempts, .
76 EF STEQ 59/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 132/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 350635 m, 2835 m/sec, 650136 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 64/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2825423 t fired, 3 attempts, .
76 EF STEQ 64/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 137/3564 2/32 DLCround-PT-09b-ReachabilityCardinality-03 366168 m, 3106 m/sec, 679785 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 69/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 2985179 t fired, 3 attempts, .
76 EF STEQ 69/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 142/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 381423 m, 3051 m/sec, 708790 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 74/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 3129454 t fired, 4 attempts, .
76 EF STEQ 74/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 147/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 397777 m, 3270 m/sec, 739900 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 79/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 3275239 t fired, 4 attempts, .
76 EF STEQ 79/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 152/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 413207 m, 3086 m/sec, 769059 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 84/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 3415708 t fired, 4 attempts, .
76 EF STEQ 84/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 157/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 427889 m, 2936 m/sec, 796916 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 89/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 3541590 t fired, 4 attempts, .
76 EF STEQ 89/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 162/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 442500 m, 2922 m/sec, 824497 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-09b-ReachabilityCardinality-03: EF 0 0 3 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF FNDP 94/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 3669149 t fired, 4 attempts, .
76 EF STEQ 94/3491 0/5 DLCround-PT-09b-ReachabilityCardinality-03 sara is running.
80 EF EXCL 167/3564 3/32 DLCround-PT-09b-ReachabilityCardinality-03 458066 m, 3113 m/sec, 854114 t fired, .

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lola: FINISHED task # 76 (type EQUN) for DLCround-PT-09b-ReachabilityCardinality-03
lola: result : false
lola: CANCELED task # 65 (type FNDP) for DLCround-PT-09b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 80 (type EXCL) for DLCround-PT-09b-ReachabilityCardinality-03 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-09b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-03: EF false state equation
DLCround-PT-09b-ReachabilityCardinality-04: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-07: EF false tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-09: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-09b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-12: AG true tandem / insertion
DLCround-PT-09b-ReachabilityCardinality-13: AG true state equation
DLCround-PT-09b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-09b-ReachabilityCardinality-15: AG false findpath

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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-09b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-09b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478700726"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-09b.tgz
mv DLCround-PT-09b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;