About the Execution of LoLa+red for DLCround-PT-08a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6019.911 | 270342.00 | 263929.00 | 899.70 | ???FFFTFF?FT?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600698.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-08a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600698
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 948K
-rw-r--r-- 1 mcc users 6.4K Feb 25 19:02 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 19:02 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 18:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 18:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 19:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Feb 25 19:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 19:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 25 19:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 479K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-08a-CTLFireability-00
FORMULA_NAME DLCround-PT-08a-CTLFireability-01
FORMULA_NAME DLCround-PT-08a-CTLFireability-02
FORMULA_NAME DLCround-PT-08a-CTLFireability-03
FORMULA_NAME DLCround-PT-08a-CTLFireability-04
FORMULA_NAME DLCround-PT-08a-CTLFireability-05
FORMULA_NAME DLCround-PT-08a-CTLFireability-06
FORMULA_NAME DLCround-PT-08a-CTLFireability-07
FORMULA_NAME DLCround-PT-08a-CTLFireability-08
FORMULA_NAME DLCround-PT-08a-CTLFireability-09
FORMULA_NAME DLCround-PT-08a-CTLFireability-10
FORMULA_NAME DLCround-PT-08a-CTLFireability-11
FORMULA_NAME DLCround-PT-08a-CTLFireability-12
FORMULA_NAME DLCround-PT-08a-CTLFireability-13
FORMULA_NAME DLCround-PT-08a-CTLFireability-14
FORMULA_NAME DLCround-PT-08a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678275575740
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-08a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 11:39:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 11:39:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 11:39:37] [INFO ] Load time of PNML (sax parser for PT used): 97 ms
[2023-03-08 11:39:37] [INFO ] Transformed 263 places.
[2023-03-08 11:39:37] [INFO ] Transformed 1907 transitions.
[2023-03-08 11:39:37] [INFO ] Found NUPN structural information;
[2023-03-08 11:39:37] [INFO ] Parsed PT model containing 263 places and 1907 transitions and 7354 arcs in 166 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Ensure Unique test removed 187 transitions
Reduce redundant transitions removed 187 transitions.
Support contains 124 out of 263 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 263/263 places, 1720/1720 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 255 transition count 1628
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 255 transition count 1628
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 18 place count 255 transition count 1626
Drop transitions removed 576 transitions
Redundant transition composition rules discarded 576 transitions
Iterating global reduction 1 with 576 rules applied. Total rules applied 594 place count 255 transition count 1050
Applied a total of 594 rules in 68 ms. Remains 255 /263 variables (removed 8) and now considering 1050/1720 (removed 670) transitions.
[2023-03-08 11:39:37] [INFO ] Flow matrix only has 176 transitions (discarded 874 similar events)
// Phase 1: matrix 176 rows 255 cols
[2023-03-08 11:39:37] [INFO ] Computed 157 place invariants in 17 ms
[2023-03-08 11:39:38] [INFO ] Implicit Places using invariants in 655 ms returned [111, 112, 113, 114, 115, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 131, 133, 134, 135, 137, 138, 139, 141, 143, 145, 147, 151, 152, 153, 154, 155, 157, 161, 162, 163, 165, 166, 167, 168, 169, 172, 173, 175, 176, 177, 179, 180, 182, 183, 187, 188, 189, 192, 193, 194, 198, 200, 204, 205, 209, 212, 214, 215, 220, 221, 222, 223, 224, 225, 227, 230, 231, 234, 235, 237, 238, 239, 242, 247, 252]
Discarding 81 places :
Ensure Unique test removed 391 transitions
Reduce isomorphic transitions removed 391 transitions.
Implicit Place search using SMT only with invariants took 680 ms to find 81 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 174/263 places, 659/1720 transitions.
Drop transitions removed 422 transitions
Redundant transition composition rules discarded 422 transitions
Iterating global reduction 0 with 422 rules applied. Total rules applied 422 place count 174 transition count 237
Applied a total of 422 rules in 7 ms. Remains 174 /174 variables (removed 0) and now considering 237/659 (removed 422) transitions.
[2023-03-08 11:39:38] [INFO ] Flow matrix only has 176 transitions (discarded 61 similar events)
// Phase 1: matrix 176 rows 174 cols
[2023-03-08 11:39:38] [INFO ] Computed 76 place invariants in 2 ms
[2023-03-08 11:39:38] [INFO ] Implicit Places using invariants in 72 ms returned []
[2023-03-08 11:39:38] [INFO ] Flow matrix only has 176 transitions (discarded 61 similar events)
[2023-03-08 11:39:38] [INFO ] Invariant cache hit.
[2023-03-08 11:39:38] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 11:39:38] [INFO ] Implicit Places using invariants and state equation in 93 ms returned []
Implicit Place search using SMT with State Equation took 166 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 174/263 places, 237/1720 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 922 ms. Remains : 174/263 places, 237/1720 transitions.
Support contains 124 out of 174 places after structural reductions.
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 36 ms
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 14 ms
[2023-03-08 11:39:38] [INFO ] Input system was already deterministic with 237 transitions.
Finished random walk after 5054 steps, including 1 resets, run visited all 74 properties in 147 ms. (steps per millisecond=34 )
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 15 ms
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 10 ms
[2023-03-08 11:39:38] [INFO ] Input system was already deterministic with 237 transitions.
Computed a total of 64 stabilizing places and 1 stable transitions
Graph (complete) has 312 edges and 174 vertex of which 111 are kept as prefixes of interest. Removing 63 places using SCC suffix rule.2 ms
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 60 places and 0 transitions.
Iterating post reduction 0 with 60 rules applied. Total rules applied 60 place count 114 transition count 237
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 77 place count 97 transition count 203
Iterating global reduction 1 with 17 rules applied. Total rules applied 94 place count 97 transition count 203
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 96 place count 97 transition count 201
Applied a total of 96 rules in 4 ms. Remains 97 /174 variables (removed 77) and now considering 201/237 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 97/174 places, 201/237 transitions.
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 11 ms
[2023-03-08 11:39:38] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:38] [INFO ] Input system was already deterministic with 201 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 61 places and 0 transitions.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 113 transition count 237
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 78 place count 96 transition count 203
Iterating global reduction 1 with 17 rules applied. Total rules applied 95 place count 96 transition count 203
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 97 place count 96 transition count 201
Applied a total of 97 rules in 4 ms. Remains 96 /174 variables (removed 78) and now considering 201/237 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 96/174 places, 201/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 201 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 62 places and 0 transitions.
Iterating post reduction 0 with 62 rules applied. Total rules applied 62 place count 112 transition count 237
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 79 place count 95 transition count 203
Iterating global reduction 1 with 17 rules applied. Total rules applied 96 place count 95 transition count 203
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 98 place count 95 transition count 201
Applied a total of 98 rules in 3 ms. Remains 95 /174 variables (removed 79) and now considering 201/237 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 95/174 places, 201/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 201 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 221 edges and 174 vertex of which 96 / 174 are part of one of the 13 SCC in 2 ms
Free SCC test removed 83 places
Ensure Unique test removed 190 transitions
Reduce isomorphic transitions removed 190 transitions.
Graph (complete) has 122 edges and 91 vertex of which 30 are kept as prefixes of interest. Removing 61 places using SCC suffix rule.1 ms
Discarding 61 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 30 transition count 45
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 28 transition count 45
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 18 place count 16 transition count 31
Iterating global reduction 2 with 12 rules applied. Total rules applied 30 place count 16 transition count 31
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 2 with 3 rules applied. Total rules applied 33 place count 16 transition count 28
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 34 place count 16 transition count 28
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 35 place count 15 transition count 27
Iterating global reduction 2 with 1 rules applied. Total rules applied 36 place count 15 transition count 27
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 37 place count 15 transition count 26
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 38 place count 15 transition count 25
Applied a total of 38 rules in 13 ms. Remains 15 /174 variables (removed 159) and now considering 25/237 (removed 212) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 15/174 places, 25/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 25 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 213 edges and 174 vertex of which 91 / 174 are part of one of the 13 SCC in 1 ms
Free SCC test removed 78 places
Ensure Unique test removed 179 transitions
Reduce isomorphic transitions removed 179 transitions.
Graph (complete) has 133 edges and 96 vertex of which 37 are kept as prefixes of interest. Removing 59 places using SCC suffix rule.1 ms
Discarding 59 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 4 place count 37 transition count 56
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 35 transition count 56
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 15 place count 26 transition count 46
Iterating global reduction 2 with 9 rules applied. Total rules applied 24 place count 26 transition count 46
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 26 place count 26 transition count 44
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 28 place count 26 transition count 44
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 30 place count 24 transition count 42
Iterating global reduction 2 with 2 rules applied. Total rules applied 32 place count 24 transition count 42
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 34 place count 24 transition count 40
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 36 place count 24 transition count 38
Applied a total of 36 rules in 8 ms. Remains 24 /174 variables (removed 150) and now considering 38/237 (removed 199) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 24/174 places, 38/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 38 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 228 edges and 174 vertex of which 101 / 174 are part of one of the 13 SCC in 0 ms
Free SCC test removed 88 places
Ensure Unique test removed 203 transitions
Reduce isomorphic transitions removed 203 transitions.
Graph (complete) has 109 edges and 86 vertex of which 25 are kept as prefixes of interest. Removing 61 places using SCC suffix rule.0 ms
Discarding 61 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 25 transition count 33
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 24 transition count 32
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 6 place count 23 transition count 32
Discarding 11 places :
Symmetric choice reduction at 3 with 11 rule applications. Total rules 17 place count 12 transition count 20
Iterating global reduction 3 with 11 rules applied. Total rules applied 28 place count 12 transition count 20
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 3 with 3 rules applied. Total rules applied 31 place count 12 transition count 17
Applied a total of 31 rules in 4 ms. Remains 12 /174 variables (removed 162) and now considering 17/237 (removed 220) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 12/174 places, 17/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 226 edges and 174 vertex of which 102 / 174 are part of one of the 13 SCC in 0 ms
Free SCC test removed 89 places
Ensure Unique test removed 204 transitions
Reduce isomorphic transitions removed 204 transitions.
Graph (complete) has 108 edges and 85 vertex of which 23 are kept as prefixes of interest. Removing 62 places using SCC suffix rule.0 ms
Discarding 62 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 23 transition count 32
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 22 transition count 32
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 16 place count 10 transition count 19
Iterating global reduction 2 with 12 rules applied. Total rules applied 28 place count 10 transition count 19
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 29 place count 10 transition count 18
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 30 place count 10 transition count 18
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 31 place count 9 transition count 17
Iterating global reduction 2 with 1 rules applied. Total rules applied 32 place count 9 transition count 17
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 33 place count 9 transition count 16
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 34 place count 9 transition count 15
Applied a total of 34 rules in 4 ms. Remains 9 /174 variables (removed 165) and now considering 15/237 (removed 222) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 9/174 places, 15/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 62 places and 0 transitions.
Iterating post reduction 0 with 62 rules applied. Total rules applied 62 place count 112 transition count 237
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 80 place count 94 transition count 201
Iterating global reduction 1 with 18 rules applied. Total rules applied 98 place count 94 transition count 201
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 100 place count 94 transition count 199
Applied a total of 100 rules in 2 ms. Remains 94 /174 variables (removed 80) and now considering 199/237 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/174 places, 199/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 199 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 53 places and 0 transitions.
Iterating post reduction 0 with 53 rules applied. Total rules applied 53 place count 121 transition count 237
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 62 place count 112 transition count 219
Iterating global reduction 1 with 9 rules applied. Total rules applied 71 place count 112 transition count 219
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 73 place count 112 transition count 217
Applied a total of 73 rules in 2 ms. Remains 112 /174 variables (removed 62) and now considering 217/237 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 112/174 places, 217/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 7 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 217 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 50 places and 0 transitions.
Iterating post reduction 0 with 50 rules applied. Total rules applied 50 place count 124 transition count 237
Discarding 12 places :
Symmetric choice reduction at 1 with 12 rule applications. Total rules 62 place count 112 transition count 213
Iterating global reduction 1 with 12 rules applied. Total rules applied 74 place count 112 transition count 213
Applied a total of 74 rules in 2 ms. Remains 112 /174 variables (removed 62) and now considering 213/237 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 112/174 places, 213/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 213 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 57 places and 0 transitions.
Iterating post reduction 0 with 57 rules applied. Total rules applied 57 place count 117 transition count 237
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 71 place count 103 transition count 209
Iterating global reduction 1 with 14 rules applied. Total rules applied 85 place count 103 transition count 209
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 87 place count 103 transition count 207
Applied a total of 87 rules in 2 ms. Remains 103 /174 variables (removed 71) and now considering 207/237 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 103/174 places, 207/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 207 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 57 places and 0 transitions.
Iterating post reduction 0 with 57 rules applied. Total rules applied 57 place count 117 transition count 237
Discarding 13 places :
Symmetric choice reduction at 1 with 13 rule applications. Total rules 70 place count 104 transition count 211
Iterating global reduction 1 with 13 rules applied. Total rules applied 83 place count 104 transition count 211
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 84 place count 104 transition count 210
Applied a total of 84 rules in 3 ms. Remains 104 /174 variables (removed 70) and now considering 210/237 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/174 places, 210/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 6 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 210 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 58 places and 0 transitions.
Iterating post reduction 0 with 58 rules applied. Total rules applied 58 place count 116 transition count 237
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 74 place count 100 transition count 205
Iterating global reduction 1 with 16 rules applied. Total rules applied 90 place count 100 transition count 205
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 92 place count 100 transition count 203
Applied a total of 92 rules in 2 ms. Remains 100 /174 variables (removed 74) and now considering 203/237 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 100/174 places, 203/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 203 transitions.
Starting structural reductions in LTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Reduce places removed 55 places and 0 transitions.
Iterating post reduction 0 with 55 rules applied. Total rules applied 55 place count 119 transition count 237
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 70 place count 104 transition count 207
Iterating global reduction 1 with 15 rules applied. Total rules applied 85 place count 104 transition count 207
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 87 place count 104 transition count 205
Applied a total of 87 rules in 3 ms. Remains 104 /174 variables (removed 70) and now considering 205/237 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/174 places, 205/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 205 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 185 edges and 174 vertex of which 67 / 174 are part of one of the 11 SCC in 0 ms
Free SCC test removed 56 places
Ensure Unique test removed 130 transitions
Reduce isomorphic transitions removed 130 transitions.
Graph (complete) has 182 edges and 118 vertex of which 63 are kept as prefixes of interest. Removing 55 places using SCC suffix rule.0 ms
Discarding 55 places :
Also discarding 0 output transitions
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 5 place count 63 transition count 104
Reduce places removed 3 places and 0 transitions.
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Iterating post reduction 1 with 8 rules applied. Total rules applied 13 place count 60 transition count 99
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 18 place count 55 transition count 99
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 25 place count 48 transition count 89
Iterating global reduction 3 with 7 rules applied. Total rules applied 32 place count 48 transition count 89
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 36 place count 48 transition count 85
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 4 rules applied. Total rules applied 40 place count 46 transition count 83
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 5 with 6 rules applied. Total rules applied 46 place count 46 transition count 77
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 5 with 3 rules applied. Total rules applied 49 place count 46 transition count 77
Discarding 3 places :
Symmetric choice reduction at 5 with 3 rule applications. Total rules 52 place count 43 transition count 74
Iterating global reduction 5 with 3 rules applied. Total rules applied 55 place count 43 transition count 74
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 58 place count 43 transition count 71
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 6 with 3 rules applied. Total rules applied 61 place count 43 transition count 68
Applied a total of 61 rules in 12 ms. Remains 43 /174 variables (removed 131) and now considering 68/237 (removed 169) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 43/174 places, 68/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 68 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 174/174 places, 237/237 transitions.
Graph (trivial) has 208 edges and 174 vertex of which 89 / 174 are part of one of the 12 SCC in 0 ms
Free SCC test removed 77 places
Ensure Unique test removed 179 transitions
Reduce isomorphic transitions removed 179 transitions.
Graph (complete) has 133 edges and 97 vertex of which 40 are kept as prefixes of interest. Removing 57 places using SCC suffix rule.0 ms
Discarding 57 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 40 transition count 57
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 1 with 4 rules applied. Total rules applied 7 place count 39 transition count 54
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 11 place count 36 transition count 53
Discarding 8 places :
Symmetric choice reduction at 3 with 8 rule applications. Total rules 19 place count 28 transition count 44
Iterating global reduction 3 with 8 rules applied. Total rules applied 27 place count 28 transition count 44
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 29 place count 28 transition count 42
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 30 place count 28 transition count 42
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 31 place count 27 transition count 41
Iterating global reduction 3 with 1 rules applied. Total rules applied 32 place count 27 transition count 41
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 33 place count 27 transition count 40
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 34 place count 27 transition count 39
Applied a total of 34 rules in 6 ms. Remains 27 /174 variables (removed 147) and now considering 39/237 (removed 198) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 27/174 places, 39/237 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:39:39] [INFO ] Input system was already deterministic with 39 transitions.
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 7 ms
[2023-03-08 11:39:39] [INFO ] Flatten gal took : 7 ms
[2023-03-08 11:39:39] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 11:39:39] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 174 places, 237 transitions and 549 arcs took 1 ms.
Total runtime 2346 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-08a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DLCround-PT-08a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678275846082
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-08a-CTLFireability-01
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:746
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 63 (type FNDP) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type EQUN) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type SRCH) for 53 DLCround-PT-08a-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 66 (type SRCH) for DLCround-PT-08a-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 63 (type FNDP) for DLCround-PT-08a-CTLFireability-15
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 64 (type EQUN) for DLCround-PT-08a-CTLFireability-15 (obsolete)
lola: FINISHED task # 64 (type EQUN) for DLCround-PT-08a-CTLFireability-15
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/211 4/32 DLCround-PT-08a-CTLFireability-01 709721 m, 141944 m/sec, 4881144 t fired, .
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DLCround-PT-08a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/211 7/32 DLCround-PT-08a-CTLFireability-01 1503160 m, 158687 m/sec, 9238668 t fired, .
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DLCround-PT-08a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/211 10/32 DLCround-PT-08a-CTLFireability-01 2135361 m, 126440 m/sec, 13704253 t fired, .
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DLCround-PT-08a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/211 14/32 DLCround-PT-08a-CTLFireability-01 2920518 m, 157031 m/sec, 18481040 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/211 17/32 DLCround-PT-08a-CTLFireability-01 3647093 m, 145315 m/sec, 22925688 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/211 21/32 DLCround-PT-08a-CTLFireability-01 4372417 m, 145064 m/sec, 27334869 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/211 24/32 DLCround-PT-08a-CTLFireability-01 5103072 m, 146131 m/sec, 31636217 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/211 27/32 DLCround-PT-08a-CTLFireability-01 5831687 m, 145723 m/sec, 35940261 t fired, .
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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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4 CTL EXCL 45/211 30/32 DLCround-PT-08a-CTLFireability-01 6558374 m, 145337 m/sec, 40245560 t fired, .
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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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lola: result : true
lola: markings : 4
lola: fired transitions : 6
lola: time used : 0.000000
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DLCround-PT-08a-CTLFireability-15: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/253 5/32 DLCround-PT-08a-CTLFireability-12 1014666 m, 202933 m/sec, 4021745 t fired, .
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/253 9/32 DLCround-PT-08a-CTLFireability-12 1900715 m, 177209 m/sec, 7675142 t fired, .
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DLCround-PT-08a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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41 CTL EXCL 15/253 14/32 DLCround-PT-08a-CTLFireability-12 2812797 m, 182416 m/sec, 11203663 t fired, .
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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DLCround-PT-08a-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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DLCround-PT-08a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-08a-CTLFireability-06: AGEF 0 1 0 0 1 0 0 0
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lola: result : true
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lola: result : false
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lola: result : true
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-CTLFireability-00: CTL unknown AGGR
DLCround-PT-08a-CTLFireability-01: CTL unknown AGGR
DLCround-PT-08a-CTLFireability-02: CTL unknown AGGR
DLCround-PT-08a-CTLFireability-03: CONJ false tscc_search
DLCround-PT-08a-CTLFireability-04: CTL false CTL model checker
DLCround-PT-08a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-08a-CTLFireability-06: AGEF true tscc_search
DLCround-PT-08a-CTLFireability-07: CTL false CTL model checker
DLCround-PT-08a-CTLFireability-08: CTL false CTL model checker
DLCround-PT-08a-CTLFireability-09: CTL unknown AGGR
DLCround-PT-08a-CTLFireability-10: CTL false CTL model checker
DLCround-PT-08a-CTLFireability-11: CTL true CTL model checker
DLCround-PT-08a-CTLFireability-12: CTL unknown AGGR
DLCround-PT-08a-CTLFireability-13: CONJ true CONJ
DLCround-PT-08a-CTLFireability-14: CTL true CTL model checker
DLCround-PT-08a-CTLFireability-15: CONJ false findpath
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-08a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600698"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;