About the Execution of LoLa+red for DLCround-PT-07b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1122.163 | 42442.00 | 90705.00 | 508.50 | TFFFFFTFTFTFTTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600694.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-07b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600694
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 7.4K Feb 25 18:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 18:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 18:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 18:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.3K Feb 25 18:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 18:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 18:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 25 18:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 963K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-07b-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678275158794
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-07b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 11:32:40] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 11:32:40] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 11:32:40] [INFO ] Load time of PNML (sax parser for PT used): 140 ms
[2023-03-08 11:32:40] [INFO ] Transformed 2703 places.
[2023-03-08 11:32:40] [INFO ] Transformed 4071 transitions.
[2023-03-08 11:32:40] [INFO ] Found NUPN structural information;
[2023-03-08 11:32:40] [INFO ] Parsed PT model containing 2703 places and 4071 transitions and 11073 arcs in 270 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 15 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-07b-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 389 ms. (steps per millisecond=25 ) properties (out of 15) seen :8
FORMULA DLCround-PT-07b-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-07 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
// Phase 1: matrix 4071 rows 2703 cols
[2023-03-08 11:32:41] [INFO ] Computed 132 place invariants in 40 ms
[2023-03-08 11:32:42] [INFO ] After 1001ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-08 11:32:43] [INFO ] [Nat]Absence check using 132 positive place invariants in 102 ms returned sat
[2023-03-08 11:32:45] [INFO ] After 2087ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-03-08 11:32:46] [INFO ] Deduced a trap composed of 107 places in 518 ms of which 40 ms to minimize.
[2023-03-08 11:32:47] [INFO ] Deduced a trap composed of 137 places in 406 ms of which 1 ms to minimize.
[2023-03-08 11:32:47] [INFO ] Deduced a trap composed of 130 places in 425 ms of which 2 ms to minimize.
[2023-03-08 11:32:48] [INFO ] Deduced a trap composed of 151 places in 425 ms of which 2 ms to minimize.
[2023-03-08 11:32:48] [INFO ] Deduced a trap composed of 144 places in 352 ms of which 2 ms to minimize.
[2023-03-08 11:32:49] [INFO ] Deduced a trap composed of 158 places in 378 ms of which 1 ms to minimize.
[2023-03-08 11:32:49] [INFO ] Deduced a trap composed of 180 places in 379 ms of which 1 ms to minimize.
[2023-03-08 11:32:50] [INFO ] Deduced a trap composed of 222 places in 355 ms of which 2 ms to minimize.
[2023-03-08 11:32:50] [INFO ] Trap strengthening (SAT) tested/added 9/8 trap constraints in 4251 ms
[2023-03-08 11:32:50] [INFO ] Deduced a trap composed of 160 places in 285 ms of which 1 ms to minimize.
[2023-03-08 11:32:51] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 532 ms
[2023-03-08 11:32:51] [INFO ] Deduced a trap composed of 168 places in 257 ms of which 1 ms to minimize.
[2023-03-08 11:32:51] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 486 ms
[2023-03-08 11:32:52] [INFO ] After 8552ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 907 ms.
[2023-03-08 11:32:53] [INFO ] After 10459ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
FORMULA DLCround-PT-07b-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-02 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA DLCround-PT-07b-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 5 properties in 244 ms.
Support contains 51 out of 2703 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 2703/2703 places, 4071/4071 transitions.
Graph (trivial) has 2452 edges and 2703 vertex of which 357 / 2703 are part of one of the 34 SCC in 10 ms
Free SCC test removed 323 places
Drop transitions removed 366 transitions
Reduce isomorphic transitions removed 366 transitions.
Drop transitions removed 1033 transitions
Trivial Post-agglo rules discarded 1033 transitions
Performed 1033 trivial Post agglomeration. Transition count delta: 1033
Iterating post reduction 0 with 1033 rules applied. Total rules applied 1034 place count 2380 transition count 2672
Reduce places removed 1033 places and 0 transitions.
Ensure Unique test removed 34 transitions
Reduce isomorphic transitions removed 34 transitions.
Drop transitions removed 25 transitions
Trivial Post-agglo rules discarded 25 transitions
Performed 25 trivial Post agglomeration. Transition count delta: 25
Iterating post reduction 1 with 1092 rules applied. Total rules applied 2126 place count 1347 transition count 2613
Reduce places removed 25 places and 0 transitions.
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 2 with 31 rules applied. Total rules applied 2157 place count 1322 transition count 2607
Reduce places removed 3 places and 0 transitions.
Performed 34 Post agglomeration using F-continuation condition.Transition count delta: 34
Iterating post reduction 3 with 37 rules applied. Total rules applied 2194 place count 1319 transition count 2573
Reduce places removed 34 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 35 rules applied. Total rules applied 2229 place count 1285 transition count 2572
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 19 Pre rules applied. Total rules applied 2229 place count 1285 transition count 2553
Deduced a syphon composed of 19 places in 20 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 5 with 38 rules applied. Total rules applied 2267 place count 1266 transition count 2553
Discarding 301 places :
Symmetric choice reduction at 5 with 301 rule applications. Total rules 2568 place count 965 transition count 2252
Iterating global reduction 5 with 301 rules applied. Total rules applied 2869 place count 965 transition count 2252
Performed 124 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 124 Pre rules applied. Total rules applied 2869 place count 965 transition count 2128
Deduced a syphon composed of 124 places in 7 ms
Reduce places removed 124 places and 0 transitions.
Iterating global reduction 5 with 248 rules applied. Total rules applied 3117 place count 841 transition count 2128
Discarding 40 places :
Symmetric choice reduction at 5 with 40 rule applications. Total rules 3157 place count 801 transition count 1694
Iterating global reduction 5 with 40 rules applied. Total rules applied 3197 place count 801 transition count 1694
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 5 with 9 rules applied. Total rules applied 3206 place count 801 transition count 1685
Performed 215 Post agglomeration using F-continuation condition with reduction of 7 identical transitions.
Deduced a syphon composed of 215 places in 2 ms
Reduce places removed 215 places and 0 transitions.
Iterating global reduction 6 with 430 rules applied. Total rules applied 3636 place count 586 transition count 1463
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 3639 place count 586 transition count 1460
Discarding 7 places :
Symmetric choice reduction at 7 with 7 rule applications. Total rules 3646 place count 579 transition count 1383
Iterating global reduction 7 with 7 rules applied. Total rules applied 3653 place count 579 transition count 1383
Performed 67 Post agglomeration using F-continuation condition.Transition count delta: -564
Deduced a syphon composed of 67 places in 1 ms
Reduce places removed 67 places and 0 transitions.
Iterating global reduction 7 with 134 rules applied. Total rules applied 3787 place count 512 transition count 1947
Drop transitions removed 77 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 84 transitions.
Iterating post reduction 7 with 84 rules applied. Total rules applied 3871 place count 512 transition count 1863
Discarding 17 places :
Symmetric choice reduction at 8 with 17 rule applications. Total rules 3888 place count 495 transition count 1495
Iterating global reduction 8 with 17 rules applied. Total rules applied 3905 place count 495 transition count 1495
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 8 with 10 rules applied. Total rules applied 3915 place count 495 transition count 1485
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: -47
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 9 with 10 rules applied. Total rules applied 3925 place count 490 transition count 1532
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 9 with 3 rules applied. Total rules applied 3928 place count 490 transition count 1529
Drop transitions removed 164 transitions
Redundant transition composition rules discarded 164 transitions
Iterating global reduction 10 with 164 rules applied. Total rules applied 4092 place count 490 transition count 1365
Discarding 7 places :
Symmetric choice reduction at 10 with 7 rule applications. Total rules 4099 place count 483 transition count 1273
Iterating global reduction 10 with 7 rules applied. Total rules applied 4106 place count 483 transition count 1273
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 10 with 8 rules applied. Total rules applied 4114 place count 483 transition count 1265
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 4116 place count 482 transition count 1264
Discarding 1 places :
Symmetric choice reduction at 11 with 1 rule applications. Total rules 4117 place count 481 transition count 1253
Iterating global reduction 11 with 1 rules applied. Total rules applied 4118 place count 481 transition count 1253
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 4119 place count 481 transition count 1252
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 12 with 6 rules applied. Total rules applied 4125 place count 478 transition count 1275
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 12 with 2 rules applied. Total rules applied 4127 place count 478 transition count 1273
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 13 with 13 rules applied. Total rules applied 4140 place count 478 transition count 1260
Discarding 1 places :
Symmetric choice reduction at 13 with 1 rule applications. Total rules 4141 place count 477 transition count 1249
Iterating global reduction 13 with 1 rules applied. Total rules applied 4142 place count 477 transition count 1249
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 4143 place count 477 transition count 1248
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 14 with 2 rules applied. Total rules applied 4145 place count 476 transition count 1258
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 14 with 1 rules applied. Total rules applied 4146 place count 476 transition count 1257
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 15 with 9 rules applied. Total rules applied 4155 place count 476 transition count 1248
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 15 with 2 rules applied. Total rules applied 4157 place count 475 transition count 1259
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 4158 place count 475 transition count 1258
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 16 with 1 rules applied. Total rules applied 4159 place count 475 transition count 1257
Free-agglomeration rule applied 207 times with reduction of 85 identical transitions.
Iterating global reduction 16 with 207 rules applied. Total rules applied 4366 place count 475 transition count 965
Reduce places removed 207 places and 0 transitions.
Drop transitions removed 259 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 266 transitions.
Graph (complete) has 812 edges and 268 vertex of which 261 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.1 ms
Discarding 7 places :
Also discarding 0 output transitions
Iterating post reduction 16 with 474 rules applied. Total rules applied 4840 place count 261 transition count 699
Discarding 22 places :
Symmetric choice reduction at 17 with 22 rule applications. Total rules 4862 place count 239 transition count 657
Iterating global reduction 17 with 22 rules applied. Total rules applied 4884 place count 239 transition count 657
Drop transitions removed 84 transitions
Redundant transition composition rules discarded 84 transitions
Iterating global reduction 17 with 84 rules applied. Total rules applied 4968 place count 239 transition count 573
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 17 with 3 rules applied. Total rules applied 4971 place count 236 transition count 573
Discarding 11 places :
Symmetric choice reduction at 18 with 11 rule applications. Total rules 4982 place count 225 transition count 552
Iterating global reduction 18 with 11 rules applied. Total rules applied 4993 place count 225 transition count 552
Free-agglomeration rule applied 1 times.
Iterating global reduction 18 with 1 rules applied. Total rules applied 4994 place count 225 transition count 551
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 4995 place count 224 transition count 551
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 19 with 1 rules applied. Total rules applied 4996 place count 224 transition count 565
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 19 with 10 rules applied. Total rules applied 5006 place count 223 transition count 556
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 20 with 6 rules applied. Total rules applied 5012 place count 223 transition count 550
Partial Free-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 20 with 4 rules applied. Total rules applied 5016 place count 223 transition count 550
Applied a total of 5016 rules in 824 ms. Remains 223 /2703 variables (removed 2480) and now considering 550/4071 (removed 3521) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 824 ms. Remains : 223/2703 places, 550/4071 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 2) seen :1
FORMULA DLCround-PT-07b-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Finished Best-First random walk after 5941 steps, including 1 resets, run visited all 1 properties in 12 ms. (steps per millisecond=495 )
FORMULA DLCround-PT-07b-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
All properties solved without resorting to model-checking.
Total runtime 14195 ms.
starting LoLA
BK_INPUT DLCround-PT-07b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCround-PT-07b-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-07b-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678275201236
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 72 (type EXCL) for 24 DLCround-PT-07b-ReachabilityCardinality-08
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 56 (type FNDP) for 24 DLCround-PT-07b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 24 DLCround-PT-07b-ReachabilityCardinality-08
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 24 DLCround-PT-07b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 72 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-08
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 56 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 69 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 71 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 92 (type EXCL) for 21 DLCround-PT-07b-ReachabilityCardinality-07
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 3 DLCround-PT-07b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 3 DLCround-PT-07b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type FNDP) for 18 DLCround-PT-07b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-08
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 69 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-08
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 49 (type FNDP) for 39 DLCround-PT-07b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 66 (type FNDP) for 30 DLCround-PT-07b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type EQUN) for 30 DLCround-PT-07b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 59 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-01
lola: result : unknown
lola: FINISHED task # 66 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 80 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 84 (type FNDP) for 9 DLCround-PT-07b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type EQUN) for 9 DLCround-PT-07b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 84 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 102 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 51 (type FNDP) for 0 DLCround-PT-07b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type EQUN) for 0 DLCround-PT-07b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 50 (type FNDP) for 12 DLCround-PT-07b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 104 (type FNDP) for 42 DLCround-PT-07b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 52 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 112 (type FNDP) for 36 DLCround-PT-07b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 132 (type EQUN) for 36 DLCround-PT-07b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 132 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 101 (type FNDP) for 6 DLCround-PT-07b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type EQUN) for 6 DLCround-PT-07b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-80.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-102.sara.
lola: FINISHED task # 80 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-10
lola: result : true
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 92 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-07
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 137 (type EXCL) for 45 DLCround-PT-07b-ReachabilityCardinality-15
lola: time limit : 597 sec
lola: memory limit: 32 pages
lola: FINISHED task # 102 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-03
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-52.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 101 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 105 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 97 (type FNDP) for 15 DLCround-PT-07b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type EQUN) for 15 DLCround-PT-07b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 97 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 44
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 129 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 127 (type FNDP) for 33 DLCround-PT-07b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type EQUN) for 33 DLCround-PT-07b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-132.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 127 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 138 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 99 (type FNDP) for 27 DLCround-PT-07b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 117 (type EQUN) for 27 DLCround-PT-07b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-00
lola: result : true
lola: FINISHED task # 99 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 117 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 122 (type EQUN) for 42 DLCround-PT-07b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type SRCH) for 42 DLCround-PT-07b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-138.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-129.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-117.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-122.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-105.sara.
lola: FINISHED task # 117 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-09
lola: result : true
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 138 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-11
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-07: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-09: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-12: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-14: AG 0 2 3 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-15: AG 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
104 EF FNDP 3/1790 0/5 DLCround-PT-07b-ReachabilityCardinality-14 553037 t fired, 1 attempts, .
122 EF STEQ 2/1193 0/5 DLCround-PT-07b-ReachabilityCardinality-14 sara is running.
130 EF SRCH 2/1193 2/5 DLCround-PT-07b-ReachabilityCardinality-14 333468 m, 66693 m/sec, 486025 t fired, .
137 EF EXCL 2/1793 1/32 DLCround-PT-07b-ReachabilityCardinality-15 9845 m, 1969 m/sec, 16565 t fired, .
Time elapsed: 16 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 132 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-12
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-07: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-09: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-12: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-07b-ReachabilityCardinality-14: AG 0 2 3 0 1 0 0 0
DLCround-PT-07b-ReachabilityCardinality-15: AG 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
104 EF FNDP 9/1789 0/5 DLCround-PT-07b-ReachabilityCardinality-14 1502404 t fired, 2 attempts, .
122 EF STEQ 8/1192 0/5 DLCround-PT-07b-ReachabilityCardinality-14 sara is running.
130 EF SRCH 8/1192 5/5 DLCround-PT-07b-ReachabilityCardinality-14 1234782 m, 180262 m/sec, 1807685 t fired, .
137 EF EXCL 8/1793 1/32 DLCround-PT-07b-ReachabilityCardinality-15 30889 m, 4208 m/sec, 53821 t fired, .
Time elapsed: 22 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 130 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-14 (memory limit exceeded)
lola: FINISHED task # 122 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 104 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 85 (type FNDP) for 45 DLCround-PT-07b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 110 (type EQUN) for 45 DLCround-PT-07b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 136 (type SRCH) for 45 DLCround-PT-07b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 104 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 2127562
lola: tried executions : 4
lola: time used : 13.000000
lola: memory pages used : 0
lola: FINISHED task # 136 (type SRCH) for DLCround-PT-07b-ReachabilityCardinality-15
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 85 (type FNDP) for DLCround-PT-07b-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 110 (type EQUN) for DLCround-PT-07b-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 137 (type EXCL) for DLCround-PT-07b-ReachabilityCardinality-15 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-07b-ReachabilityCardinality-00: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-01: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-02: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-05: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-06: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-07: AG false tandem / relaxed
DLCround-PT-07b-ReachabilityCardinality-08: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-09: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-10: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-07b-ReachabilityCardinality-12: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-07b-ReachabilityCardinality-14: AG true state equation
DLCround-PT-07b-ReachabilityCardinality-15: AG false tandem / insertion
Time elapsed: 26 secs. Pages in use: 6
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-07b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-07b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600694"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-07b.tgz
mv DLCround-PT-07b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;