Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600678.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-06b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600678
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.5K Feb 25 18:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 18:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 18:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K Feb 25 18:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.8K Feb 25 18:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 18:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 18:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 22K Feb 25 18:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 813K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-06b-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678273703829

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-06b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 11:08:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 11:08:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 11:08:25] [INFO ] Load time of PNML (sax parser for PT used): 133 ms
[2023-03-08 11:08:25] [INFO ] Transformed 2340 places.
[2023-03-08 11:08:25] [INFO ] Transformed 3456 transitions.
[2023-03-08 11:08:25] [INFO ] Found NUPN structural information;
[2023-03-08 11:08:25] [INFO ] Parsed PT model containing 2340 places and 3456 transitions and 9288 arcs in 227 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 11 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-06b-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-06b-ReachabilityCardinality-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 333 ms. (steps per millisecond=30 ) properties (out of 14) seen :11
FORMULA DLCround-PT-06b-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 3456 rows 2340 cols
[2023-03-08 11:08:26] [INFO ] Computed 109 place invariants in 36 ms
[2023-03-08 11:08:26] [INFO ] After 831ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-08 11:08:27] [INFO ] [Nat]Absence check using 109 positive place invariants in 78 ms returned sat
[2023-03-08 11:08:28] [INFO ] After 1384ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-08 11:08:29] [INFO ] Deduced a trap composed of 159 places in 459 ms of which 10 ms to minimize.
[2023-03-08 11:08:29] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 669 ms
[2023-03-08 11:08:30] [INFO ] After 2553ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 342 ms.
[2023-03-08 11:08:30] [INFO ] After 3544ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Parikh walk visited 0 properties in 90 ms.
Support contains 25 out of 2340 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 2340/2340 places, 3456/3456 transitions.
Graph (trivial) has 2176 edges and 2340 vertex of which 388 / 2340 are part of one of the 33 SCC in 10 ms
Free SCC test removed 355 places
Drop transitions removed 400 transitions
Reduce isomorphic transitions removed 400 transitions.
Drop transitions removed 896 transitions
Trivial Post-agglo rules discarded 896 transitions
Performed 896 trivial Post agglomeration. Transition count delta: 896
Iterating post reduction 0 with 896 rules applied. Total rules applied 897 place count 1985 transition count 2160
Reduce places removed 896 places and 0 transitions.
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Drop transitions removed 26 transitions
Trivial Post-agglo rules discarded 26 transitions
Performed 26 trivial Post agglomeration. Transition count delta: 26
Iterating post reduction 1 with 954 rules applied. Total rules applied 1851 place count 1089 transition count 2102
Reduce places removed 26 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 34 rules applied. Total rules applied 1885 place count 1063 transition count 2094
Reduce places removed 4 places and 0 transitions.
Performed 11 Post agglomeration using F-continuation condition.Transition count delta: 11
Iterating post reduction 3 with 15 rules applied. Total rules applied 1900 place count 1059 transition count 2083
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 4 with 11 rules applied. Total rules applied 1911 place count 1048 transition count 2083
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 10 Pre rules applied. Total rules applied 1911 place count 1048 transition count 2073
Deduced a syphon composed of 10 places in 5 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 1931 place count 1038 transition count 2073
Discarding 273 places :
Symmetric choice reduction at 5 with 273 rule applications. Total rules 2204 place count 765 transition count 1800
Iterating global reduction 5 with 273 rules applied. Total rules applied 2477 place count 765 transition count 1800
Performed 113 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 113 Pre rules applied. Total rules applied 2477 place count 765 transition count 1687
Deduced a syphon composed of 113 places in 13 ms
Reduce places removed 113 places and 0 transitions.
Iterating global reduction 5 with 226 rules applied. Total rules applied 2703 place count 652 transition count 1687
Discarding 46 places :
Symmetric choice reduction at 5 with 46 rule applications. Total rules 2749 place count 606 transition count 1245
Iterating global reduction 5 with 46 rules applied. Total rules applied 2795 place count 606 transition count 1245
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 5 with 13 rules applied. Total rules applied 2808 place count 606 transition count 1232
Performed 158 Post agglomeration using F-continuation condition with reduction of 7 identical transitions.
Deduced a syphon composed of 158 places in 1 ms
Reduce places removed 158 places and 0 transitions.
Iterating global reduction 6 with 316 rules applied. Total rules applied 3124 place count 448 transition count 1067
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 6 with 5 rules applied. Total rules applied 3129 place count 448 transition count 1062
Discarding 3 places :
Symmetric choice reduction at 7 with 3 rule applications. Total rules 3132 place count 445 transition count 1032
Iterating global reduction 7 with 3 rules applied. Total rules applied 3135 place count 445 transition count 1032
Performed 59 Post agglomeration using F-continuation condition with reduction of 21 identical transitions.
Deduced a syphon composed of 59 places in 1 ms
Reduce places removed 59 places and 0 transitions.
Iterating global reduction 7 with 118 rules applied. Total rules applied 3253 place count 386 transition count 1548
Drop transitions removed 79 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 80 transitions.
Iterating post reduction 7 with 80 rules applied. Total rules applied 3333 place count 386 transition count 1468
Discarding 18 places :
Symmetric choice reduction at 8 with 18 rule applications. Total rules 3351 place count 368 transition count 1100
Iterating global reduction 8 with 18 rules applied. Total rules applied 3369 place count 368 transition count 1100
Ensure Unique test removed 35 transitions
Reduce isomorphic transitions removed 35 transitions.
Iterating post reduction 8 with 35 rules applied. Total rules applied 3404 place count 368 transition count 1065
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -25
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 9 with 4 rules applied. Total rules applied 3408 place count 366 transition count 1090
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 9 with 4 rules applied. Total rules applied 3412 place count 366 transition count 1086
Drop transitions removed 124 transitions
Redundant transition composition rules discarded 124 transitions
Iterating global reduction 10 with 124 rules applied. Total rules applied 3536 place count 366 transition count 962
Discarding 6 places :
Symmetric choice reduction at 10 with 6 rule applications. Total rules 3542 place count 360 transition count 890
Iterating global reduction 10 with 6 rules applied. Total rules applied 3548 place count 360 transition count 890
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 10 with 6 rules applied. Total rules applied 3554 place count 360 transition count 884
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 3556 place count 359 transition count 897
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 3557 place count 359 transition count 896
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 12 with 13 rules applied. Total rules applied 3570 place count 359 transition count 883
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 12 with 2 rules applied. Total rules applied 3572 place count 358 transition count 896
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 12 with 1 rules applied. Total rules applied 3573 place count 358 transition count 895
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 13 with 13 rules applied. Total rules applied 3586 place count 358 transition count 882
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 13 with 2 rules applied. Total rules applied 3588 place count 357 transition count 895
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 3589 place count 357 transition count 894
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 14 with 1 rules applied. Total rules applied 3590 place count 357 transition count 893
Free-agglomeration rule applied 169 times with reduction of 85 identical transitions.
Iterating global reduction 14 with 169 rules applied. Total rules applied 3759 place count 357 transition count 639
Reduce places removed 169 places and 0 transitions.
Drop transitions removed 215 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 220 transitions.
Graph (complete) has 504 edges and 188 vertex of which 168 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.1 ms
Discarding 20 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Iterating post reduction 14 with 390 rules applied. Total rules applied 4149 place count 168 transition count 418
Drop transitions removed 8 transitions
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 15 with 21 rules applied. Total rules applied 4170 place count 168 transition count 397
Discarding 28 places :
Symmetric choice reduction at 16 with 28 rule applications. Total rules 4198 place count 140 transition count 343
Iterating global reduction 16 with 28 rules applied. Total rules applied 4226 place count 140 transition count 343
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 16 with 6 rules applied. Total rules applied 4232 place count 140 transition count 337
Drop transitions removed 39 transitions
Redundant transition composition rules discarded 39 transitions
Iterating global reduction 17 with 39 rules applied. Total rules applied 4271 place count 140 transition count 298
Reduce places removed 2 places and 0 transitions.
Graph (complete) has 378 edges and 138 vertex of which 136 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.0 ms
Discarding 2 places :
Also discarding 0 output transitions
Iterating post reduction 17 with 3 rules applied. Total rules applied 4274 place count 136 transition count 298
Drop transitions removed 2 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 18 with 3 rules applied. Total rules applied 4277 place count 136 transition count 295
Discarding 7 places :
Symmetric choice reduction at 19 with 7 rule applications. Total rules 4284 place count 129 transition count 283
Iterating global reduction 19 with 7 rules applied. Total rules applied 4291 place count 129 transition count 283
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -15
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 19 with 2 rules applied. Total rules applied 4293 place count 128 transition count 298
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 19 with 6 rules applied. Total rules applied 4299 place count 128 transition count 292
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 20 with 6 rules applied. Total rules applied 4305 place count 128 transition count 286
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 20 with 1 rules applied. Total rules applied 4306 place count 128 transition count 286
Applied a total of 4306 rules in 571 ms. Remains 128 /2340 variables (removed 2212) and now considering 286/3456 (removed 3170) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 571 ms. Remains : 128/2340 places, 286/3456 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 3) seen :2
FORMULA DLCround-PT-06b-ReachabilityCardinality-13 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-06b-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 11:08:31] [INFO ] Flow matrix only has 209 transitions (discarded 77 similar events)
// Phase 1: matrix 209 rows 128 cols
[2023-03-08 11:08:31] [INFO ] Computed 56 place invariants in 8 ms
[2023-03-08 11:08:31] [INFO ] After 40ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 11:08:31] [INFO ] [Nat]Absence check using 56 positive place invariants in 7 ms returned sat
[2023-03-08 11:08:31] [INFO ] After 62ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 11:08:31] [INFO ] State equation strengthened by 64 read => feed constraints.
[2023-03-08 11:08:31] [INFO ] After 30ms SMT Verify possible using 64 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-08 11:08:31] [INFO ] After 63ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 22 ms.
[2023-03-08 11:08:31] [INFO ] After 194ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 18 out of 128 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 128/128 places, 286/286 transitions.
Graph (trivial) has 17 edges and 128 vertex of which 2 / 128 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Graph (complete) has 354 edges and 127 vertex of which 122 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.0 ms
Discarding 5 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Drop transitions removed 2 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 6 place count 122 transition count 276
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 1 Pre rules applied. Total rules applied 6 place count 122 transition count 275
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 1 with 2 rules applied. Total rules applied 8 place count 121 transition count 275
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 1 with 6 rules applied. Total rules applied 14 place count 118 transition count 272
Drop transitions removed 6 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 8 transitions.
Graph (complete) has 330 edges and 118 vertex of which 115 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.1 ms
Discarding 3 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 9 rules applied. Total rules applied 23 place count 115 transition count 264
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 25 place count 115 transition count 262
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 28 place count 112 transition count 257
Iterating global reduction 3 with 3 rules applied. Total rules applied 31 place count 112 transition count 257
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 3 with 4 rules applied. Total rules applied 35 place count 112 transition count 253
Free-agglomeration rule applied 1 times.
Iterating global reduction 3 with 1 rules applied. Total rules applied 36 place count 112 transition count 252
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 37 place count 111 transition count 252
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 4 with 6 rules applied. Total rules applied 43 place count 111 transition count 246
Applied a total of 43 rules in 25 ms. Remains 111 /128 variables (removed 17) and now considering 246/286 (removed 40) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 25 ms. Remains : 111/128 places, 246/286 transitions.
Finished random walk after 88 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=44 )
FORMULA DLCround-PT-06b-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
All properties solved without resorting to model-checking.
Total runtime 6336 ms.
starting LoLA
BK_INPUT DLCround-PT-06b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA DLCround-PT-06b-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-06b-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678273725383

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 68 (type EXCL) for 36 DLCround-PT-06b-ReachabilityCardinality-12
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 51 (type FNDP) for 36 DLCround-PT-06b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 36 DLCround-PT-06b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 67 (type SRCH) for 36 DLCround-PT-06b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-12
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 51 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 58 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 67 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 66 (type EXCL) for 15 DLCround-PT-06b-ReachabilityCardinality-05
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62 (type FNDP) for 9 DLCround-PT-06b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type EQUN) for 9 DLCround-PT-06b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SRCH) for 9 DLCround-PT-06b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 67 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 51 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-58.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 62 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 63 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 74 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 89 (type FNDP) for 30 DLCround-PT-06b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 30 DLCround-PT-06b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SRCH) for 30 DLCround-PT-06b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 66 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-05
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 55 (type EXCL) for 6 DLCround-PT-06b-ReachabilityCardinality-02
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 74 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-03
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 92 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 90 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 100 (type FNDP) for 33 DLCround-PT-06b-ReachabilityCardinality-11sara:
try reading problem file /home/mcc/execution/ReachabilityCardinality-63.sara.lola:
time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type FNDP) for 27 DLCround-PT-06b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type EQUN) for 27 DLCround-PT-06b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 89 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola:
time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 102 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 103 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 122 (type EXCL) for 21 DLCround-PT-06b-ReachabilityCardinality-07
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 99 (type FNDP) for 18 DLCround-PT-06b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type EQUN) for 18 DLCround-PT-06b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 100 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 58 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-12
lola: result : true
lola: LAUNCH task # 72 (type FNDP) for 39 DLCround-PT-06b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-03
lola: result : true
lola: FINISHED task # 72 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-103.sara.
lola: LAUNCH task # 95 (type FNDP) for 3 DLCround-PT-06b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 103 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-09
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-114.sara.

lola: FINISHED task # 114 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-06
lola: result : true
lola: CANCELED task # 99 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 71 (type FNDP) for 12 DLCround-PT-06b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 12 DLCround-PT-06b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 99 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 95 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 98 (type FNDP) for 21 DLCround-PT-06b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-90.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 90 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 71 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 112 (type EQUN) for 21 DLCround-PT-06b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type SRCH) for 21 DLCround-PT-06b-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-04
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-112.sara.
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.

lola: FINISHED task # 112 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-07
lola: result : false
lola: CANCELED task # 98 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 121 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 122 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 141 (type EXCL) for 0 DLCround-PT-06b-ReachabilityCardinality-00
lola: time limit : 897 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 149 (type FNDP) for 45 DLCround-PT-06b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 150 (type EQUN) for 45 DLCround-PT-06b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 152 (type SRCH) for 45 DLCround-PT-06b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 98 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 1127047
lola: tried executions : 3
lola: time used : 2.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 152 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-15
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 149 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 150 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 134 (type FNDP) for 24 DLCround-PT-06b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 136 (type EQUN) for 24 DLCround-PT-06b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type SRCH) for 24 DLCround-PT-06b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 141 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-00
lola: result : true
lola: markings : 75
lola: fired transitions : 99
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 146 (type EXCL) for 42 DLCround-PT-06b-ReachabilityCardinality-14
lola: time limit : 1795 sec
lola: memory limit: 32 pages
lola: FINISHED task # 149 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-15
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-136.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-150.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-06b-ReachabilityCardinality-00: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-06b-ReachabilityCardinality-02: EF true tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-05: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-06: EF true state equation
DLCround-PT-06b-ReachabilityCardinality-07: AG true state equation
DLCround-PT-06b-ReachabilityCardinality-09: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-10: AG false tandem / insertion
DLCround-PT-06b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-12: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-06b-ReachabilityCardinality-15: EF true tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06b-ReachabilityCardinality-08: AG 0 2 3 0 1 0 0 0
DLCround-PT-06b-ReachabilityCardinality-14: AG 0 4 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF FNDP 2/1196 0/5 DLCround-PT-06b-ReachabilityCardinality-08 298884 t fired, 41 attempts, .
136 EF STEQ 2/1196 0/5 DLCround-PT-06b-ReachabilityCardinality-08 sara is running.
138 EF SRCH 2/1795 1/5 DLCround-PT-06b-ReachabilityCardinality-08 159699 m, 31939 m/sec, 202913 t fired, .
146 EF EXCL 2/1795 1/32 DLCround-PT-06b-ReachabilityCardinality-14 9154 m, 1830 m/sec, 18505 t fired, .

Time elapsed: 12 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 150 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-15
lola: result : unknown

lola: FINISHED task # 136 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 134 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 138 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 135 (type FNDP) for 42 DLCround-PT-06b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 143 (type EQUN) for 42 DLCround-PT-06b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 145 (type SRCH) for 42 DLCround-PT-06b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 134 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 559807
lola: tried executions : 83
lola: time used : 3.000000
lola: memory pages used : 0
lola: FINISHED task # 135 (type FNDP) for DLCround-PT-06b-ReachabilityCardinality-14
lola: result : true
lola: fired transitions : 302
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 143 (type EQUN) for DLCround-PT-06b-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 145 (type SRCH) for DLCround-PT-06b-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 146 (type EXCL) for DLCround-PT-06b-ReachabilityCardinality-14 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-06b-ReachabilityCardinality-00: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-01: EF true findpath
DLCround-PT-06b-ReachabilityCardinality-02: EF true tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-03: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-04: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-05: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-06: EF true state equation
DLCround-PT-06b-ReachabilityCardinality-07: AG true state equation
DLCround-PT-06b-ReachabilityCardinality-08: AG true state equation
DLCround-PT-06b-ReachabilityCardinality-09: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-10: AG false tandem / insertion
DLCround-PT-06b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-12: AG false tandem / relaxed
DLCround-PT-06b-ReachabilityCardinality-13: EF true findpath
DLCround-PT-06b-ReachabilityCardinality-14: AG false findpath
DLCround-PT-06b-ReachabilityCardinality-15: EF true tandem / insertion


Time elapsed: 13 secs. Pages in use: 5

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-06b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-06b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600678"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-06b.tgz
mv DLCround-PT-06b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;