Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600658.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-05b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600658
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.6K Feb 25 18:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 18:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 18:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 18:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 18:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 18:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 25 18:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 25 18:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 674K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05b-CTLFireability-00
FORMULA_NAME DLCround-PT-05b-CTLFireability-01
FORMULA_NAME DLCround-PT-05b-CTLFireability-02
FORMULA_NAME DLCround-PT-05b-CTLFireability-03
FORMULA_NAME DLCround-PT-05b-CTLFireability-04
FORMULA_NAME DLCround-PT-05b-CTLFireability-05
FORMULA_NAME DLCround-PT-05b-CTLFireability-06
FORMULA_NAME DLCround-PT-05b-CTLFireability-07
FORMULA_NAME DLCround-PT-05b-CTLFireability-08
FORMULA_NAME DLCround-PT-05b-CTLFireability-09
FORMULA_NAME DLCround-PT-05b-CTLFireability-10
FORMULA_NAME DLCround-PT-05b-CTLFireability-11
FORMULA_NAME DLCround-PT-05b-CTLFireability-12
FORMULA_NAME DLCround-PT-05b-CTLFireability-13
FORMULA_NAME DLCround-PT-05b-CTLFireability-14
FORMULA_NAME DLCround-PT-05b-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678273000920

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-05b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:56:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 10:56:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:56:42] [INFO ] Load time of PNML (sax parser for PT used): 125 ms
[2023-03-08 10:56:42] [INFO ] Transformed 1999 places.
[2023-03-08 10:56:42] [INFO ] Transformed 2887 transitions.
[2023-03-08 10:56:42] [INFO ] Found NUPN structural information;
[2023-03-08 10:56:42] [INFO ] Parsed PT model containing 1999 places and 2887 transitions and 7649 arcs in 216 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 148 out of 1999 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1999/1999 places, 2887/2887 transitions.
Discarding 319 places :
Symmetric choice reduction at 0 with 319 rule applications. Total rules 319 place count 1680 transition count 2568
Iterating global reduction 0 with 319 rules applied. Total rules applied 638 place count 1680 transition count 2568
Discarding 233 places :
Symmetric choice reduction at 0 with 233 rule applications. Total rules 871 place count 1447 transition count 2335
Iterating global reduction 0 with 233 rules applied. Total rules applied 1104 place count 1447 transition count 2335
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 1108 place count 1447 transition count 2331
Discarding 38 places :
Symmetric choice reduction at 1 with 38 rule applications. Total rules 1146 place count 1409 transition count 2267
Iterating global reduction 1 with 38 rules applied. Total rules applied 1184 place count 1409 transition count 2267
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 1209 place count 1384 transition count 2242
Iterating global reduction 1 with 25 rules applied. Total rules applied 1234 place count 1384 transition count 2242
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 1236 place count 1384 transition count 2240
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 1248 place count 1372 transition count 2228
Iterating global reduction 2 with 12 rules applied. Total rules applied 1260 place count 1372 transition count 2228
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 1271 place count 1361 transition count 2217
Iterating global reduction 2 with 11 rules applied. Total rules applied 1282 place count 1361 transition count 2217
Discarding 10 places :
Symmetric choice reduction at 2 with 10 rule applications. Total rules 1292 place count 1351 transition count 2207
Iterating global reduction 2 with 10 rules applied. Total rules applied 1302 place count 1351 transition count 2207
Discarding 7 places :
Symmetric choice reduction at 2 with 7 rule applications. Total rules 1309 place count 1344 transition count 2200
Iterating global reduction 2 with 7 rules applied. Total rules applied 1316 place count 1344 transition count 2200
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 1319 place count 1341 transition count 2197
Iterating global reduction 2 with 3 rules applied. Total rules applied 1322 place count 1341 transition count 2197
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 1325 place count 1338 transition count 2194
Iterating global reduction 2 with 3 rules applied. Total rules applied 1328 place count 1338 transition count 2194
Applied a total of 1328 rules in 942 ms. Remains 1338 /1999 variables (removed 661) and now considering 2194/2887 (removed 693) transitions.
// Phase 1: matrix 2194 rows 1338 cols
[2023-03-08 10:56:43] [INFO ] Computed 88 place invariants in 48 ms
[2023-03-08 10:56:44] [INFO ] Implicit Places using invariants in 616 ms returned []
[2023-03-08 10:56:44] [INFO ] Invariant cache hit.
[2023-03-08 10:56:45] [INFO ] Implicit Places using invariants and state equation in 988 ms returned []
Implicit Place search using SMT with State Equation took 1628 ms to find 0 implicit places.
[2023-03-08 10:56:45] [INFO ] Invariant cache hit.
[2023-03-08 10:56:46] [INFO ] Dead Transitions using invariants and state equation in 882 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1338/1999 places, 2194/2887 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3456 ms. Remains : 1338/1999 places, 2194/2887 transitions.
Support contains 148 out of 1338 places after structural reductions.
[2023-03-08 10:56:46] [INFO ] Flatten gal took : 142 ms
[2023-03-08 10:56:46] [INFO ] Flatten gal took : 101 ms
[2023-03-08 10:56:46] [INFO ] Input system was already deterministic with 2194 transitions.
Support contains 147 out of 1338 places (down from 148) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 482 ms. (steps per millisecond=20 ) properties (out of 86) seen :64
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 22) seen :0
Running SMT prover for 22 properties.
[2023-03-08 10:56:47] [INFO ] Invariant cache hit.
[2023-03-08 10:56:48] [INFO ] [Real]Absence check using 88 positive place invariants in 50 ms returned sat
[2023-03-08 10:56:48] [INFO ] After 956ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:22
[2023-03-08 10:56:49] [INFO ] [Nat]Absence check using 88 positive place invariants in 41 ms returned sat
[2023-03-08 10:56:51] [INFO ] After 1881ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :22
[2023-03-08 10:56:53] [INFO ] After 4268ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :22
Attempting to minimize the solution found.
Minimization took 1307 ms.
[2023-03-08 10:56:55] [INFO ] After 6753ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :22
Fused 22 Parikh solutions to 21 different solutions.
Parikh walk visited 16 properties in 963 ms.
Support contains 9 out of 1338 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1223 edges and 1338 vertex of which 353 / 1338 are part of one of the 27 SCC in 10 ms
Free SCC test removed 326 places
Drop transitions removed 369 transitions
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 378 transitions.
Drop transitions removed 256 transitions
Trivial Post-agglo rules discarded 256 transitions
Performed 256 trivial Post agglomeration. Transition count delta: 256
Iterating post reduction 0 with 256 rules applied. Total rules applied 257 place count 1012 transition count 1560
Reduce places removed 256 places and 0 transitions.
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Drop transitions removed 21 transitions
Trivial Post-agglo rules discarded 21 transitions
Performed 21 trivial Post agglomeration. Transition count delta: 21
Iterating post reduction 1 with 290 rules applied. Total rules applied 547 place count 756 transition count 1526
Reduce places removed 21 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 23 rules applied. Total rules applied 570 place count 735 transition count 1524
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 572 place count 734 transition count 1523
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 573 place count 733 transition count 1523
Performed 84 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 84 Pre rules applied. Total rules applied 573 place count 733 transition count 1439
Deduced a syphon composed of 84 places in 3 ms
Reduce places removed 84 places and 0 transitions.
Iterating global reduction 5 with 168 rules applied. Total rules applied 741 place count 649 transition count 1439
Discarding 64 places :
Symmetric choice reduction at 5 with 64 rule applications. Total rules 805 place count 585 transition count 1216
Iterating global reduction 5 with 64 rules applied. Total rules applied 869 place count 585 transition count 1216
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 872 place count 585 transition count 1213
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 20 Pre rules applied. Total rules applied 872 place count 585 transition count 1193
Deduced a syphon composed of 20 places in 5 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 6 with 40 rules applied. Total rules applied 912 place count 565 transition count 1193
Discarding 4 places :
Symmetric choice reduction at 6 with 4 rule applications. Total rules 916 place count 561 transition count 1160
Iterating global reduction 6 with 4 rules applied. Total rules applied 920 place count 561 transition count 1160
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 923 place count 561 transition count 1157
Performed 202 Post agglomeration using F-continuation condition with reduction of 5 identical transitions.
Deduced a syphon composed of 202 places in 0 ms
Reduce places removed 202 places and 0 transitions.
Iterating global reduction 7 with 404 rules applied. Total rules applied 1327 place count 359 transition count 950
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 7 with 6 rules applied. Total rules applied 1333 place count 359 transition count 944
Discarding 18 places :
Symmetric choice reduction at 8 with 18 rule applications. Total rules 1351 place count 341 transition count 794
Iterating global reduction 8 with 18 rules applied. Total rules applied 1369 place count 341 transition count 794
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 8 with 13 rules applied. Total rules applied 1382 place count 341 transition count 781
Performed 33 Post agglomeration using F-continuation condition with reduction of 24 identical transitions.
Deduced a syphon composed of 33 places in 1 ms
Reduce places removed 33 places and 0 transitions.
Iterating global reduction 9 with 66 rules applied. Total rules applied 1448 place count 308 transition count 1009
Drop transitions removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 9 with 12 rules applied. Total rules applied 1460 place count 308 transition count 997
Discarding 14 places :
Symmetric choice reduction at 10 with 14 rule applications. Total rules 1474 place count 294 transition count 765
Iterating global reduction 10 with 14 rules applied. Total rules applied 1488 place count 294 transition count 765
Ensure Unique test removed 35 transitions
Reduce isomorphic transitions removed 35 transitions.
Iterating post reduction 10 with 35 rules applied. Total rules applied 1523 place count 294 transition count 730
Drop transitions removed 76 transitions
Redundant transition composition rules discarded 76 transitions
Iterating global reduction 11 with 76 rules applied. Total rules applied 1599 place count 294 transition count 654
Discarding 6 places :
Symmetric choice reduction at 11 with 6 rule applications. Total rules 1605 place count 288 transition count 599
Iterating global reduction 11 with 6 rules applied. Total rules applied 1611 place count 288 transition count 599
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 11 with 6 rules applied. Total rules applied 1617 place count 288 transition count 593
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: -34
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 12 with 8 rules applied. Total rules applied 1625 place count 284 transition count 627
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 12 with 5 rules applied. Total rules applied 1630 place count 284 transition count 622
Renaming transitions due to excessive name length > 1024 char.
Drop transitions removed 21 transitions
Redundant transition composition rules discarded 21 transitions
Iterating global reduction 13 with 21 rules applied. Total rules applied 1651 place count 284 transition count 601
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -26
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 13 with 6 rules applied. Total rules applied 1657 place count 281 transition count 627
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 13 with 6 rules applied. Total rules applied 1663 place count 281 transition count 621
Drop transitions removed 17 transitions
Redundant transition composition rules discarded 17 transitions
Iterating global reduction 14 with 17 rules applied. Total rules applied 1680 place count 281 transition count 604
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -29
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 14 with 6 rules applied. Total rules applied 1686 place count 278 transition count 633
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 14 with 4 rules applied. Total rules applied 1690 place count 278 transition count 629
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 15 with 19 rules applied. Total rules applied 1709 place count 278 transition count 610
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 15 with 6 rules applied. Total rules applied 1715 place count 275 transition count 633
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 15 with 5 rules applied. Total rules applied 1720 place count 275 transition count 628
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 16 with 18 rules applied. Total rules applied 1738 place count 275 transition count 610
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -24
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 16 with 6 rules applied. Total rules applied 1744 place count 272 transition count 634
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 16 with 4 rules applied. Total rules applied 1748 place count 272 transition count 630
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 17 with 19 rules applied. Total rules applied 1767 place count 272 transition count 611
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -24
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 17 with 6 rules applied. Total rules applied 1773 place count 269 transition count 635
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 17 with 5 rules applied. Total rules applied 1778 place count 269 transition count 630
Drop transitions removed 16 transitions
Redundant transition composition rules discarded 16 transitions
Iterating global reduction 18 with 16 rules applied. Total rules applied 1794 place count 269 transition count 614
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -19
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 18 with 4 rules applied. Total rules applied 1798 place count 267 transition count 633
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 18 with 3 rules applied. Total rules applied 1801 place count 267 transition count 630
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 19 with 15 rules applied. Total rules applied 1816 place count 267 transition count 615
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -20
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 19 with 4 rules applied. Total rules applied 1820 place count 265 transition count 635
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 19 with 3 rules applied. Total rules applied 1823 place count 265 transition count 632
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 20 with 15 rules applied. Total rules applied 1838 place count 265 transition count 617
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -19
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 20 with 4 rules applied. Total rules applied 1842 place count 263 transition count 636
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 20 with 3 rules applied. Total rules applied 1845 place count 263 transition count 633
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 21 with 15 rules applied. Total rules applied 1860 place count 263 transition count 618
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -18
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 21 with 4 rules applied. Total rules applied 1864 place count 261 transition count 636
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 21 with 3 rules applied. Total rules applied 1867 place count 261 transition count 633
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 22 with 11 rules applied. Total rules applied 1878 place count 261 transition count 622
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 22 with 2 rules applied. Total rules applied 1880 place count 260 transition count 633
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 22 with 1 rules applied. Total rules applied 1881 place count 260 transition count 632
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 23 with 10 rules applied. Total rules applied 1891 place count 260 transition count 622
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 23 with 2 rules applied. Total rules applied 1893 place count 259 transition count 633
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 23 with 2 rules applied. Total rules applied 1895 place count 259 transition count 631
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 24 with 9 rules applied. Total rules applied 1904 place count 259 transition count 622
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -12
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 24 with 2 rules applied. Total rules applied 1906 place count 258 transition count 634
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 24 with 1 rules applied. Total rules applied 1907 place count 258 transition count 633
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 25 with 10 rules applied. Total rules applied 1917 place count 258 transition count 623
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 25 with 2 rules applied. Total rules applied 1919 place count 257 transition count 634
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 25 with 2 rules applied. Total rules applied 1921 place count 257 transition count 632
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 26 with 9 rules applied. Total rules applied 1930 place count 257 transition count 623
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 26 with 2 rules applied. Total rules applied 1932 place count 256 transition count 634
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 26 with 1 rules applied. Total rules applied 1933 place count 256 transition count 633
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 27 with 10 rules applied. Total rules applied 1943 place count 256 transition count 623
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 27 with 2 rules applied. Total rules applied 1945 place count 255 transition count 634
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 27 with 2 rules applied. Total rules applied 1947 place count 255 transition count 632
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 28 with 9 rules applied. Total rules applied 1956 place count 255 transition count 623
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 28 with 2 rules applied. Total rules applied 1958 place count 254 transition count 634
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 28 with 1 rules applied. Total rules applied 1959 place count 254 transition count 633
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 29 with 2 rules applied. Total rules applied 1961 place count 254 transition count 631
Free-agglomeration rule applied 106 times with reduction of 46 identical transitions.
Iterating global reduction 29 with 106 rules applied. Total rules applied 2067 place count 254 transition count 479
Reduce places removed 106 places and 0 transitions.
Drop transitions removed 176 transitions
Reduce isomorphic transitions removed 176 transitions.
Graph (complete) has 408 edges and 148 vertex of which 134 are kept as prefixes of interest. Removing 14 places using SCC suffix rule.1 ms
Discarding 14 places :
Also discarding 0 output transitions
Iterating post reduction 29 with 283 rules applied. Total rules applied 2350 place count 134 transition count 303
Discarding 10 places :
Symmetric choice reduction at 30 with 10 rule applications. Total rules 2360 place count 124 transition count 288
Iterating global reduction 30 with 10 rules applied. Total rules applied 2370 place count 124 transition count 288
Drop transitions removed 32 transitions
Redundant transition composition rules discarded 32 transitions
Iterating global reduction 30 with 32 rules applied. Total rules applied 2402 place count 124 transition count 256
Applied a total of 2402 rules in 795 ms. Remains 124 /1338 variables (removed 1214) and now considering 256/2194 (removed 1938) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 795 ms. Remains : 124/1338 places, 256/2194 transitions.
Finished random walk after 3356 steps, including 1 resets, run visited all 6 properties in 30 ms. (steps per millisecond=111 )
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 66 ms
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 63 ms
[2023-03-08 10:56:57] [INFO ] Input system was already deterministic with 2194 transitions.
Computed a total of 197 stabilizing places and 197 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1236 edges and 1338 vertex of which 344 / 1338 are part of one of the 27 SCC in 1 ms
Free SCC test removed 317 places
Ensure Unique test removed 339 transitions
Reduce isomorphic transitions removed 339 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 266 transitions
Trivial Post-agglo rules discarded 266 transitions
Performed 266 trivial Post agglomeration. Transition count delta: 266
Iterating post reduction 0 with 266 rules applied. Total rules applied 267 place count 1020 transition count 1588
Reduce places removed 266 places and 0 transitions.
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Drop transitions removed 21 transitions
Trivial Post-agglo rules discarded 21 transitions
Performed 21 trivial Post agglomeration. Transition count delta: 21
Iterating post reduction 1 with 302 rules applied. Total rules applied 569 place count 754 transition count 1552
Reduce places removed 21 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 23 rules applied. Total rules applied 592 place count 733 transition count 1550
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 594 place count 732 transition count 1549
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 595 place count 731 transition count 1549
Performed 83 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 83 Pre rules applied. Total rules applied 595 place count 731 transition count 1466
Deduced a syphon composed of 83 places in 3 ms
Reduce places removed 83 places and 0 transitions.
Iterating global reduction 5 with 166 rules applied. Total rules applied 761 place count 648 transition count 1466
Discarding 67 places :
Symmetric choice reduction at 5 with 67 rule applications. Total rules 828 place count 581 transition count 1236
Iterating global reduction 5 with 67 rules applied. Total rules applied 895 place count 581 transition count 1236
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 898 place count 581 transition count 1233
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 19 Pre rules applied. Total rules applied 898 place count 581 transition count 1214
Deduced a syphon composed of 19 places in 3 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 6 with 38 rules applied. Total rules applied 936 place count 562 transition count 1214
Discarding 4 places :
Symmetric choice reduction at 6 with 4 rule applications. Total rules 940 place count 558 transition count 1181
Iterating global reduction 6 with 4 rules applied. Total rules applied 944 place count 558 transition count 1181
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 947 place count 558 transition count 1178
Performed 184 Post agglomeration using F-continuation condition.Transition count delta: 184
Deduced a syphon composed of 184 places in 1 ms
Reduce places removed 184 places and 0 transitions.
Iterating global reduction 7 with 368 rules applied. Total rules applied 1315 place count 374 transition count 994
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 1316 place count 374 transition count 993
Discarding 21 places :
Symmetric choice reduction at 8 with 21 rule applications. Total rules 1337 place count 353 transition count 816
Iterating global reduction 8 with 21 rules applied. Total rules applied 1358 place count 353 transition count 816
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 8 with 14 rules applied. Total rules applied 1372 place count 353 transition count 802
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 1374 place count 352 transition count 801
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 9 with 13 rules applied. Total rules applied 1387 place count 352 transition count 788
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 9 with 6 rules applied. Total rules applied 1393 place count 352 transition count 782
Reduce places removed 6 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 10 with 7 rules applied. Total rules applied 1400 place count 346 transition count 781
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 11 with 1 rules applied. Total rules applied 1401 place count 345 transition count 781
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 12 with 2 rules applied. Total rules applied 1403 place count 343 transition count 779
Applied a total of 1403 rules in 166 ms. Remains 343 /1338 variables (removed 995) and now considering 779/2194 (removed 1415) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 166 ms. Remains : 343/1338 places, 779/2194 transitions.
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 27 ms
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:56:57] [INFO ] Input system was already deterministic with 779 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 53 places :
Symmetric choice reduction at 0 with 53 rule applications. Total rules 53 place count 1285 transition count 2132
Iterating global reduction 0 with 53 rules applied. Total rules applied 106 place count 1285 transition count 2132
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 138 place count 1253 transition count 2100
Iterating global reduction 0 with 32 rules applied. Total rules applied 170 place count 1253 transition count 2100
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 173 place count 1253 transition count 2097
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 182 place count 1244 transition count 2079
Iterating global reduction 1 with 9 rules applied. Total rules applied 191 place count 1244 transition count 2079
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 197 place count 1238 transition count 2073
Iterating global reduction 1 with 6 rules applied. Total rules applied 203 place count 1238 transition count 2073
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 204 place count 1238 transition count 2072
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 208 place count 1234 transition count 2068
Iterating global reduction 2 with 4 rules applied. Total rules applied 212 place count 1234 transition count 2068
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 216 place count 1230 transition count 2064
Iterating global reduction 2 with 4 rules applied. Total rules applied 220 place count 1230 transition count 2064
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 223 place count 1227 transition count 2061
Iterating global reduction 2 with 3 rules applied. Total rules applied 226 place count 1227 transition count 2061
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 228 place count 1225 transition count 2059
Iterating global reduction 2 with 2 rules applied. Total rules applied 230 place count 1225 transition count 2059
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 231 place count 1224 transition count 2058
Iterating global reduction 2 with 1 rules applied. Total rules applied 232 place count 1224 transition count 2058
Applied a total of 232 rules in 237 ms. Remains 1224 /1338 variables (removed 114) and now considering 2058/2194 (removed 136) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 238 ms. Remains : 1224/1338 places, 2058/2194 transitions.
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 50 ms
[2023-03-08 10:56:57] [INFO ] Flatten gal took : 49 ms
[2023-03-08 10:56:58] [INFO ] Input system was already deterministic with 2058 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 47 places :
Symmetric choice reduction at 0 with 47 rule applications. Total rules 47 place count 1291 transition count 2130
Iterating global reduction 0 with 47 rules applied. Total rules applied 94 place count 1291 transition count 2130
Discarding 25 places :
Symmetric choice reduction at 0 with 25 rule applications. Total rules 119 place count 1266 transition count 2105
Iterating global reduction 0 with 25 rules applied. Total rules applied 144 place count 1266 transition count 2105
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 145 place count 1266 transition count 2104
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 154 place count 1257 transition count 2086
Iterating global reduction 1 with 9 rules applied. Total rules applied 163 place count 1257 transition count 2086
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 169 place count 1251 transition count 2080
Iterating global reduction 1 with 6 rules applied. Total rules applied 175 place count 1251 transition count 2080
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 176 place count 1251 transition count 2079
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 180 place count 1247 transition count 2075
Iterating global reduction 2 with 4 rules applied. Total rules applied 184 place count 1247 transition count 2075
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 188 place count 1243 transition count 2071
Iterating global reduction 2 with 4 rules applied. Total rules applied 192 place count 1243 transition count 2071
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 194 place count 1241 transition count 2069
Iterating global reduction 2 with 2 rules applied. Total rules applied 196 place count 1241 transition count 2069
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 197 place count 1240 transition count 2068
Iterating global reduction 2 with 1 rules applied. Total rules applied 198 place count 1240 transition count 2068
Applied a total of 198 rules in 219 ms. Remains 1240 /1338 variables (removed 98) and now considering 2068/2194 (removed 126) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 220 ms. Remains : 1240/1338 places, 2068/2194 transitions.
[2023-03-08 10:56:58] [INFO ] Flatten gal took : 50 ms
[2023-03-08 10:56:58] [INFO ] Flatten gal took : 52 ms
[2023-03-08 10:56:58] [INFO ] Input system was already deterministic with 2068 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1225 edges and 1338 vertex of which 321 / 1338 are part of one of the 29 SCC in 2 ms
Free SCC test removed 292 places
Ensure Unique test removed 312 transitions
Reduce isomorphic transitions removed 312 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 272 transitions
Trivial Post-agglo rules discarded 272 transitions
Performed 272 trivial Post agglomeration. Transition count delta: 272
Iterating post reduction 0 with 272 rules applied. Total rules applied 273 place count 1045 transition count 1609
Reduce places removed 272 places and 0 transitions.
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 1 with 309 rules applied. Total rules applied 582 place count 773 transition count 1572
Reduce places removed 22 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 24 rules applied. Total rules applied 606 place count 751 transition count 1570
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 3 with 4 rules applied. Total rules applied 610 place count 750 transition count 1567
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 613 place count 747 transition count 1567
Performed 84 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 84 Pre rules applied. Total rules applied 613 place count 747 transition count 1483
Deduced a syphon composed of 84 places in 3 ms
Reduce places removed 84 places and 0 transitions.
Iterating global reduction 5 with 168 rules applied. Total rules applied 781 place count 663 transition count 1483
Discarding 61 places :
Symmetric choice reduction at 5 with 61 rule applications. Total rules 842 place count 602 transition count 1279
Iterating global reduction 5 with 61 rules applied. Total rules applied 903 place count 602 transition count 1279
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 906 place count 602 transition count 1276
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 19 Pre rules applied. Total rules applied 906 place count 602 transition count 1257
Deduced a syphon composed of 19 places in 2 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 6 with 38 rules applied. Total rules applied 944 place count 583 transition count 1257
Discarding 3 places :
Symmetric choice reduction at 6 with 3 rule applications. Total rules 947 place count 580 transition count 1233
Iterating global reduction 6 with 3 rules applied. Total rules applied 950 place count 580 transition count 1233
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 953 place count 580 transition count 1230
Performed 192 Post agglomeration using F-continuation condition.Transition count delta: 192
Deduced a syphon composed of 192 places in 0 ms
Reduce places removed 192 places and 0 transitions.
Iterating global reduction 7 with 384 rules applied. Total rules applied 1337 place count 388 transition count 1038
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 1339 place count 388 transition count 1036
Discarding 18 places :
Symmetric choice reduction at 8 with 18 rule applications. Total rules 1357 place count 370 transition count 886
Iterating global reduction 8 with 18 rules applied. Total rules applied 1375 place count 370 transition count 886
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 8 with 10 rules applied. Total rules applied 1385 place count 370 transition count 876
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 9 with 4 rules applied. Total rules applied 1389 place count 368 transition count 874
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 9 with 10 rules applied. Total rules applied 1399 place count 368 transition count 864
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 9 with 5 rules applied. Total rules applied 1404 place count 368 transition count 859
Reduce places removed 5 places and 0 transitions.
Iterating post reduction 10 with 5 rules applied. Total rules applied 1409 place count 363 transition count 859
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 11 with 1 rules applied. Total rules applied 1410 place count 363 transition count 859
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 1412 place count 361 transition count 857
Applied a total of 1412 rules in 149 ms. Remains 361 /1338 variables (removed 977) and now considering 857/2194 (removed 1337) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 149 ms. Remains : 361/1338 places, 857/2194 transitions.
[2023-03-08 10:56:58] [INFO ] Flatten gal took : 20 ms
[2023-03-08 10:56:58] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:56:58] [INFO ] Input system was already deterministic with 857 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 56 places :
Symmetric choice reduction at 0 with 56 rule applications. Total rules 56 place count 1282 transition count 2121
Iterating global reduction 0 with 56 rules applied. Total rules applied 112 place count 1282 transition count 2121
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 145 place count 1249 transition count 2088
Iterating global reduction 0 with 33 rules applied. Total rules applied 178 place count 1249 transition count 2088
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 181 place count 1249 transition count 2085
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 191 place count 1239 transition count 2066
Iterating global reduction 1 with 10 rules applied. Total rules applied 201 place count 1239 transition count 2066
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 208 place count 1232 transition count 2059
Iterating global reduction 1 with 7 rules applied. Total rules applied 215 place count 1232 transition count 2059
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 216 place count 1232 transition count 2058
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 221 place count 1227 transition count 2053
Iterating global reduction 2 with 5 rules applied. Total rules applied 226 place count 1227 transition count 2053
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 231 place count 1222 transition count 2048
Iterating global reduction 2 with 5 rules applied. Total rules applied 236 place count 1222 transition count 2048
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 239 place count 1219 transition count 2045
Iterating global reduction 2 with 3 rules applied. Total rules applied 242 place count 1219 transition count 2045
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 244 place count 1217 transition count 2043
Iterating global reduction 2 with 2 rules applied. Total rules applied 246 place count 1217 transition count 2043
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 247 place count 1216 transition count 2042
Iterating global reduction 2 with 1 rules applied. Total rules applied 248 place count 1216 transition count 2042
Applied a total of 248 rules in 224 ms. Remains 1216 /1338 variables (removed 122) and now considering 2042/2194 (removed 152) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 224 ms. Remains : 1216/1338 places, 2042/2194 transitions.
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 41 ms
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 43 ms
[2023-03-08 10:56:59] [INFO ] Input system was already deterministic with 2042 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 57 place count 1281 transition count 2120
Iterating global reduction 0 with 57 rules applied. Total rules applied 114 place count 1281 transition count 2120
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 148 place count 1247 transition count 2086
Iterating global reduction 0 with 34 rules applied. Total rules applied 182 place count 1247 transition count 2086
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 185 place count 1247 transition count 2083
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 195 place count 1237 transition count 2064
Iterating global reduction 1 with 10 rules applied. Total rules applied 205 place count 1237 transition count 2064
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 212 place count 1230 transition count 2057
Iterating global reduction 1 with 7 rules applied. Total rules applied 219 place count 1230 transition count 2057
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 220 place count 1230 transition count 2056
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 225 place count 1225 transition count 2051
Iterating global reduction 2 with 5 rules applied. Total rules applied 230 place count 1225 transition count 2051
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 235 place count 1220 transition count 2046
Iterating global reduction 2 with 5 rules applied. Total rules applied 240 place count 1220 transition count 2046
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 243 place count 1217 transition count 2043
Iterating global reduction 2 with 3 rules applied. Total rules applied 246 place count 1217 transition count 2043
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 248 place count 1215 transition count 2041
Iterating global reduction 2 with 2 rules applied. Total rules applied 250 place count 1215 transition count 2041
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 251 place count 1214 transition count 2040
Iterating global reduction 2 with 1 rules applied. Total rules applied 252 place count 1214 transition count 2040
Applied a total of 252 rules in 226 ms. Remains 1214 /1338 variables (removed 124) and now considering 2040/2194 (removed 154) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 226 ms. Remains : 1214/1338 places, 2040/2194 transitions.
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 49 ms
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 39 ms
[2023-03-08 10:56:59] [INFO ] Input system was already deterministic with 2040 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1237 edges and 1338 vertex of which 359 / 1338 are part of one of the 28 SCC in 1 ms
Free SCC test removed 331 places
Ensure Unique test removed 356 transitions
Reduce isomorphic transitions removed 356 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 262 transitions
Trivial Post-agglo rules discarded 262 transitions
Performed 262 trivial Post agglomeration. Transition count delta: 262
Iterating post reduction 0 with 262 rules applied. Total rules applied 263 place count 1006 transition count 1575
Reduce places removed 262 places and 0 transitions.
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition count delta: 22
Iterating post reduction 1 with 300 rules applied. Total rules applied 563 place count 744 transition count 1537
Reduce places removed 22 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 24 rules applied. Total rules applied 587 place count 722 transition count 1535
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 588 place count 721 transition count 1535
Performed 80 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 80 Pre rules applied. Total rules applied 588 place count 721 transition count 1455
Deduced a syphon composed of 80 places in 3 ms
Reduce places removed 80 places and 0 transitions.
Iterating global reduction 4 with 160 rules applied. Total rules applied 748 place count 641 transition count 1455
Discarding 69 places :
Symmetric choice reduction at 4 with 69 rule applications. Total rules 817 place count 572 transition count 1219
Iterating global reduction 4 with 69 rules applied. Total rules applied 886 place count 572 transition count 1219
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 889 place count 572 transition count 1216
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 19 Pre rules applied. Total rules applied 889 place count 572 transition count 1197
Deduced a syphon composed of 19 places in 3 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 5 with 38 rules applied. Total rules applied 927 place count 553 transition count 1197
Discarding 4 places :
Symmetric choice reduction at 5 with 4 rule applications. Total rules 931 place count 549 transition count 1164
Iterating global reduction 5 with 4 rules applied. Total rules applied 935 place count 549 transition count 1164
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 938 place count 549 transition count 1161
Performed 183 Post agglomeration using F-continuation condition.Transition count delta: 183
Deduced a syphon composed of 183 places in 0 ms
Reduce places removed 183 places and 0 transitions.
Iterating global reduction 6 with 366 rules applied. Total rules applied 1304 place count 366 transition count 978
Discarding 21 places :
Symmetric choice reduction at 6 with 21 rule applications. Total rules 1325 place count 345 transition count 801
Iterating global reduction 6 with 21 rules applied. Total rules applied 1346 place count 345 transition count 801
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 6 with 14 rules applied. Total rules applied 1360 place count 345 transition count 787
Drop transitions removed 12 transitions
Redundant transition composition rules discarded 12 transitions
Iterating global reduction 7 with 12 rules applied. Total rules applied 1372 place count 345 transition count 775
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 7 with 6 rules applied. Total rules applied 1378 place count 345 transition count 769
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 8 with 6 rules applied. Total rules applied 1384 place count 339 transition count 769
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 1386 place count 337 transition count 767
Applied a total of 1386 rules in 121 ms. Remains 337 /1338 variables (removed 1001) and now considering 767/2194 (removed 1427) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 122 ms. Remains : 337/1338 places, 767/2194 transitions.
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 15 ms
[2023-03-08 10:56:59] [INFO ] Flatten gal took : 16 ms
[2023-03-08 10:56:59] [INFO ] Input system was already deterministic with 767 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 59 places :
Symmetric choice reduction at 0 with 59 rule applications. Total rules 59 place count 1279 transition count 2118
Iterating global reduction 0 with 59 rules applied. Total rules applied 118 place count 1279 transition count 2118
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 152 place count 1245 transition count 2084
Iterating global reduction 0 with 34 rules applied. Total rules applied 186 place count 1245 transition count 2084
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 189 place count 1245 transition count 2081
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 199 place count 1235 transition count 2062
Iterating global reduction 1 with 10 rules applied. Total rules applied 209 place count 1235 transition count 2062
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 216 place count 1228 transition count 2055
Iterating global reduction 1 with 7 rules applied. Total rules applied 223 place count 1228 transition count 2055
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 224 place count 1228 transition count 2054
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 229 place count 1223 transition count 2049
Iterating global reduction 2 with 5 rules applied. Total rules applied 234 place count 1223 transition count 2049
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 239 place count 1218 transition count 2044
Iterating global reduction 2 with 5 rules applied. Total rules applied 244 place count 1218 transition count 2044
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 247 place count 1215 transition count 2041
Iterating global reduction 2 with 3 rules applied. Total rules applied 250 place count 1215 transition count 2041
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 252 place count 1213 transition count 2039
Iterating global reduction 2 with 2 rules applied. Total rules applied 254 place count 1213 transition count 2039
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 255 place count 1212 transition count 2038
Iterating global reduction 2 with 1 rules applied. Total rules applied 256 place count 1212 transition count 2038
Applied a total of 256 rules in 225 ms. Remains 1212 /1338 variables (removed 126) and now considering 2038/2194 (removed 156) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 226 ms. Remains : 1212/1338 places, 2038/2194 transitions.
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 38 ms
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 40 ms
[2023-03-08 10:57:00] [INFO ] Input system was already deterministic with 2038 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1224 edges and 1338 vertex of which 353 / 1338 are part of one of the 28 SCC in 1 ms
Free SCC test removed 325 places
Ensure Unique test removed 349 transitions
Reduce isomorphic transitions removed 349 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 261 transitions
Trivial Post-agglo rules discarded 261 transitions
Performed 261 trivial Post agglomeration. Transition count delta: 261
Iterating post reduction 0 with 261 rules applied. Total rules applied 262 place count 1012 transition count 1583
Reduce places removed 261 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Drop transitions removed 19 transitions
Trivial Post-agglo rules discarded 19 transitions
Performed 19 trivial Post agglomeration. Transition count delta: 19
Iterating post reduction 1 with 294 rules applied. Total rules applied 556 place count 751 transition count 1550
Reduce places removed 19 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 21 rules applied. Total rules applied 577 place count 732 transition count 1548
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 4 rules applied. Total rules applied 581 place count 730 transition count 1546
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 582 place count 729 transition count 1546
Performed 81 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 81 Pre rules applied. Total rules applied 582 place count 729 transition count 1465
Deduced a syphon composed of 81 places in 3 ms
Reduce places removed 81 places and 0 transitions.
Iterating global reduction 5 with 162 rules applied. Total rules applied 744 place count 648 transition count 1465
Discarding 64 places :
Symmetric choice reduction at 5 with 64 rule applications. Total rules 808 place count 584 transition count 1242
Iterating global reduction 5 with 64 rules applied. Total rules applied 872 place count 584 transition count 1242
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 5 with 3 rules applied. Total rules applied 875 place count 584 transition count 1239
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 17 Pre rules applied. Total rules applied 875 place count 584 transition count 1222
Deduced a syphon composed of 17 places in 3 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 909 place count 567 transition count 1222
Discarding 4 places :
Symmetric choice reduction at 6 with 4 rule applications. Total rules 913 place count 563 transition count 1189
Iterating global reduction 6 with 4 rules applied. Total rules applied 917 place count 563 transition count 1189
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 920 place count 563 transition count 1186
Performed 182 Post agglomeration using F-continuation condition.Transition count delta: 182
Deduced a syphon composed of 182 places in 0 ms
Reduce places removed 182 places and 0 transitions.
Iterating global reduction 7 with 364 rules applied. Total rules applied 1284 place count 381 transition count 1004
Discarding 19 places :
Symmetric choice reduction at 7 with 19 rule applications. Total rules 1303 place count 362 transition count 845
Iterating global reduction 7 with 19 rules applied. Total rules applied 1322 place count 362 transition count 845
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 7 with 12 rules applied. Total rules applied 1334 place count 362 transition count 833
Drop transitions removed 13 transitions
Redundant transition composition rules discarded 13 transitions
Iterating global reduction 8 with 13 rules applied. Total rules applied 1347 place count 362 transition count 820
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 8 with 6 rules applied. Total rules applied 1353 place count 362 transition count 814
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 9 with 6 rules applied. Total rules applied 1359 place count 356 transition count 814
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 1359 place count 356 transition count 813
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1361 place count 355 transition count 813
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1363 place count 353 transition count 811
Applied a total of 1363 rules in 122 ms. Remains 353 /1338 variables (removed 985) and now considering 811/2194 (removed 1383) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 123 ms. Remains : 353/1338 places, 811/2194 transitions.
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 17 ms
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 19 ms
[2023-03-08 10:57:00] [INFO ] Input system was already deterministic with 811 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 56 places :
Symmetric choice reduction at 0 with 56 rule applications. Total rules 56 place count 1282 transition count 2122
Iterating global reduction 0 with 56 rules applied. Total rules applied 112 place count 1282 transition count 2122
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 146 place count 1248 transition count 2088
Iterating global reduction 0 with 34 rules applied. Total rules applied 180 place count 1248 transition count 2088
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 182 place count 1248 transition count 2086
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 191 place count 1239 transition count 2076
Iterating global reduction 1 with 9 rules applied. Total rules applied 200 place count 1239 transition count 2076
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 207 place count 1232 transition count 2069
Iterating global reduction 1 with 7 rules applied. Total rules applied 214 place count 1232 transition count 2069
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 215 place count 1232 transition count 2068
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 220 place count 1227 transition count 2063
Iterating global reduction 2 with 5 rules applied. Total rules applied 225 place count 1227 transition count 2063
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 230 place count 1222 transition count 2058
Iterating global reduction 2 with 5 rules applied. Total rules applied 235 place count 1222 transition count 2058
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 238 place count 1219 transition count 2055
Iterating global reduction 2 with 3 rules applied. Total rules applied 241 place count 1219 transition count 2055
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 243 place count 1217 transition count 2053
Iterating global reduction 2 with 2 rules applied. Total rules applied 245 place count 1217 transition count 2053
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 246 place count 1216 transition count 2052
Iterating global reduction 2 with 1 rules applied. Total rules applied 247 place count 1216 transition count 2052
Applied a total of 247 rules in 227 ms. Remains 1216 /1338 variables (removed 122) and now considering 2052/2194 (removed 142) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 228 ms. Remains : 1216/1338 places, 2052/2194 transitions.
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 35 ms
[2023-03-08 10:57:00] [INFO ] Flatten gal took : 37 ms
[2023-03-08 10:57:00] [INFO ] Input system was already deterministic with 2052 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 54 places :
Symmetric choice reduction at 0 with 54 rule applications. Total rules 54 place count 1284 transition count 2123
Iterating global reduction 0 with 54 rules applied. Total rules applied 108 place count 1284 transition count 2123
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 139 place count 1253 transition count 2092
Iterating global reduction 0 with 31 rules applied. Total rules applied 170 place count 1253 transition count 2092
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 173 place count 1253 transition count 2089
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 182 place count 1244 transition count 2071
Iterating global reduction 1 with 9 rules applied. Total rules applied 191 place count 1244 transition count 2071
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 197 place count 1238 transition count 2065
Iterating global reduction 1 with 6 rules applied. Total rules applied 203 place count 1238 transition count 2065
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 204 place count 1238 transition count 2064
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 208 place count 1234 transition count 2060
Iterating global reduction 2 with 4 rules applied. Total rules applied 212 place count 1234 transition count 2060
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 216 place count 1230 transition count 2056
Iterating global reduction 2 with 4 rules applied. Total rules applied 220 place count 1230 transition count 2056
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 222 place count 1228 transition count 2054
Iterating global reduction 2 with 2 rules applied. Total rules applied 224 place count 1228 transition count 2054
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 225 place count 1227 transition count 2053
Iterating global reduction 2 with 1 rules applied. Total rules applied 226 place count 1227 transition count 2053
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 227 place count 1226 transition count 2052
Iterating global reduction 2 with 1 rules applied. Total rules applied 228 place count 1226 transition count 2052
Applied a total of 228 rules in 232 ms. Remains 1226 /1338 variables (removed 112) and now considering 2052/2194 (removed 142) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 233 ms. Remains : 1226/1338 places, 2052/2194 transitions.
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 34 ms
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 36 ms
[2023-03-08 10:57:01] [INFO ] Input system was already deterministic with 2052 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 57 place count 1281 transition count 2120
Iterating global reduction 0 with 57 rules applied. Total rules applied 114 place count 1281 transition count 2120
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 147 place count 1248 transition count 2087
Iterating global reduction 0 with 33 rules applied. Total rules applied 180 place count 1248 transition count 2087
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 183 place count 1248 transition count 2084
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 192 place count 1239 transition count 2066
Iterating global reduction 1 with 9 rules applied. Total rules applied 201 place count 1239 transition count 2066
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 207 place count 1233 transition count 2060
Iterating global reduction 1 with 6 rules applied. Total rules applied 213 place count 1233 transition count 2060
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 214 place count 1233 transition count 2059
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 218 place count 1229 transition count 2055
Iterating global reduction 2 with 4 rules applied. Total rules applied 222 place count 1229 transition count 2055
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 226 place count 1225 transition count 2051
Iterating global reduction 2 with 4 rules applied. Total rules applied 230 place count 1225 transition count 2051
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 232 place count 1223 transition count 2049
Iterating global reduction 2 with 2 rules applied. Total rules applied 234 place count 1223 transition count 2049
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 235 place count 1222 transition count 2048
Iterating global reduction 2 with 1 rules applied. Total rules applied 236 place count 1222 transition count 2048
Applied a total of 236 rules in 190 ms. Remains 1222 /1338 variables (removed 116) and now considering 2048/2194 (removed 146) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 191 ms. Remains : 1222/1338 places, 2048/2194 transitions.
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 31 ms
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 33 ms
[2023-03-08 10:57:01] [INFO ] Input system was already deterministic with 2048 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 46 places :
Symmetric choice reduction at 0 with 46 rule applications. Total rules 46 place count 1292 transition count 2139
Iterating global reduction 0 with 46 rules applied. Total rules applied 92 place count 1292 transition count 2139
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 122 place count 1262 transition count 2109
Iterating global reduction 0 with 30 rules applied. Total rules applied 152 place count 1262 transition count 2109
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 154 place count 1262 transition count 2107
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 160 place count 1256 transition count 2100
Iterating global reduction 1 with 6 rules applied. Total rules applied 166 place count 1256 transition count 2100
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 171 place count 1251 transition count 2095
Iterating global reduction 1 with 5 rules applied. Total rules applied 176 place count 1251 transition count 2095
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 177 place count 1251 transition count 2094
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 181 place count 1247 transition count 2090
Iterating global reduction 2 with 4 rules applied. Total rules applied 185 place count 1247 transition count 2090
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 189 place count 1243 transition count 2086
Iterating global reduction 2 with 4 rules applied. Total rules applied 193 place count 1243 transition count 2086
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 195 place count 1241 transition count 2084
Iterating global reduction 2 with 2 rules applied. Total rules applied 197 place count 1241 transition count 2084
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 199 place count 1239 transition count 2082
Iterating global reduction 2 with 2 rules applied. Total rules applied 201 place count 1239 transition count 2082
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 202 place count 1238 transition count 2081
Iterating global reduction 2 with 1 rules applied. Total rules applied 203 place count 1238 transition count 2081
Applied a total of 203 rules in 275 ms. Remains 1238 /1338 variables (removed 100) and now considering 2081/2194 (removed 113) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 277 ms. Remains : 1238/1338 places, 2081/2194 transitions.
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 34 ms
[2023-03-08 10:57:01] [INFO ] Flatten gal took : 36 ms
[2023-03-08 10:57:02] [INFO ] Input system was already deterministic with 2081 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 57 places :
Symmetric choice reduction at 0 with 57 rule applications. Total rules 57 place count 1281 transition count 2120
Iterating global reduction 0 with 57 rules applied. Total rules applied 114 place count 1281 transition count 2120
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 149 place count 1246 transition count 2085
Iterating global reduction 0 with 35 rules applied. Total rules applied 184 place count 1246 transition count 2085
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 187 place count 1246 transition count 2082
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 197 place count 1236 transition count 2063
Iterating global reduction 1 with 10 rules applied. Total rules applied 207 place count 1236 transition count 2063
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 214 place count 1229 transition count 2056
Iterating global reduction 1 with 7 rules applied. Total rules applied 221 place count 1229 transition count 2056
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 222 place count 1229 transition count 2055
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 227 place count 1224 transition count 2050
Iterating global reduction 2 with 5 rules applied. Total rules applied 232 place count 1224 transition count 2050
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 237 place count 1219 transition count 2045
Iterating global reduction 2 with 5 rules applied. Total rules applied 242 place count 1219 transition count 2045
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 245 place count 1216 transition count 2042
Iterating global reduction 2 with 3 rules applied. Total rules applied 248 place count 1216 transition count 2042
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 250 place count 1214 transition count 2040
Iterating global reduction 2 with 2 rules applied. Total rules applied 252 place count 1214 transition count 2040
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 253 place count 1213 transition count 2039
Iterating global reduction 2 with 1 rules applied. Total rules applied 254 place count 1213 transition count 2039
Applied a total of 254 rules in 220 ms. Remains 1213 /1338 variables (removed 125) and now considering 2039/2194 (removed 155) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 221 ms. Remains : 1213/1338 places, 2039/2194 transitions.
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 31 ms
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 34 ms
[2023-03-08 10:57:02] [INFO ] Input system was already deterministic with 2039 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Discarding 56 places :
Symmetric choice reduction at 0 with 56 rule applications. Total rules 56 place count 1282 transition count 2129
Iterating global reduction 0 with 56 rules applied. Total rules applied 112 place count 1282 transition count 2129
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 145 place count 1249 transition count 2096
Iterating global reduction 0 with 33 rules applied. Total rules applied 178 place count 1249 transition count 2096
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 181 place count 1249 transition count 2093
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 189 place count 1241 transition count 2076
Iterating global reduction 1 with 8 rules applied. Total rules applied 197 place count 1241 transition count 2076
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 203 place count 1235 transition count 2070
Iterating global reduction 1 with 6 rules applied. Total rules applied 209 place count 1235 transition count 2070
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 210 place count 1235 transition count 2069
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 214 place count 1231 transition count 2065
Iterating global reduction 2 with 4 rules applied. Total rules applied 218 place count 1231 transition count 2065
Discarding 4 places :
Symmetric choice reduction at 2 with 4 rule applications. Total rules 222 place count 1227 transition count 2061
Iterating global reduction 2 with 4 rules applied. Total rules applied 226 place count 1227 transition count 2061
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 229 place count 1224 transition count 2058
Iterating global reduction 2 with 3 rules applied. Total rules applied 232 place count 1224 transition count 2058
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 234 place count 1222 transition count 2056
Iterating global reduction 2 with 2 rules applied. Total rules applied 236 place count 1222 transition count 2056
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 237 place count 1221 transition count 2055
Iterating global reduction 2 with 1 rules applied. Total rules applied 238 place count 1221 transition count 2055
Applied a total of 238 rules in 226 ms. Remains 1221 /1338 variables (removed 117) and now considering 2055/2194 (removed 139) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 227 ms. Remains : 1221/1338 places, 2055/2194 transitions.
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 33 ms
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 35 ms
[2023-03-08 10:57:02] [INFO ] Input system was already deterministic with 2055 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1338/1338 places, 2194/2194 transitions.
Graph (trivial) has 1230 edges and 1338 vertex of which 347 / 1338 are part of one of the 26 SCC in 0 ms
Free SCC test removed 321 places
Ensure Unique test removed 346 transitions
Reduce isomorphic transitions removed 346 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 262 transitions
Trivial Post-agglo rules discarded 262 transitions
Performed 262 trivial Post agglomeration. Transition count delta: 262
Iterating post reduction 0 with 262 rules applied. Total rules applied 263 place count 1016 transition count 1585
Reduce places removed 262 places and 0 transitions.
Ensure Unique test removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Drop transitions removed 20 transitions
Trivial Post-agglo rules discarded 20 transitions
Performed 20 trivial Post agglomeration. Transition count delta: 20
Iterating post reduction 1 with 297 rules applied. Total rules applied 560 place count 754 transition count 1550
Reduce places removed 20 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 22 rules applied. Total rules applied 582 place count 734 transition count 1548
Reduce places removed 1 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 3 with 4 rules applied. Total rules applied 586 place count 733 transition count 1545
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 5 rules applied. Total rules applied 591 place count 730 transition count 1543
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 592 place count 729 transition count 1543
Performed 82 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 82 Pre rules applied. Total rules applied 592 place count 729 transition count 1461
Deduced a syphon composed of 82 places in 2 ms
Reduce places removed 82 places and 0 transitions.
Iterating global reduction 6 with 164 rules applied. Total rules applied 756 place count 647 transition count 1461
Discarding 66 places :
Symmetric choice reduction at 6 with 66 rule applications. Total rules 822 place count 581 transition count 1244
Iterating global reduction 6 with 66 rules applied. Total rules applied 888 place count 581 transition count 1244
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 891 place count 581 transition count 1241
Performed 19 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 19 Pre rules applied. Total rules applied 891 place count 581 transition count 1222
Deduced a syphon composed of 19 places in 2 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 7 with 38 rules applied. Total rules applied 929 place count 562 transition count 1222
Discarding 4 places :
Symmetric choice reduction at 7 with 4 rule applications. Total rules 933 place count 558 transition count 1189
Iterating global reduction 7 with 4 rules applied. Total rules applied 937 place count 558 transition count 1189
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 7 with 3 rules applied. Total rules applied 940 place count 558 transition count 1186
Performed 184 Post agglomeration using F-continuation condition.Transition count delta: 184
Deduced a syphon composed of 184 places in 0 ms
Reduce places removed 184 places and 0 transitions.
Iterating global reduction 8 with 368 rules applied. Total rules applied 1308 place count 374 transition count 1002
Discarding 21 places :
Symmetric choice reduction at 8 with 21 rule applications. Total rules 1329 place count 353 transition count 825
Iterating global reduction 8 with 21 rules applied. Total rules applied 1350 place count 353 transition count 825
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 8 with 14 rules applied. Total rules applied 1364 place count 353 transition count 811
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 9 with 11 rules applied. Total rules applied 1375 place count 353 transition count 800
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 9 with 6 rules applied. Total rules applied 1381 place count 353 transition count 794
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 10 with 6 rules applied. Total rules applied 1387 place count 347 transition count 794
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 1389 place count 345 transition count 792
Applied a total of 1389 rules in 94 ms. Remains 345 /1338 variables (removed 993) and now considering 792/2194 (removed 1402) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 96 ms. Remains : 345/1338 places, 792/2194 transitions.
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 14 ms
[2023-03-08 10:57:02] [INFO ] Flatten gal took : 14 ms
[2023-03-08 10:57:02] [INFO ] Input system was already deterministic with 792 transitions.
[2023-03-08 10:57:03] [INFO ] Flatten gal took : 36 ms
[2023-03-08 10:57:03] [INFO ] Flatten gal took : 37 ms
[2023-03-08 10:57:03] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-08 10:57:03] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1338 places, 2194 transitions and 6209 arcs took 8 ms.
Total runtime 20662 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-05b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA DLCround-PT-05b-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678273294969

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-05b-CTLFireability-00
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-05b-CTLFireability-00
lola: result : true
lola: markings : 4
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-05b-CTLFireability-08
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for DLCround-PT-05b-CTLFireability-08
lola: result : true
lola: markings : 6
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 23 (type EXCL) for 22 DLCround-PT-05b-CTLFireability-06
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for DLCround-PT-05b-CTLFireability-06
lola: result : true
lola: markings : 79
lola: fired transitions : 79
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type EXCL) for 57 DLCround-PT-05b-CTLFireability-15
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 61 (type EXCL) for DLCround-PT-05b-CTLFireability-15
lola: result : true
lola: markings : 79
lola: fired transitions : 79
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 12 DLCround-PT-05b-CTLFireability-04
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for DLCround-PT-05b-CTLFireability-04
lola: result : true
lola: markings : 83
lola: fired transitions : 83
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-05b-CTLFireability-03
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DLCround-PT-05b-CTLFireability-03
lola: result : true
lola: markings : 7
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: LAUNCH task # 55 (type EXCL) for 54 DLCround-PT-05b-CTLFireability-14
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 4/299 3/32 DLCround-PT-05b-CTLFireability-14 257723 m, 51544 m/sec, 302915 t fired, .

Time elapsed: 10 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 9/299 7/32 DLCround-PT-05b-CTLFireability-14 667166 m, 81888 m/sec, 783318 t fired, .

Time elapsed: 15 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
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DLCround-PT-05b-CTLFireability-06: EG true state space / EG
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32 CTL EXCL 20/692 11/32 DLCround-PT-05b-CTLFireability-09 958540 m, 44109 m/sec, 2608913 t fired, .

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DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
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32 CTL EXCL 25/692 13/32 DLCround-PT-05b-CTLFireability-09 1173758 m, 43043 m/sec, 3265881 t fired, .

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DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
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32 CTL EXCL 30/692 15/32 DLCround-PT-05b-CTLFireability-09 1390776 m, 43403 m/sec, 3934468 t fired, .

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DLCround-PT-05b-CTLFireability-06: EG true state space / EG
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DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/1133 30/32 DLCround-PT-05b-CTLFireability-05 3293282 m, 109527 m/sec, 3546806 t fired, .

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DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1682 6/32 DLCround-PT-05b-CTLFireability-02 556793 m, 111358 m/sec, 603979 t fired, .

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DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1682 11/32 DLCround-PT-05b-CTLFireability-02 1094623 m, 107566 m/sec, 1187618 t fired, .

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DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1682 16/32 DLCround-PT-05b-CTLFireability-02 1628573 m, 106790 m/sec, 1767844 t fired, .

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DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1682 21/32 DLCround-PT-05b-CTLFireability-02 2163284 m, 106942 m/sec, 2349113 t fired, .

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DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 25/1682 26/32 DLCround-PT-05b-CTLFireability-02 2699232 m, 107189 m/sec, 2932045 t fired, .

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DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

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DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/1682 32/32 DLCround-PT-05b-CTLFireability-02 3234431 m, 107039 m/sec, 3514779 t fired, .

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DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-15: F false state space / EG

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DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-01: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-02: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-03: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-05: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-09: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-11: CONJ unknown CONJ
DLCround-PT-05b-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-14: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-15: F false state space / EG


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-05b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600658"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05b.tgz
mv DLCround-PT-05b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;