Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600650.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600650
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 792K
-rw-r--r-- 1 mcc users 8.0K Feb 25 18:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 18:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 18:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 18:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 18:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Feb 25 18:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 18:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 25 18:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 259K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05a-CTLFireability-00
FORMULA_NAME DLCround-PT-05a-CTLFireability-01
FORMULA_NAME DLCround-PT-05a-CTLFireability-02
FORMULA_NAME DLCround-PT-05a-CTLFireability-03
FORMULA_NAME DLCround-PT-05a-CTLFireability-04
FORMULA_NAME DLCround-PT-05a-CTLFireability-05
FORMULA_NAME DLCround-PT-05a-CTLFireability-06
FORMULA_NAME DLCround-PT-05a-CTLFireability-07
FORMULA_NAME DLCround-PT-05a-CTLFireability-08
FORMULA_NAME DLCround-PT-05a-CTLFireability-09
FORMULA_NAME DLCround-PT-05a-CTLFireability-10
FORMULA_NAME DLCround-PT-05a-CTLFireability-11
FORMULA_NAME DLCround-PT-05a-CTLFireability-12
FORMULA_NAME DLCround-PT-05a-CTLFireability-13
FORMULA_NAME DLCround-PT-05a-CTLFireability-14
FORMULA_NAME DLCround-PT-05a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678272597866

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-05a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:49:59] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 10:49:59] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:49:59] [INFO ] Load time of PNML (sax parser for PT used): 83 ms
[2023-03-08 10:49:59] [INFO ] Transformed 167 places.
[2023-03-08 10:49:59] [INFO ] Transformed 1055 transitions.
[2023-03-08 10:49:59] [INFO ] Found NUPN structural information;
[2023-03-08 10:49:59] [INFO ] Parsed PT model containing 167 places and 1055 transitions and 3985 arcs in 148 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 112 transitions
Reduce redundant transitions removed 112 transitions.
FORMULA DLCround-PT-05a-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 94 out of 167 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 167/167 places, 943/943 transitions.
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 4 place count 163 transition count 911
Iterating global reduction 0 with 4 rules applied. Total rules applied 8 place count 163 transition count 911
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 10 place count 163 transition count 909
Drop transitions removed 309 transitions
Redundant transition composition rules discarded 309 transitions
Iterating global reduction 1 with 309 rules applied. Total rules applied 319 place count 163 transition count 600
Applied a total of 319 rules in 45 ms. Remains 163 /167 variables (removed 4) and now considering 600/943 (removed 343) transitions.
[2023-03-08 10:49:59] [INFO ] Flow matrix only has 132 transitions (discarded 468 similar events)
// Phase 1: matrix 132 rows 163 cols
[2023-03-08 10:49:59] [INFO ] Computed 88 place invariants in 7 ms
[2023-03-08 10:50:00] [INFO ] Implicit Places using invariants in 482 ms returned [85, 87, 88, 90, 91, 93, 94, 96, 99, 101, 103, 106, 107, 111, 113, 115, 118, 119, 121, 123, 127, 129, 130, 131, 137, 140, 142, 147, 151, 152, 153, 154, 156, 161]
Discarding 34 places :
Ensure Unique test removed 133 transitions
Reduce isomorphic transitions removed 133 transitions.
Implicit Place search using SMT only with invariants took 511 ms to find 34 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 129/167 places, 467/943 transitions.
Drop transitions removed 278 transitions
Redundant transition composition rules discarded 278 transitions
Iterating global reduction 0 with 278 rules applied. Total rules applied 278 place count 129 transition count 189
Applied a total of 278 rules in 4 ms. Remains 129 /129 variables (removed 0) and now considering 189/467 (removed 278) transitions.
[2023-03-08 10:50:00] [INFO ] Flow matrix only has 132 transitions (discarded 57 similar events)
// Phase 1: matrix 132 rows 129 cols
[2023-03-08 10:50:00] [INFO ] Computed 54 place invariants in 4 ms
[2023-03-08 10:50:00] [INFO ] Implicit Places using invariants in 102 ms returned []
[2023-03-08 10:50:00] [INFO ] Flow matrix only has 132 transitions (discarded 57 similar events)
[2023-03-08 10:50:00] [INFO ] Invariant cache hit.
[2023-03-08 10:50:00] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-03-08 10:50:00] [INFO ] Implicit Places using invariants and state equation in 71 ms returned []
Implicit Place search using SMT with State Equation took 175 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 129/167 places, 189/943 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 735 ms. Remains : 129/167 places, 189/943 transitions.
Support contains 94 out of 129 places after structural reductions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 32 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 12 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 189 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 56) seen :55
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 10:50:00] [INFO ] Flow matrix only has 132 transitions (discarded 57 similar events)
[2023-03-08 10:50:00] [INFO ] Invariant cache hit.
[2023-03-08 10:50:00] [INFO ] [Real]Absence check using 54 positive place invariants in 9 ms returned sat
[2023-03-08 10:50:00] [INFO ] After 58ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
FORMULA DLCround-PT-05a-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 9 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 189 transitions.
Computed a total of 45 stabilizing places and 1 stable transitions
Graph (complete) has 256 edges and 129 vertex of which 91 are kept as prefixes of interest. Removing 38 places using SCC suffix rule.2 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Graph (trivial) has 149 edges and 129 vertex of which 62 / 129 are part of one of the 12 SCC in 3 ms
Free SCC test removed 50 places
Ensure Unique test removed 110 transitions
Reduce isomorphic transitions removed 110 transitions.
Graph (complete) has 146 edges and 79 vertex of which 46 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.0 ms
Discarding 33 places :
Also discarding 0 output transitions
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 6 place count 46 transition count 75
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 11 place count 42 transition count 74
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 20 place count 33 transition count 59
Iterating global reduction 2 with 9 rules applied. Total rules applied 29 place count 33 transition count 59
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 31 place count 32 transition count 58
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 2 with 6 rules applied. Total rules applied 37 place count 32 transition count 52
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 39 place count 31 transition count 51
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 40 place count 31 transition count 51
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 30 transition count 50
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 30 transition count 50
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 43 place count 30 transition count 49
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 44 place count 30 transition count 48
Applied a total of 44 rules in 20 ms. Remains 30 /129 variables (removed 99) and now considering 48/189 (removed 141) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 30/129 places, 48/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 48 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Graph (trivial) has 173 edges and 129 vertex of which 78 / 129 are part of one of the 10 SCC in 1 ms
Free SCC test removed 68 places
Ensure Unique test removed 156 transitions
Reduce isomorphic transitions removed 156 transitions.
Graph (complete) has 100 edges and 61 vertex of which 24 are kept as prefixes of interest. Removing 37 places using SCC suffix rule.1 ms
Discarding 37 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 24 transition count 32
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 23 transition count 32
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 16 place count 11 transition count 15
Iterating global reduction 2 with 12 rules applied. Total rules applied 28 place count 11 transition count 15
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 30 place count 10 transition count 14
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 32 place count 10 transition count 12
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 34 place count 9 transition count 11
Applied a total of 34 rules in 6 ms. Remains 9 /129 variables (removed 120) and now considering 11/189 (removed 178) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 9/129 places, 11/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 0 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 11 transitions.
Finished random walk after 7 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=7 )
FORMULA DLCround-PT-05a-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 31 places and 0 transitions.
Iterating post reduction 0 with 31 rules applied. Total rules applied 31 place count 98 transition count 189
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 45 place count 84 transition count 161
Iterating global reduction 1 with 14 rules applied. Total rules applied 59 place count 84 transition count 161
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 60 place count 84 transition count 160
Applied a total of 60 rules in 3 ms. Remains 84 /129 variables (removed 45) and now considering 160/189 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 84/129 places, 160/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 160 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 35 places and 0 transitions.
Iterating post reduction 0 with 35 rules applied. Total rules applied 35 place count 94 transition count 189
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 54 place count 75 transition count 151
Iterating global reduction 1 with 19 rules applied. Total rules applied 73 place count 75 transition count 151
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 74 place count 75 transition count 150
Applied a total of 74 rules in 4 ms. Remains 75 /129 variables (removed 54) and now considering 150/189 (removed 39) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 75/129 places, 150/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 150 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 36 places and 0 transitions.
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 93 transition count 189
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 54 place count 75 transition count 153
Iterating global reduction 1 with 18 rules applied. Total rules applied 72 place count 75 transition count 153
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 73 place count 75 transition count 152
Applied a total of 73 rules in 5 ms. Remains 75 /129 variables (removed 54) and now considering 152/189 (removed 37) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 75/129 places, 152/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:00] [INFO ] Input system was already deterministic with 152 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 34 places and 0 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 34 place count 95 transition count 189
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 53 place count 76 transition count 151
Iterating global reduction 1 with 19 rules applied. Total rules applied 72 place count 76 transition count 151
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 74 place count 76 transition count 149
Applied a total of 74 rules in 4 ms. Remains 76 /129 variables (removed 53) and now considering 149/189 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 76/129 places, 149/189 transitions.
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:00] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 149 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 36 places and 0 transitions.
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 93 transition count 189
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 52 place count 77 transition count 157
Iterating global reduction 1 with 16 rules applied. Total rules applied 68 place count 77 transition count 157
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 70 place count 77 transition count 155
Applied a total of 70 rules in 4 ms. Remains 77 /129 variables (removed 52) and now considering 155/189 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 77/129 places, 155/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 155 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 31 places and 0 transitions.
Iterating post reduction 0 with 31 rules applied. Total rules applied 31 place count 98 transition count 189
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 45 place count 84 transition count 161
Iterating global reduction 1 with 14 rules applied. Total rules applied 59 place count 84 transition count 161
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 61 place count 84 transition count 159
Applied a total of 61 rules in 3 ms. Remains 84 /129 variables (removed 45) and now considering 159/189 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 84/129 places, 159/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 159 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 35 places and 0 transitions.
Iterating post reduction 0 with 35 rules applied. Total rules applied 35 place count 94 transition count 189
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 54 place count 75 transition count 151
Iterating global reduction 1 with 19 rules applied. Total rules applied 73 place count 75 transition count 151
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 75 place count 75 transition count 149
Applied a total of 75 rules in 3 ms. Remains 75 /129 variables (removed 54) and now considering 149/189 (removed 40) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 75/129 places, 149/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 149 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Graph (trivial) has 169 edges and 129 vertex of which 76 / 129 are part of one of the 10 SCC in 0 ms
Free SCC test removed 66 places
Ensure Unique test removed 151 transitions
Reduce isomorphic transitions removed 151 transitions.
Graph (complete) has 105 edges and 63 vertex of which 28 are kept as prefixes of interest. Removing 35 places using SCC suffix rule.0 ms
Discarding 35 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 28 transition count 37
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 27 transition count 37
Discarding 10 places :
Symmetric choice reduction at 2 with 10 rule applications. Total rules 14 place count 17 transition count 22
Iterating global reduction 2 with 10 rules applied. Total rules applied 24 place count 17 transition count 22
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 26 place count 16 transition count 21
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 28 place count 16 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 30 place count 15 transition count 18
Applied a total of 30 rules in 5 ms. Remains 15 /129 variables (removed 114) and now considering 18/189 (removed 171) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 15/129 places, 18/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 32 places and 0 transitions.
Iterating post reduction 0 with 32 rules applied. Total rules applied 32 place count 97 transition count 189
Discarding 18 places :
Symmetric choice reduction at 1 with 18 rule applications. Total rules 50 place count 79 transition count 153
Iterating global reduction 1 with 18 rules applied. Total rules applied 68 place count 79 transition count 153
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 70 place count 79 transition count 151
Applied a total of 70 rules in 2 ms. Remains 79 /129 variables (removed 50) and now considering 151/189 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 79/129 places, 151/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 151 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 38 places and 0 transitions.
Iterating post reduction 0 with 38 rules applied. Total rules applied 38 place count 91 transition count 189
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 58 place count 71 transition count 149
Iterating global reduction 1 with 20 rules applied. Total rules applied 78 place count 71 transition count 149
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 79 place count 71 transition count 148
Applied a total of 79 rules in 3 ms. Remains 71 /129 variables (removed 58) and now considering 148/189 (removed 41) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 71/129 places, 148/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 148 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 34 places and 0 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 34 place count 95 transition count 189
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 54 place count 75 transition count 149
Iterating global reduction 1 with 20 rules applied. Total rules applied 74 place count 75 transition count 149
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 76 place count 75 transition count 147
Applied a total of 76 rules in 3 ms. Remains 75 /129 variables (removed 54) and now considering 147/189 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 75/129 places, 147/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 8 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 147 transitions.
Starting structural reductions in LTL mode, iteration 0 : 129/129 places, 189/189 transitions.
Reduce places removed 34 places and 0 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 34 place count 95 transition count 189
Discarding 21 places :
Symmetric choice reduction at 1 with 21 rule applications. Total rules 55 place count 74 transition count 147
Iterating global reduction 1 with 21 rules applied. Total rules applied 76 place count 74 transition count 147
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 78 place count 74 transition count 145
Applied a total of 78 rules in 2 ms. Remains 74 /129 variables (removed 55) and now considering 145/189 (removed 44) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 74/129 places, 145/189 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 4 ms
[2023-03-08 10:50:01] [INFO ] Input system was already deterministic with 145 transitions.
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:50:01] [INFO ] Flatten gal took : 6 ms
[2023-03-08 10:50:01] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 10:50:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 129 places, 189 transitions and 455 arcs took 0 ms.
Total runtime 1823 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA DLCround-PT-05a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-05a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678272937921

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-05a-CTLFireability-05
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:737
lola: rewrite Frontend/Parser/formula_rewrite.k:693
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 10 (type EXCL) for DLCround-PT-05a-CTLFireability-05
lola: result : false
lola: markings : 27
lola: fired transitions : 70
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 34 (type EXCL) for 33 DLCround-PT-05a-CTLFireability-09
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 65 (type FNDP) for 22 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 22 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SRCH) for 22 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 68 (type SRCH) for DLCround-PT-05a-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 65 (type FNDP) for DLCround-PT-05a-CTLFireability-08
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 66 (type EQUN) for DLCround-PT-05a-CTLFireability-08 (obsolete)
lola: FINISHED task # 66 (type EQUN) for DLCround-PT-05a-CTLFireability-08
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 70 (type FNDP) for 49 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 49 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type SRCH) for 49 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type SRCH) for DLCround-PT-05a-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 70 (type FNDP) for DLCround-PT-05a-CTLFireability-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for DLCround-PT-05a-CTLFireability-13 (obsolete)
lola: FINISHED task # 71 (type EQUN) for DLCround-PT-05a-CTLFireability-13
lola: result : unknown
lola: FINISHED task # 34 (type EXCL) for DLCround-PT-05a-CTLFireability-09
lola: result : false
lola: markings : 36429
lola: fired transitions : 217801
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 DLCround-PT-05a-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 6 0 0 2
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 5/257 4/32 DLCround-PT-05a-CTLFireability-14 869105 m, 173821 m/sec, 4360078 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 10/257 8/32 DLCround-PT-05a-CTLFireability-14 1703665 m, 166912 m/sec, 8721726 t fired, .

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DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 6 0 0 1
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 15/257 11/32 DLCround-PT-05a-CTLFireability-14 2494415 m, 158150 m/sec, 12852052 t fired, .

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DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 6 0 0 1
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61 CTL EXCL 20/257 15/32 DLCround-PT-05a-CTLFireability-14 3261623 m, 153441 m/sec, 16886508 t fired, .

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61 CTL EXCL 25/257 18/32 DLCround-PT-05a-CTLFireability-14 3989234 m, 145522 m/sec, 20801085 t fired, .

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4 CTL EXCL 5/666 4/32 DLCround-PT-05a-CTLFireability-02 728542 m, 145708 m/sec, 4826705 t fired, .

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-00: EFEG true state space /EFEG
DLCround-PT-05a-CTLFireability-02: CTL unknown AGGR
DLCround-PT-05a-CTLFireability-03: CTL unknown AGGR
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-06: CTL unknown AGGR
DLCround-PT-05a-CTLFireability-07: CONJ unknown CONJ
DLCround-PT-05a-CTLFireability-08: DISJ false DISJ
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-10: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600650"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05a.tgz
mv DLCround-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;