About the Execution of LoLa+red for DLCround-PT-03b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 664.380 | 16554.00 | 33717.00 | 302.70 | FFTFTTFTFFFFTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600630.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-03b, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600630
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 860K
-rw-r--r-- 1 mcc users 6.2K Feb 25 18:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 25 18:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 18:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 18:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 18:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 18:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 18:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 18:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 432K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-00
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-01
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-02
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-03
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-04
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-05
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-06
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-07
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-08
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-09
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-10
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-11
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-12
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-13
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-14
FORMULA_NAME DLCround-PT-03b-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678270889896
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-03b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:21:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-08 10:21:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:21:31] [INFO ] Load time of PNML (sax parser for PT used): 97 ms
[2023-03-08 10:21:31] [INFO ] Transformed 1383 places.
[2023-03-08 10:21:31] [INFO ] Transformed 1887 transitions.
[2023-03-08 10:21:31] [INFO ] Found NUPN structural information;
[2023-03-08 10:21:31] [INFO ] Parsed PT model containing 1383 places and 1887 transitions and 4809 arcs in 176 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 16 ms.
Working with output stream class java.io.PrintStream
FORMULA DLCround-PT-03b-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-03b-ReachabilityCardinality-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-03b-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DLCround-PT-03b-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 371 ms. (steps per millisecond=26 ) properties (out of 12) seen :7
FORMULA DLCround-PT-03b-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 1887 rows 1383 cols
[2023-03-08 10:21:32] [INFO ] Computed 52 place invariants in 34 ms
[2023-03-08 10:21:32] [INFO ] After 649ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-08 10:21:33] [INFO ] [Nat]Absence check using 52 positive place invariants in 29 ms returned sat
[2023-03-08 10:21:34] [INFO ] After 998ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :4
[2023-03-08 10:21:34] [INFO ] Deduced a trap composed of 103 places in 183 ms of which 7 ms to minimize.
[2023-03-08 10:21:35] [INFO ] Deduced a trap composed of 132 places in 165 ms of which 1 ms to minimize.
[2023-03-08 10:21:35] [INFO ] Deduced a trap composed of 116 places in 130 ms of which 2 ms to minimize.
[2023-03-08 10:21:35] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 761 ms
[2023-03-08 10:21:35] [INFO ] Deduced a trap composed of 75 places in 239 ms of which 2 ms to minimize.
[2023-03-08 10:21:36] [INFO ] Deduced a trap composed of 75 places in 185 ms of which 1 ms to minimize.
[2023-03-08 10:21:36] [INFO ] Deduced a trap composed of 73 places in 158 ms of which 1 ms to minimize.
[2023-03-08 10:21:36] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 830 ms
[2023-03-08 10:21:36] [INFO ] After 3110ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :4
Attempting to minimize the solution found.
Minimization took 383 ms.
[2023-03-08 10:21:36] [INFO ] After 3966ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :4
FORMULA DLCround-PT-03b-ReachabilityCardinality-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 5 Parikh solutions to 4 different solutions.
FORMULA DLCround-PT-03b-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 64 ms.
Support contains 99 out of 1383 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1383/1383 places, 1887/1887 transitions.
Graph (trivial) has 1154 edges and 1383 vertex of which 111 / 1383 are part of one of the 15 SCC in 6 ms
Free SCC test removed 96 places
Drop transitions removed 112 transitions
Reduce isomorphic transitions removed 112 transitions.
Drop transitions removed 528 transitions
Trivial Post-agglo rules discarded 528 transitions
Performed 528 trivial Post agglomeration. Transition count delta: 528
Iterating post reduction 0 with 528 rules applied. Total rules applied 529 place count 1287 transition count 1247
Reduce places removed 528 places and 0 transitions.
Ensure Unique test removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 1 with 556 rules applied. Total rules applied 1085 place count 759 transition count 1219
Reduce places removed 14 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 16 rules applied. Total rules applied 1101 place count 745 transition count 1217
Reduce places removed 1 places and 0 transitions.
Performed 52 Post agglomeration using F-continuation condition.Transition count delta: 52
Iterating post reduction 3 with 53 rules applied. Total rules applied 1154 place count 744 transition count 1165
Reduce places removed 52 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 54 rules applied. Total rules applied 1208 place count 692 transition count 1163
Performed 30 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 30 Pre rules applied. Total rules applied 1208 place count 692 transition count 1133
Deduced a syphon composed of 30 places in 2 ms
Reduce places removed 30 places and 0 transitions.
Iterating global reduction 5 with 60 rules applied. Total rules applied 1268 place count 662 transition count 1133
Discarding 99 places :
Symmetric choice reduction at 5 with 99 rule applications. Total rules 1367 place count 563 transition count 1034
Iterating global reduction 5 with 99 rules applied. Total rules applied 1466 place count 563 transition count 1034
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 1468 place count 563 transition count 1032
Performed 32 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 32 Pre rules applied. Total rules applied 1468 place count 563 transition count 1000
Deduced a syphon composed of 32 places in 4 ms
Reduce places removed 32 places and 0 transitions.
Iterating global reduction 6 with 64 rules applied. Total rules applied 1532 place count 531 transition count 1000
Discarding 9 places :
Symmetric choice reduction at 6 with 9 rule applications. Total rules 1541 place count 522 transition count 940
Iterating global reduction 6 with 9 rules applied. Total rules applied 1550 place count 522 transition count 940
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 1551 place count 522 transition count 939
Performed 127 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 127 places in 1 ms
Reduce places removed 127 places and 0 transitions.
Iterating global reduction 7 with 254 rules applied. Total rules applied 1805 place count 395 transition count 811
Discarding 8 places :
Symmetric choice reduction at 7 with 8 rule applications. Total rules 1813 place count 387 transition count 755
Iterating global reduction 7 with 8 rules applied. Total rules applied 1821 place count 387 transition count 755
Performed 48 Post agglomeration using F-continuation condition with reduction of 8 identical transitions.
Deduced a syphon composed of 48 places in 1 ms
Reduce places removed 48 places and 0 transitions.
Iterating global reduction 7 with 96 rules applied. Total rules applied 1917 place count 339 transition count 1023
Drop transitions removed 26 transitions
Reduce isomorphic transitions removed 26 transitions.
Iterating post reduction 7 with 26 rules applied. Total rules applied 1943 place count 339 transition count 997
Discarding 5 places :
Symmetric choice reduction at 8 with 5 rule applications. Total rules 1948 place count 334 transition count 932
Iterating global reduction 8 with 5 rules applied. Total rules applied 1953 place count 334 transition count 932
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 8 with 10 rules applied. Total rules applied 1963 place count 334 transition count 922
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -38
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 9 with 6 rules applied. Total rules applied 1969 place count 331 transition count 960
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 9 with 5 rules applied. Total rules applied 1974 place count 331 transition count 955
Drop transitions removed 52 transitions
Redundant transition composition rules discarded 52 transitions
Iterating global reduction 10 with 52 rules applied. Total rules applied 2026 place count 331 transition count 903
Discarding 3 places :
Symmetric choice reduction at 10 with 3 rule applications. Total rules 2029 place count 328 transition count 877
Iterating global reduction 10 with 3 rules applied. Total rules applied 2032 place count 328 transition count 877
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 10 with 2 rules applied. Total rules applied 2034 place count 328 transition count 875
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -25
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 11 with 4 rules applied. Total rules applied 2038 place count 326 transition count 900
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 11 with 2 rules applied. Total rules applied 2040 place count 326 transition count 898
Drop transitions removed 3 transitions
Redundant transition composition rules discarded 3 transitions
Iterating global reduction 12 with 3 rules applied. Total rules applied 2043 place count 326 transition count 895
Free-agglomeration rule applied 65 times with reduction of 11 identical transitions.
Iterating global reduction 12 with 65 rules applied. Total rules applied 2108 place count 326 transition count 819
Reduce places removed 65 places and 0 transitions.
Drop transitions removed 56 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 63 transitions.
Iterating post reduction 12 with 128 rules applied. Total rules applied 2236 place count 261 transition count 756
Drop transitions removed 27 transitions
Redundant transition composition rules discarded 27 transitions
Iterating global reduction 13 with 27 rules applied. Total rules applied 2263 place count 261 transition count 729
Free-agglomeration rule applied 1 times.
Iterating global reduction 13 with 1 rules applied. Total rules applied 2264 place count 261 transition count 728
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 13 with 7 rules applied. Total rules applied 2271 place count 260 transition count 722
Partial Free-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 14 with 4 rules applied. Total rules applied 2275 place count 260 transition count 722
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 14 with 1 rules applied. Total rules applied 2276 place count 260 transition count 721
Applied a total of 2276 rules in 357 ms. Remains 260 /1383 variables (removed 1123) and now considering 721/1887 (removed 1166) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 357 ms. Remains : 260/1383 places, 721/1887 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=104 ) properties (out of 3) seen :1
FORMULA DLCround-PT-03b-ReachabilityCardinality-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-08 10:21:37] [INFO ] Flow matrix only has 556 transitions (discarded 165 similar events)
// Phase 1: matrix 556 rows 260 cols
[2023-03-08 10:21:37] [INFO ] Computed 52 place invariants in 5 ms
[2023-03-08 10:21:37] [INFO ] After 50ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 10:21:37] [INFO ] [Nat]Absence check using 52 positive place invariants in 8 ms returned sat
[2023-03-08 10:21:37] [INFO ] After 166ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-08 10:21:37] [INFO ] State equation strengthened by 100 read => feed constraints.
[2023-03-08 10:21:37] [INFO ] After 87ms SMT Verify possible using 100 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-08 10:21:37] [INFO ] After 180ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 63 ms.
[2023-03-08 10:21:38] [INFO ] After 474ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 1 ms.
Support contains 46 out of 260 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 260/260 places, 721/721 transitions.
Graph (trivial) has 117 edges and 260 vertex of which 18 / 260 are part of one of the 7 SCC in 1 ms
Free SCC test removed 11 places
Drop transitions removed 19 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 20 transitions.
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 0 with 14 rules applied. Total rules applied 15 place count 249 transition count 687
Reduce places removed 14 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Iterating post reduction 1 with 18 rules applied. Total rules applied 33 place count 235 transition count 683
Reduce places removed 4 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 38 place count 231 transition count 682
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 12 Pre rules applied. Total rules applied 38 place count 231 transition count 670
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 3 with 24 rules applied. Total rules applied 62 place count 219 transition count 670
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 67 place count 214 transition count 659
Iterating global reduction 3 with 5 rules applied. Total rules applied 72 place count 214 transition count 659
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 3 with 10 rules applied. Total rules applied 82 place count 214 transition count 649
Performed 12 Post agglomeration using F-continuation condition with reduction of 1 identical transitions.
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 4 with 24 rules applied. Total rules applied 106 place count 202 transition count 636
Drop transitions removed 19 transitions
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 38 transitions.
Iterating post reduction 4 with 38 rules applied. Total rules applied 144 place count 202 transition count 598
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 145 place count 201 transition count 590
Iterating global reduction 5 with 1 rules applied. Total rules applied 146 place count 201 transition count 590
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: -33
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 5 with 20 rules applied. Total rules applied 166 place count 191 transition count 623
Drop transitions removed 23 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 5 with 30 rules applied. Total rules applied 196 place count 191 transition count 593
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 197 place count 190 transition count 585
Iterating global reduction 6 with 1 rules applied. Total rules applied 198 place count 190 transition count 585
Drop transitions removed 52 transitions
Redundant transition composition rules discarded 52 transitions
Iterating global reduction 6 with 52 rules applied. Total rules applied 250 place count 190 transition count 533
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 251 place count 189 transition count 528
Iterating global reduction 6 with 1 rules applied. Total rules applied 252 place count 189 transition count 528
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 254 place count 188 transition count 539
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 6 with 4 rules applied. Total rules applied 258 place count 188 transition count 535
Drop transitions removed 7 transitions
Redundant transition composition rules discarded 7 transitions
Iterating global reduction 7 with 7 rules applied. Total rules applied 265 place count 188 transition count 528
Free-agglomeration rule applied 12 times.
Iterating global reduction 7 with 12 rules applied. Total rules applied 277 place count 188 transition count 516
Reduce places removed 12 places and 0 transitions.
Drop transitions removed 31 transitions
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 35 transitions.
Iterating post reduction 7 with 47 rules applied. Total rules applied 324 place count 176 transition count 481
Drop transitions removed 4 transitions
Redundant transition composition rules discarded 4 transitions
Iterating global reduction 8 with 4 rules applied. Total rules applied 328 place count 176 transition count 477
Partial Free-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 8 with 3 rules applied. Total rules applied 331 place count 176 transition count 477
Applied a total of 331 rules in 76 ms. Remains 176 /260 variables (removed 84) and now considering 477/721 (removed 244) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 76 ms. Remains : 176/260 places, 477/721 transitions.
Finished random walk after 8341 steps, including 2 resets, run visited all 2 properties in 59 ms. (steps per millisecond=141 )
FORMULA DLCround-PT-03b-ReachabilityCardinality-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA DLCround-PT-03b-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
All properties solved without resorting to model-checking.
Total runtime 6864 ms.
starting LoLA
BK_INPUT DLCround-PT-03b
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA DLCround-PT-03b-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-03b-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678270906450
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 21 DLCround-PT-03b-ReachabilityCardinality-07
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type FNDP) for 6 DLCround-PT-03b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 6 DLCround-PT-03b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 6 DLCround-PT-03b-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 56 (type EXCL) for DLCround-PT-03b-ReachabilityCardinality-07
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 12 DLCround-PT-03b-ReachabilityCardinality-04
lola: time limit : 239 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-59.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 59 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 58 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 61 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 103 (type FNDP) for 0 DLCround-PT-03b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type EQUN) for 0 DLCround-PT-03b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 110 (type SRCH) for 0 DLCround-PT-03b-ReachabilityCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 82339
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 110 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-00
lola: result : true
lola: markings : 91
lola: fired transitions : 111
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 103 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-00 (obsolete)
lola: CANCELED task # 104 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-00 (obsolete)
lola: LAUNCH task # 87 (type FNDP) for 3 DLCround-PT-03b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 3 DLCround-PT-03b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 3 DLCround-PT-03b-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 103 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-00
lola: result : true
lola: fired transitions : 109
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 90 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-01
lola: result : true
lola: markings : 32
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 87 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 88 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 9 DLCround-PT-03b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type EQUN) for 9 DLCround-PT-03b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type SRCH) for 9 DLCround-PT-03b-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 100 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-03
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 93 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 95 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 148 (type FNDP) for 30 DLCround-PT-03b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 149 (type EQUN) for 30 DLCround-PT-03b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 151 (type SRCH) for 30 DLCround-PT-03b-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 151 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-10
lola: result : true
lola: markings : 23
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 148 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 149 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 127 (type FNDP) for 39 DLCround-PT-03b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type EQUN) for 39 DLCround-PT-03b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 130 (type SRCH) for 39 DLCround-PT-03b-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-95.sara.
lola: FINISHED task # 130 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-13
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 127 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 128 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 134 (type FNDP) for 33 DLCround-PT-03b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 135 (type EQUN) for 33 DLCround-PT-03b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 137 (type SRCH) for 33 DLCround-PT-03b-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
lola: FINISHED task # 127 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 148 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 87 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 30
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-149.sara.
lola: FINISHED task # 134 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 135 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 137 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 113 (type FNDP) for 42 DLCround-PT-03b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type EQUN) for 42 DLCround-PT-03b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type SRCH) for 42 DLCround-PT-03b-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 116 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-14
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 113 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 114 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 120 (type FNDP) for 45 DLCround-PT-03b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type EQUN) for 45 DLCround-PT-03b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 123 (type SRCH) for 45 DLCround-PT-03b-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 113 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-128.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-135.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-104.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-121.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-114.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 149 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 121 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 120 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 123 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 80 (type FNDP) for 24 DLCround-PT-03b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 24 DLCround-PT-03b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SRCH) for 24 DLCround-PT-03b-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 120 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 79325
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 80 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 16
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 81 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 83 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 68 (type FNDP) for 27 DLCround-PT-03b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 27 DLCround-PT-03b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 75 (type SRCH) for 27 DLCround-PT-03b-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-73.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 73 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-09
lola: result : false
lola: CANCELED task # 68 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 75 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 67 (type FNDP) for 15 DLCround-PT-03b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 15 DLCround-PT-03b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type SRCH) for 15 DLCround-PT-03b-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 71 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-05
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 67 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 69 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 96 (type FNDP) for 18 DLCround-PT-03b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 98 (type EQUN) for 18 DLCround-PT-03b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type SRCH) for 18 DLCround-PT-03b-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 67 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 107 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-06
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 96 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-06 (obsolete)
lola: CANCELED task # 98 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 141 (type FNDP) for 36 DLCround-PT-03b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 142 (type EQUN) for 36 DLCround-PT-03b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 144 (type SRCH) for 36 DLCround-PT-03b-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-09
lola: result : unknown
lola: fired transitions : 55760
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 96 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-69.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-98.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-142.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 98 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-06
lola: result : true
lola: FINISHED task # 69 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-05
lola: result : true
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 142 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-12
lola: result : false
lola: CANCELED task # 141 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 144 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-12 (obsolete)
lola: LAUNCH task # 48 (type FNDP) for 12 DLCround-PT-03b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 12 DLCround-PT-03b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 12 DLCround-PT-03b-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 141 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-12
lola: result : unknown
lola: fired transitions : 80969
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 48 (type FNDP) for DLCround-PT-03b-ReachabilityCardinality-04
lola: result : true
lola: fired transitions : 5
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 49 (type EQUN) for DLCround-PT-03b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 64 (type SRCH) for DLCround-PT-03b-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 65 (type EXCL) for DLCround-PT-03b-ReachabilityCardinality-04 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-ReachabilityCardinality-00: AG false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-01: AG false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-02: AG true state equation
DLCround-PT-03b-ReachabilityCardinality-03: EF false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-04: EF true findpath
DLCround-PT-03b-ReachabilityCardinality-05: EF true tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-06: AG false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-07: EF true tandem / relaxed
DLCround-PT-03b-ReachabilityCardinality-08: AG false findpath
DLCround-PT-03b-ReachabilityCardinality-09: EF false state equation
DLCround-PT-03b-ReachabilityCardinality-10: AG false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-11: AG false findpath
DLCround-PT-03b-ReachabilityCardinality-12: AG true state equation
DLCround-PT-03b-ReachabilityCardinality-13: AG false tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-14: EF true tandem / insertion
DLCround-PT-03b-ReachabilityCardinality-15: AG true state equation
Time elapsed: 7 secs. Pages in use: 3
lola: rewrite Frontend/Parser/formula_rewrite.k:711
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-03b"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-03b, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600630"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-03b.tgz
mv DLCround-PT-03b execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;