Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478600626.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCround-PT-03b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478600626
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 860K
-rw-r--r-- 1 mcc users 6.2K Feb 25 18:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 65K Feb 25 18:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 18:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 18:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 18:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 25 18:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 18:20 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 18:20 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 432K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-03b-CTLFireability-00
FORMULA_NAME DLCround-PT-03b-CTLFireability-01
FORMULA_NAME DLCround-PT-03b-CTLFireability-02
FORMULA_NAME DLCround-PT-03b-CTLFireability-03
FORMULA_NAME DLCround-PT-03b-CTLFireability-04
FORMULA_NAME DLCround-PT-03b-CTLFireability-05
FORMULA_NAME DLCround-PT-03b-CTLFireability-06
FORMULA_NAME DLCround-PT-03b-CTLFireability-07
FORMULA_NAME DLCround-PT-03b-CTLFireability-08
FORMULA_NAME DLCround-PT-03b-CTLFireability-09
FORMULA_NAME DLCround-PT-03b-CTLFireability-10
FORMULA_NAME DLCround-PT-03b-CTLFireability-11
FORMULA_NAME DLCround-PT-03b-CTLFireability-12
FORMULA_NAME DLCround-PT-03b-CTLFireability-13
FORMULA_NAME DLCround-PT-03b-CTLFireability-14
FORMULA_NAME DLCround-PT-03b-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678270511883

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-03b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:15:13] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 10:15:13] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:15:13] [INFO ] Load time of PNML (sax parser for PT used): 95 ms
[2023-03-08 10:15:13] [INFO ] Transformed 1383 places.
[2023-03-08 10:15:13] [INFO ] Transformed 1887 transitions.
[2023-03-08 10:15:13] [INFO ] Found NUPN structural information;
[2023-03-08 10:15:13] [INFO ] Parsed PT model containing 1383 places and 1887 transitions and 4809 arcs in 170 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 148 out of 1383 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1383/1383 places, 1887/1887 transitions.
Discarding 211 places :
Symmetric choice reduction at 0 with 211 rule applications. Total rules 211 place count 1172 transition count 1676
Iterating global reduction 0 with 211 rules applied. Total rules applied 422 place count 1172 transition count 1676
Discarding 140 places :
Symmetric choice reduction at 0 with 140 rule applications. Total rules 562 place count 1032 transition count 1536
Iterating global reduction 0 with 140 rules applied. Total rules applied 702 place count 1032 transition count 1536
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 706 place count 1032 transition count 1532
Discarding 29 places :
Symmetric choice reduction at 1 with 29 rule applications. Total rules 735 place count 1003 transition count 1489
Iterating global reduction 1 with 29 rules applied. Total rules applied 764 place count 1003 transition count 1489
Discarding 21 places :
Symmetric choice reduction at 1 with 21 rule applications. Total rules 785 place count 982 transition count 1468
Iterating global reduction 1 with 21 rules applied. Total rules applied 806 place count 982 transition count 1468
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 808 place count 982 transition count 1466
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 819 place count 971 transition count 1455
Iterating global reduction 2 with 11 rules applied. Total rules applied 830 place count 971 transition count 1455
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 841 place count 960 transition count 1444
Iterating global reduction 2 with 11 rules applied. Total rules applied 852 place count 960 transition count 1444
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 861 place count 951 transition count 1435
Iterating global reduction 2 with 9 rules applied. Total rules applied 870 place count 951 transition count 1435
Discarding 5 places :
Symmetric choice reduction at 2 with 5 rule applications. Total rules 875 place count 946 transition count 1430
Iterating global reduction 2 with 5 rules applied. Total rules applied 880 place count 946 transition count 1430
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 883 place count 943 transition count 1427
Iterating global reduction 2 with 3 rules applied. Total rules applied 886 place count 943 transition count 1427
Discarding 3 places :
Symmetric choice reduction at 2 with 3 rule applications. Total rules 889 place count 940 transition count 1424
Iterating global reduction 2 with 3 rules applied. Total rules applied 892 place count 940 transition count 1424
Applied a total of 892 rules in 493 ms. Remains 940 /1383 variables (removed 443) and now considering 1424/1887 (removed 463) transitions.
// Phase 1: matrix 1424 rows 940 cols
[2023-03-08 10:15:14] [INFO ] Computed 52 place invariants in 27 ms
[2023-03-08 10:15:14] [INFO ] Implicit Places using invariants in 363 ms returned []
[2023-03-08 10:15:14] [INFO ] Invariant cache hit.
[2023-03-08 10:15:14] [INFO ] Implicit Places using invariants and state equation in 543 ms returned []
Implicit Place search using SMT with State Equation took 931 ms to find 0 implicit places.
[2023-03-08 10:15:14] [INFO ] Invariant cache hit.
[2023-03-08 10:15:15] [INFO ] Dead Transitions using invariants and state equation in 491 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 940/1383 places, 1424/1887 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1916 ms. Remains : 940/1383 places, 1424/1887 transitions.
Support contains 148 out of 940 places after structural reductions.
[2023-03-08 10:15:15] [INFO ] Flatten gal took : 103 ms
[2023-03-08 10:15:15] [INFO ] Flatten gal took : 65 ms
[2023-03-08 10:15:16] [INFO ] Input system was already deterministic with 1424 transitions.
Support contains 141 out of 940 places (down from 148) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 459 ms. (steps per millisecond=21 ) properties (out of 88) seen :74
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 13) seen :0
Running SMT prover for 13 properties.
[2023-03-08 10:15:16] [INFO ] Invariant cache hit.
[2023-03-08 10:15:17] [INFO ] [Real]Absence check using 52 positive place invariants in 34 ms returned sat
[2023-03-08 10:15:18] [INFO ] After 1435ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:12
[2023-03-08 10:15:18] [INFO ] [Nat]Absence check using 52 positive place invariants in 20 ms returned sat
[2023-03-08 10:15:19] [INFO ] After 860ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :12
[2023-03-08 10:15:20] [INFO ] After 1800ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :12
Attempting to minimize the solution found.
Minimization took 486 ms.
[2023-03-08 10:15:21] [INFO ] After 2739ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :12
Fused 13 Parikh solutions to 11 different solutions.
Parikh walk visited 7 properties in 148 ms.
Support contains 12 out of 940 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 869 edges and 940 vertex of which 227 / 940 are part of one of the 19 SCC in 5 ms
Free SCC test removed 208 places
Drop transitions removed 236 transitions
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 241 transitions.
Drop transitions removed 210 transitions
Trivial Post-agglo rules discarded 210 transitions
Performed 210 trivial Post agglomeration. Transition count delta: 210
Iterating post reduction 0 with 210 rules applied. Total rules applied 211 place count 732 transition count 973
Reduce places removed 210 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 18 transitions
Trivial Post-agglo rules discarded 18 transitions
Performed 18 trivial Post agglomeration. Transition count delta: 18
Iterating post reduction 1 with 238 rules applied. Total rules applied 449 place count 522 transition count 945
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 22 rules applied. Total rules applied 471 place count 504 transition count 941
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 475 place count 502 transition count 939
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 477 place count 500 transition count 939
Performed 56 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 56 Pre rules applied. Total rules applied 477 place count 500 transition count 883
Deduced a syphon composed of 56 places in 1 ms
Reduce places removed 56 places and 0 transitions.
Iterating global reduction 5 with 112 rules applied. Total rules applied 589 place count 444 transition count 883
Discarding 48 places :
Symmetric choice reduction at 5 with 48 rule applications. Total rules 637 place count 396 transition count 745
Iterating global reduction 5 with 48 rules applied. Total rules applied 685 place count 396 transition count 745
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 687 place count 396 transition count 743
Performed 14 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 14 Pre rules applied. Total rules applied 687 place count 396 transition count 729
Deduced a syphon composed of 14 places in 1 ms
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 6 with 28 rules applied. Total rules applied 715 place count 382 transition count 729
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 716 place count 381 transition count 722
Iterating global reduction 6 with 1 rules applied. Total rules applied 717 place count 381 transition count 722
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 718 place count 381 transition count 721
Performed 134 Post agglomeration using F-continuation condition with reduction of 3 identical transitions.
Deduced a syphon composed of 134 places in 0 ms
Reduce places removed 134 places and 0 transitions.
Iterating global reduction 7 with 268 rules applied. Total rules applied 986 place count 247 transition count 584
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 7 with 6 rules applied. Total rules applied 992 place count 247 transition count 578
Discarding 12 places :
Symmetric choice reduction at 8 with 12 rule applications. Total rules 1004 place count 235 transition count 506
Iterating global reduction 8 with 12 rules applied. Total rules applied 1016 place count 235 transition count 506
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 8 with 9 rules applied. Total rules applied 1025 place count 235 transition count 497
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 9 with 6 rules applied. Total rules applied 1031 place count 232 transition count 494
Performed 30 Post agglomeration using F-continuation condition with reduction of 16 identical transitions.
Deduced a syphon composed of 30 places in 1 ms
Reduce places removed 30 places and 0 transitions.
Iterating global reduction 9 with 60 rules applied. Total rules applied 1091 place count 202 transition count 646
Drop transitions removed 13 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 9 with 14 rules applied. Total rules applied 1105 place count 202 transition count 632
Discarding 11 places :
Symmetric choice reduction at 10 with 11 rule applications. Total rules 1116 place count 191 transition count 503
Iterating global reduction 10 with 11 rules applied. Total rules applied 1127 place count 191 transition count 503
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 10 with 21 rules applied. Total rules applied 1148 place count 191 transition count 482
Performed 2 Post agglomeration using F-continuation condition with reduction of 2 identical transitions.
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 11 with 4 rules applied. Total rules applied 1152 place count 189 transition count 503
Drop transitions removed 2 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 11 with 9 rules applied. Total rules applied 1161 place count 189 transition count 494
Drop transitions removed 48 transitions
Redundant transition composition rules discarded 48 transitions
Iterating global reduction 12 with 48 rules applied. Total rules applied 1209 place count 189 transition count 446
Discarding 4 places :
Symmetric choice reduction at 12 with 4 rule applications. Total rules 1213 place count 185 transition count 416
Iterating global reduction 12 with 4 rules applied. Total rules applied 1217 place count 185 transition count 416
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 12 with 4 rules applied. Total rules applied 1221 place count 185 transition count 412
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -23
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 13 with 4 rules applied. Total rules applied 1225 place count 183 transition count 435
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 13 with 1 rules applied. Total rules applied 1226 place count 183 transition count 434
Drop transitions removed 11 transitions
Redundant transition composition rules discarded 11 transitions
Iterating global reduction 14 with 11 rules applied. Total rules applied 1237 place count 183 transition count 423
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 14 with 2 rules applied. Total rules applied 1239 place count 182 transition count 434
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 14 with 2 rules applied. Total rules applied 1241 place count 182 transition count 432
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 15 with 9 rules applied. Total rules applied 1250 place count 182 transition count 423
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 15 with 2 rules applied. Total rules applied 1252 place count 181 transition count 436
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 15 with 1 rules applied. Total rules applied 1253 place count 181 transition count 435
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 16 with 10 rules applied. Total rules applied 1263 place count 181 transition count 425
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 16 with 2 rules applied. Total rules applied 1265 place count 180 transition count 436
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 16 with 2 rules applied. Total rules applied 1267 place count 180 transition count 434
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 17 with 9 rules applied. Total rules applied 1276 place count 180 transition count 425
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 17 with 2 rules applied. Total rules applied 1278 place count 179 transition count 438
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 17 with 2 rules applied. Total rules applied 1280 place count 179 transition count 436
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 18 with 10 rules applied. Total rules applied 1290 place count 179 transition count 426
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -9
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 18 with 2 rules applied. Total rules applied 1292 place count 178 transition count 435
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 18 with 1 rules applied. Total rules applied 1293 place count 178 transition count 434
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 19 with 9 rules applied. Total rules applied 1302 place count 178 transition count 425
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 19 with 2 rules applied. Total rules applied 1304 place count 177 transition count 436
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 19 with 2 rules applied. Total rules applied 1306 place count 177 transition count 434
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 20 with 9 rules applied. Total rules applied 1315 place count 177 transition count 425
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 20 with 2 rules applied. Total rules applied 1317 place count 176 transition count 438
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 20 with 2 rules applied. Total rules applied 1319 place count 176 transition count 436
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 21 with 10 rules applied. Total rules applied 1329 place count 176 transition count 426
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 21 with 2 rules applied. Total rules applied 1331 place count 175 transition count 437
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 21 with 2 rules applied. Total rules applied 1333 place count 175 transition count 435
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 22 with 9 rules applied. Total rules applied 1342 place count 175 transition count 426
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -13
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 22 with 2 rules applied. Total rules applied 1344 place count 174 transition count 439
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 22 with 2 rules applied. Total rules applied 1346 place count 174 transition count 437
Drop transitions removed 10 transitions
Redundant transition composition rules discarded 10 transitions
Iterating global reduction 23 with 10 rules applied. Total rules applied 1356 place count 174 transition count 427
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: -11
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 23 with 2 rules applied. Total rules applied 1358 place count 173 transition count 438
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 23 with 1 rules applied. Total rules applied 1359 place count 173 transition count 437
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 24 with 1 rules applied. Total rules applied 1360 place count 173 transition count 436
Free-agglomeration rule applied 70 times with reduction of 29 identical transitions.
Iterating global reduction 24 with 70 rules applied. Total rules applied 1430 place count 173 transition count 337
Reduce places removed 70 places and 0 transitions.
Drop transitions removed 97 transitions
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 99 transitions.
Iterating post reduction 24 with 169 rules applied. Total rules applied 1599 place count 103 transition count 238
Discarding 5 places :
Symmetric choice reduction at 25 with 5 rule applications. Total rules 1604 place count 98 transition count 232
Iterating global reduction 25 with 5 rules applied. Total rules applied 1609 place count 98 transition count 232
Drop transitions removed 36 transitions
Redundant transition composition rules discarded 36 transitions
Iterating global reduction 25 with 36 rules applied. Total rules applied 1645 place count 98 transition count 196
Discarding 6 places :
Symmetric choice reduction at 25 with 6 rule applications. Total rules 1651 place count 92 transition count 188
Iterating global reduction 25 with 6 rules applied. Total rules applied 1657 place count 92 transition count 188
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 25 with 1 rules applied. Total rules applied 1658 place count 92 transition count 200
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 25 with 11 rules applied. Total rules applied 1669 place count 91 transition count 190
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 26 with 9 rules applied. Total rules applied 1678 place count 91 transition count 181
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 26 with 1 rules applied. Total rules applied 1679 place count 91 transition count 181
Applied a total of 1679 rules in 371 ms. Remains 91 /940 variables (removed 849) and now considering 181/1424 (removed 1243) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 371 ms. Remains : 91/940 places, 181/1424 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 5) seen :4
Finished Best-First random walk after 2664 steps, including 0 resets, run visited all 1 properties in 3 ms. (steps per millisecond=888 )
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 10:15:21] [INFO ] Flatten gal took : 45 ms
[2023-03-08 10:15:21] [INFO ] Flatten gal took : 47 ms
[2023-03-08 10:15:21] [INFO ] Input system was already deterministic with 1424 transitions.
Computed a total of 125 stabilizing places and 125 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 51 places :
Symmetric choice reduction at 0 with 51 rule applications. Total rules 51 place count 889 transition count 1367
Iterating global reduction 0 with 51 rules applied. Total rules applied 102 place count 889 transition count 1367
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 131 place count 860 transition count 1336
Iterating global reduction 0 with 29 rules applied. Total rules applied 160 place count 860 transition count 1336
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 175 place count 845 transition count 1315
Iterating global reduction 0 with 15 rules applied. Total rules applied 190 place count 845 transition count 1315
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 192 place count 845 transition count 1313
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 202 place count 835 transition count 1303
Iterating global reduction 1 with 10 rules applied. Total rules applied 212 place count 835 transition count 1303
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 220 place count 827 transition count 1295
Iterating global reduction 1 with 8 rules applied. Total rules applied 228 place count 827 transition count 1295
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 234 place count 821 transition count 1289
Iterating global reduction 1 with 6 rules applied. Total rules applied 240 place count 821 transition count 1289
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 244 place count 817 transition count 1285
Iterating global reduction 1 with 4 rules applied. Total rules applied 248 place count 817 transition count 1285
Applied a total of 248 rules in 138 ms. Remains 817 /940 variables (removed 123) and now considering 1285/1424 (removed 139) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 138 ms. Remains : 817/940 places, 1285/1424 transitions.
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 34 ms
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 34 ms
[2023-03-08 10:15:22] [INFO ] Input system was already deterministic with 1285 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 882 edges and 940 vertex of which 263 / 940 are part of one of the 19 SCC in 2 ms
Free SCC test removed 244 places
Ensure Unique test removed 262 transitions
Reduce isomorphic transitions removed 262 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 198 transitions
Trivial Post-agglo rules discarded 198 transitions
Performed 198 trivial Post agglomeration. Transition count delta: 198
Iterating post reduction 0 with 198 rules applied. Total rules applied 199 place count 695 transition count 963
Reduce places removed 198 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 18 transitions
Trivial Post-agglo rules discarded 18 transitions
Performed 18 trivial Post agglomeration. Transition count delta: 18
Iterating post reduction 1 with 226 rules applied. Total rules applied 425 place count 497 transition count 935
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 22 rules applied. Total rules applied 447 place count 479 transition count 931
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 4 rules applied. Total rules applied 451 place count 477 transition count 929
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 453 place count 475 transition count 929
Performed 51 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 51 Pre rules applied. Total rules applied 453 place count 475 transition count 878
Deduced a syphon composed of 51 places in 2 ms
Reduce places removed 51 places and 0 transitions.
Iterating global reduction 5 with 102 rules applied. Total rules applied 555 place count 424 transition count 878
Discarding 55 places :
Symmetric choice reduction at 5 with 55 rule applications. Total rules 610 place count 369 transition count 733
Iterating global reduction 5 with 55 rules applied. Total rules applied 665 place count 369 transition count 733
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 667 place count 369 transition count 731
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 15 Pre rules applied. Total rules applied 667 place count 369 transition count 716
Deduced a syphon composed of 15 places in 3 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 6 with 30 rules applied. Total rules applied 697 place count 354 transition count 716
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 698 place count 353 transition count 709
Iterating global reduction 6 with 1 rules applied. Total rules applied 699 place count 353 transition count 709
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 700 place count 353 transition count 708
Performed 106 Post agglomeration using F-continuation condition.Transition count delta: 106
Deduced a syphon composed of 106 places in 0 ms
Reduce places removed 106 places and 0 transitions.
Iterating global reduction 7 with 212 rules applied. Total rules applied 912 place count 247 transition count 602
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 913 place count 247 transition count 601
Discarding 15 places :
Symmetric choice reduction at 8 with 15 rule applications. Total rules 928 place count 232 transition count 514
Iterating global reduction 8 with 15 rules applied. Total rules applied 943 place count 232 transition count 514
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 8 with 11 rules applied. Total rules applied 954 place count 232 transition count 503
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 956 place count 231 transition count 502
Drop transitions removed 7 transitions
Redundant transition composition rules discarded 7 transitions
Iterating global reduction 9 with 7 rules applied. Total rules applied 963 place count 231 transition count 495
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 9 with 4 rules applied. Total rules applied 967 place count 231 transition count 491
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 10 with 4 rules applied. Total rules applied 971 place count 227 transition count 491
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 973 place count 225 transition count 489
Applied a total of 973 rules in 112 ms. Remains 225 /940 variables (removed 715) and now considering 489/1424 (removed 935) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 112 ms. Remains : 225/940 places, 489/1424 transitions.
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 15 ms
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 16 ms
[2023-03-08 10:15:22] [INFO ] Input system was already deterministic with 489 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 51 places :
Symmetric choice reduction at 0 with 51 rule applications. Total rules 51 place count 889 transition count 1367
Iterating global reduction 0 with 51 rules applied. Total rules applied 102 place count 889 transition count 1367
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 131 place count 860 transition count 1336
Iterating global reduction 0 with 29 rules applied. Total rules applied 160 place count 860 transition count 1336
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 175 place count 845 transition count 1315
Iterating global reduction 0 with 15 rules applied. Total rules applied 190 place count 845 transition count 1315
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 192 place count 845 transition count 1313
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 202 place count 835 transition count 1303
Iterating global reduction 1 with 10 rules applied. Total rules applied 212 place count 835 transition count 1303
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 220 place count 827 transition count 1295
Iterating global reduction 1 with 8 rules applied. Total rules applied 228 place count 827 transition count 1295
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 234 place count 821 transition count 1289
Iterating global reduction 1 with 6 rules applied. Total rules applied 240 place count 821 transition count 1289
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 244 place count 817 transition count 1285
Iterating global reduction 1 with 4 rules applied. Total rules applied 248 place count 817 transition count 1285
Applied a total of 248 rules in 147 ms. Remains 817 /940 variables (removed 123) and now considering 1285/1424 (removed 139) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 148 ms. Remains : 817/940 places, 1285/1424 transitions.
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 31 ms
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 37 ms
[2023-03-08 10:15:22] [INFO ] Input system was already deterministic with 1285 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 896 transition count 1380
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 896 transition count 1380
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 111 place count 873 transition count 1355
Iterating global reduction 0 with 23 rules applied. Total rules applied 134 place count 873 transition count 1355
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 146 place count 861 transition count 1337
Iterating global reduction 0 with 12 rules applied. Total rules applied 158 place count 861 transition count 1337
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 160 place count 861 transition count 1335
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 167 place count 854 transition count 1328
Iterating global reduction 1 with 7 rules applied. Total rules applied 174 place count 854 transition count 1328
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 179 place count 849 transition count 1323
Iterating global reduction 1 with 5 rules applied. Total rules applied 184 place count 849 transition count 1323
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 187 place count 846 transition count 1320
Iterating global reduction 1 with 3 rules applied. Total rules applied 190 place count 846 transition count 1320
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 192 place count 844 transition count 1318
Iterating global reduction 1 with 2 rules applied. Total rules applied 194 place count 844 transition count 1318
Applied a total of 194 rules in 117 ms. Remains 844 /940 variables (removed 96) and now considering 1318/1424 (removed 106) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 117 ms. Remains : 844/940 places, 1318/1424 transitions.
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 29 ms
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 29 ms
[2023-03-08 10:15:22] [INFO ] Input system was already deterministic with 1318 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 884 edges and 940 vertex of which 235 / 940 are part of one of the 20 SCC in 1 ms
Free SCC test removed 215 places
Ensure Unique test removed 229 transitions
Reduce isomorphic transitions removed 229 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 214 transitions
Trivial Post-agglo rules discarded 214 transitions
Performed 214 trivial Post agglomeration. Transition count delta: 214
Iterating post reduction 0 with 214 rules applied. Total rules applied 215 place count 724 transition count 980
Reduce places removed 214 places and 0 transitions.
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 1 with 240 rules applied. Total rules applied 455 place count 510 transition count 954
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 19 rules applied. Total rules applied 474 place count 493 transition count 952
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 475 place count 492 transition count 952
Performed 55 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 55 Pre rules applied. Total rules applied 475 place count 492 transition count 897
Deduced a syphon composed of 55 places in 0 ms
Reduce places removed 55 places and 0 transitions.
Iterating global reduction 4 with 110 rules applied. Total rules applied 585 place count 437 transition count 897
Discarding 50 places :
Symmetric choice reduction at 4 with 50 rule applications. Total rules 635 place count 387 transition count 763
Iterating global reduction 4 with 50 rules applied. Total rules applied 685 place count 387 transition count 763
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 687 place count 387 transition count 761
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 16 Pre rules applied. Total rules applied 687 place count 387 transition count 745
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 5 with 32 rules applied. Total rules applied 719 place count 371 transition count 745
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 720 place count 370 transition count 738
Iterating global reduction 5 with 1 rules applied. Total rules applied 721 place count 370 transition count 738
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 722 place count 370 transition count 737
Performed 116 Post agglomeration using F-continuation condition.Transition count delta: 116
Deduced a syphon composed of 116 places in 0 ms
Reduce places removed 116 places and 0 transitions.
Iterating global reduction 6 with 232 rules applied. Total rules applied 954 place count 254 transition count 621
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 957 place count 254 transition count 618
Discarding 14 places :
Symmetric choice reduction at 7 with 14 rule applications. Total rules 971 place count 240 transition count 535
Iterating global reduction 7 with 14 rules applied. Total rules applied 985 place count 240 transition count 535
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 7 with 10 rules applied. Total rules applied 995 place count 240 transition count 525
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 8 with 6 rules applied. Total rules applied 1001 place count 237 transition count 522
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 8 with 8 rules applied. Total rules applied 1009 place count 237 transition count 514
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 8 with 4 rules applied. Total rules applied 1013 place count 237 transition count 510
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 9 with 4 rules applied. Total rules applied 1017 place count 233 transition count 510
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 1017 place count 233 transition count 509
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1019 place count 232 transition count 509
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1021 place count 230 transition count 507
Applied a total of 1021 rules in 79 ms. Remains 230 /940 variables (removed 710) and now considering 507/1424 (removed 917) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 80 ms. Remains : 230/940 places, 507/1424 transitions.
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 12 ms
[2023-03-08 10:15:22] [INFO ] Flatten gal took : 13 ms
[2023-03-08 10:15:22] [INFO ] Input system was already deterministic with 507 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 880 edges and 940 vertex of which 244 / 940 are part of one of the 21 SCC in 1 ms
Free SCC test removed 223 places
Ensure Unique test removed 238 transitions
Reduce isomorphic transitions removed 238 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 210 transitions
Trivial Post-agglo rules discarded 210 transitions
Performed 210 trivial Post agglomeration. Transition count delta: 210
Iterating post reduction 0 with 210 rules applied. Total rules applied 211 place count 716 transition count 975
Reduce places removed 210 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 1 with 237 rules applied. Total rules applied 448 place count 506 transition count 948
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 21 rules applied. Total rules applied 469 place count 489 transition count 944
Reduce places removed 2 places and 0 transitions.
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 3 with 5 rules applied. Total rules applied 474 place count 487 transition count 941
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 477 place count 484 transition count 941
Performed 52 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 52 Pre rules applied. Total rules applied 477 place count 484 transition count 889
Deduced a syphon composed of 52 places in 1 ms
Reduce places removed 52 places and 0 transitions.
Iterating global reduction 5 with 104 rules applied. Total rules applied 581 place count 432 transition count 889
Discarding 53 places :
Symmetric choice reduction at 5 with 53 rule applications. Total rules 634 place count 379 transition count 752
Iterating global reduction 5 with 53 rules applied. Total rules applied 687 place count 379 transition count 752
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 689 place count 379 transition count 750
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 16 Pre rules applied. Total rules applied 689 place count 379 transition count 734
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 6 with 32 rules applied. Total rules applied 721 place count 363 transition count 734
Performed 110 Post agglomeration using F-continuation condition.Transition count delta: 110
Deduced a syphon composed of 110 places in 0 ms
Reduce places removed 110 places and 0 transitions.
Iterating global reduction 6 with 220 rules applied. Total rules applied 941 place count 253 transition count 624
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 6 with 2 rules applied. Total rules applied 943 place count 253 transition count 622
Discarding 17 places :
Symmetric choice reduction at 7 with 17 rule applications. Total rules 960 place count 236 transition count 521
Iterating global reduction 7 with 17 rules applied. Total rules applied 977 place count 236 transition count 521
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 7 with 11 rules applied. Total rules applied 988 place count 236 transition count 510
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 8 with 4 rules applied. Total rules applied 992 place count 234 transition count 508
Drop transitions removed 9 transitions
Redundant transition composition rules discarded 9 transitions
Iterating global reduction 8 with 9 rules applied. Total rules applied 1001 place count 234 transition count 499
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 8 with 4 rules applied. Total rules applied 1005 place count 234 transition count 495
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 9 with 4 rules applied. Total rules applied 1009 place count 230 transition count 495
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 10 with 1 rules applied. Total rules applied 1010 place count 230 transition count 495
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1012 place count 228 transition count 493
Applied a total of 1012 rules in 75 ms. Remains 228 /940 variables (removed 712) and now considering 493/1424 (removed 931) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 75 ms. Remains : 228/940 places, 493/1424 transitions.
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 12 ms
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 13 ms
[2023-03-08 10:15:23] [INFO ] Input system was already deterministic with 493 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 49 places :
Symmetric choice reduction at 0 with 49 rule applications. Total rules 49 place count 891 transition count 1369
Iterating global reduction 0 with 49 rules applied. Total rules applied 98 place count 891 transition count 1369
Discarding 27 places :
Symmetric choice reduction at 0 with 27 rule applications. Total rules 125 place count 864 transition count 1340
Iterating global reduction 0 with 27 rules applied. Total rules applied 152 place count 864 transition count 1340
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 165 place count 851 transition count 1321
Iterating global reduction 0 with 13 rules applied. Total rules applied 178 place count 851 transition count 1321
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 180 place count 851 transition count 1319
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 189 place count 842 transition count 1310
Iterating global reduction 1 with 9 rules applied. Total rules applied 198 place count 842 transition count 1310
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 206 place count 834 transition count 1302
Iterating global reduction 1 with 8 rules applied. Total rules applied 214 place count 834 transition count 1302
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 219 place count 829 transition count 1297
Iterating global reduction 1 with 5 rules applied. Total rules applied 224 place count 829 transition count 1297
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 228 place count 825 transition count 1293
Iterating global reduction 1 with 4 rules applied. Total rules applied 232 place count 825 transition count 1293
Applied a total of 232 rules in 120 ms. Remains 825 /940 variables (removed 115) and now considering 1293/1424 (removed 131) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 120 ms. Remains : 825/940 places, 1293/1424 transitions.
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 26 ms
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 28 ms
[2023-03-08 10:15:23] [INFO ] Input system was already deterministic with 1293 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 893 edges and 940 vertex of which 270 / 940 are part of one of the 20 SCC in 1 ms
Free SCC test removed 250 places
Ensure Unique test removed 269 transitions
Reduce isomorphic transitions removed 269 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 198 transitions
Trivial Post-agglo rules discarded 198 transitions
Performed 198 trivial Post agglomeration. Transition count delta: 198
Iterating post reduction 0 with 198 rules applied. Total rules applied 199 place count 689 transition count 956
Reduce places removed 198 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 18 transitions
Trivial Post-agglo rules discarded 18 transitions
Performed 18 trivial Post agglomeration. Transition count delta: 18
Iterating post reduction 1 with 226 rules applied. Total rules applied 425 place count 491 transition count 928
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 22 rules applied. Total rules applied 447 place count 473 transition count 924
Reduce places removed 2 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 3 rules applied. Total rules applied 450 place count 471 transition count 923
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 451 place count 470 transition count 923
Performed 50 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 50 Pre rules applied. Total rules applied 451 place count 470 transition count 873
Deduced a syphon composed of 50 places in 1 ms
Reduce places removed 50 places and 0 transitions.
Iterating global reduction 5 with 100 rules applied. Total rules applied 551 place count 420 transition count 873
Discarding 58 places :
Symmetric choice reduction at 5 with 58 rule applications. Total rules 609 place count 362 transition count 719
Iterating global reduction 5 with 58 rules applied. Total rules applied 667 place count 362 transition count 719
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 669 place count 362 transition count 717
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 17 Pre rules applied. Total rules applied 669 place count 362 transition count 700
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 703 place count 345 transition count 700
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 704 place count 344 transition count 693
Iterating global reduction 6 with 1 rules applied. Total rules applied 705 place count 344 transition count 693
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 706 place count 344 transition count 692
Performed 107 Post agglomeration using F-continuation condition.Transition count delta: 107
Deduced a syphon composed of 107 places in 0 ms
Reduce places removed 107 places and 0 transitions.
Iterating global reduction 7 with 214 rules applied. Total rules applied 920 place count 237 transition count 585
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 921 place count 237 transition count 584
Discarding 16 places :
Symmetric choice reduction at 8 with 16 rule applications. Total rules 937 place count 221 transition count 490
Iterating global reduction 8 with 16 rules applied. Total rules applied 953 place count 221 transition count 490
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 8 with 13 rules applied. Total rules applied 966 place count 221 transition count 477
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 968 place count 220 transition count 476
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 9 with 8 rules applied. Total rules applied 976 place count 220 transition count 468
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 9 with 4 rules applied. Total rules applied 980 place count 220 transition count 464
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 10 with 4 rules applied. Total rules applied 984 place count 216 transition count 464
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 986 place count 214 transition count 462
Applied a total of 986 rules in 76 ms. Remains 214 /940 variables (removed 726) and now considering 462/1424 (removed 962) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 76 ms. Remains : 214/940 places, 462/1424 transitions.
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 10 ms
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:15:23] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 48 places :
Symmetric choice reduction at 0 with 48 rule applications. Total rules 48 place count 892 transition count 1370
Iterating global reduction 0 with 48 rules applied. Total rules applied 96 place count 892 transition count 1370
Discarding 28 places :
Symmetric choice reduction at 0 with 28 rule applications. Total rules 124 place count 864 transition count 1340
Iterating global reduction 0 with 28 rules applied. Total rules applied 152 place count 864 transition count 1340
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 166 place count 850 transition count 1320
Iterating global reduction 0 with 14 rules applied. Total rules applied 180 place count 850 transition count 1320
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 182 place count 850 transition count 1318
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 191 place count 841 transition count 1309
Iterating global reduction 1 with 9 rules applied. Total rules applied 200 place count 841 transition count 1309
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 207 place count 834 transition count 1302
Iterating global reduction 1 with 7 rules applied. Total rules applied 214 place count 834 transition count 1302
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 220 place count 828 transition count 1296
Iterating global reduction 1 with 6 rules applied. Total rules applied 226 place count 828 transition count 1296
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 230 place count 824 transition count 1292
Iterating global reduction 1 with 4 rules applied. Total rules applied 234 place count 824 transition count 1292
Applied a total of 234 rules in 127 ms. Remains 824 /940 variables (removed 116) and now considering 1292/1424 (removed 132) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 128 ms. Remains : 824/940 places, 1292/1424 transitions.
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 27 ms
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 28 ms
[2023-03-08 10:15:23] [INFO ] Input system was already deterministic with 1292 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 44 places :
Symmetric choice reduction at 0 with 44 rule applications. Total rules 44 place count 896 transition count 1374
Iterating global reduction 0 with 44 rules applied. Total rules applied 88 place count 896 transition count 1374
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 114 place count 870 transition count 1346
Iterating global reduction 0 with 26 rules applied. Total rules applied 140 place count 870 transition count 1346
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 152 place count 858 transition count 1334
Iterating global reduction 0 with 12 rules applied. Total rules applied 164 place count 858 transition count 1334
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 166 place count 858 transition count 1332
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 175 place count 849 transition count 1323
Iterating global reduction 1 with 9 rules applied. Total rules applied 184 place count 849 transition count 1323
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 192 place count 841 transition count 1315
Iterating global reduction 1 with 8 rules applied. Total rules applied 200 place count 841 transition count 1315
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 206 place count 835 transition count 1309
Iterating global reduction 1 with 6 rules applied. Total rules applied 212 place count 835 transition count 1309
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 216 place count 831 transition count 1305
Iterating global reduction 1 with 4 rules applied. Total rules applied 220 place count 831 transition count 1305
Applied a total of 220 rules in 128 ms. Remains 831 /940 variables (removed 109) and now considering 1305/1424 (removed 119) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 129 ms. Remains : 831/940 places, 1305/1424 transitions.
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 26 ms
[2023-03-08 10:15:23] [INFO ] Flatten gal took : 28 ms
[2023-03-08 10:15:23] [INFO ] Input system was already deterministic with 1305 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 893 edges and 940 vertex of which 270 / 940 are part of one of the 20 SCC in 1 ms
Free SCC test removed 250 places
Ensure Unique test removed 269 transitions
Reduce isomorphic transitions removed 269 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 201 transitions
Trivial Post-agglo rules discarded 201 transitions
Performed 201 trivial Post agglomeration. Transition count delta: 201
Iterating post reduction 0 with 201 rules applied. Total rules applied 202 place count 689 transition count 953
Reduce places removed 201 places and 0 transitions.
Ensure Unique test removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Drop transitions removed 18 transitions
Trivial Post-agglo rules discarded 18 transitions
Performed 18 trivial Post agglomeration. Transition count delta: 18
Iterating post reduction 1 with 229 rules applied. Total rules applied 431 place count 488 transition count 925
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 2 with 22 rules applied. Total rules applied 453 place count 470 transition count 921
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 455 place count 468 transition count 921
Performed 50 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 50 Pre rules applied. Total rules applied 455 place count 468 transition count 871
Deduced a syphon composed of 50 places in 1 ms
Reduce places removed 50 places and 0 transitions.
Iterating global reduction 4 with 100 rules applied. Total rules applied 555 place count 418 transition count 871
Discarding 58 places :
Symmetric choice reduction at 4 with 58 rule applications. Total rules 613 place count 360 transition count 717
Iterating global reduction 4 with 58 rules applied. Total rules applied 671 place count 360 transition count 717
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 673 place count 360 transition count 715
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 17 Pre rules applied. Total rules applied 673 place count 360 transition count 698
Deduced a syphon composed of 17 places in 1 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 5 with 34 rules applied. Total rules applied 707 place count 343 transition count 698
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 708 place count 342 transition count 691
Iterating global reduction 5 with 1 rules applied. Total rules applied 709 place count 342 transition count 691
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 710 place count 342 transition count 690
Performed 107 Post agglomeration using F-continuation condition.Transition count delta: 107
Deduced a syphon composed of 107 places in 0 ms
Reduce places removed 107 places and 0 transitions.
Iterating global reduction 6 with 214 rules applied. Total rules applied 924 place count 235 transition count 583
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 925 place count 235 transition count 582
Discarding 16 places :
Symmetric choice reduction at 7 with 16 rule applications. Total rules 941 place count 219 transition count 488
Iterating global reduction 7 with 16 rules applied. Total rules applied 957 place count 219 transition count 488
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 7 with 13 rules applied. Total rules applied 970 place count 219 transition count 475
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 8 with 2 rules applied. Total rules applied 972 place count 218 transition count 474
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 8 with 8 rules applied. Total rules applied 980 place count 218 transition count 466
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 8 with 4 rules applied. Total rules applied 984 place count 218 transition count 462
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 9 with 4 rules applied. Total rules applied 988 place count 214 transition count 462
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 990 place count 212 transition count 460
Applied a total of 990 rules in 66 ms. Remains 212 /940 variables (removed 728) and now considering 460/1424 (removed 964) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 67 ms. Remains : 212/940 places, 460/1424 transitions.
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 9 ms
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:15:24] [INFO ] Input system was already deterministic with 460 transitions.
Finished random walk after 448 steps, including 0 resets, run visited all 1 properties in 6 ms. (steps per millisecond=74 )
FORMULA DLCround-PT-03b-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Graph (trivial) has 880 edges and 940 vertex of which 270 / 940 are part of one of the 20 SCC in 0 ms
Free SCC test removed 250 places
Ensure Unique test removed 269 transitions
Reduce isomorphic transitions removed 269 transitions.
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 191 transitions
Trivial Post-agglo rules discarded 191 transitions
Performed 191 trivial Post agglomeration. Transition count delta: 191
Iterating post reduction 0 with 191 rules applied. Total rules applied 192 place count 689 transition count 963
Reduce places removed 191 places and 0 transitions.
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 1 with 217 rules applied. Total rules applied 409 place count 498 transition count 937
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 19 rules applied. Total rules applied 428 place count 481 transition count 935
Reduce places removed 1 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 3 with 3 rules applied. Total rules applied 431 place count 480 transition count 933
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 4 with 2 rules applied. Total rules applied 433 place count 478 transition count 933
Performed 52 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 52 Pre rules applied. Total rules applied 433 place count 478 transition count 881
Deduced a syphon composed of 52 places in 1 ms
Reduce places removed 52 places and 0 transitions.
Iterating global reduction 5 with 104 rules applied. Total rules applied 537 place count 426 transition count 881
Discarding 54 places :
Symmetric choice reduction at 5 with 54 rule applications. Total rules 591 place count 372 transition count 737
Iterating global reduction 5 with 54 rules applied. Total rules applied 645 place count 372 transition count 737
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 647 place count 372 transition count 735
Performed 16 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 16 Pre rules applied. Total rules applied 647 place count 372 transition count 719
Deduced a syphon composed of 16 places in 1 ms
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 6 with 32 rules applied. Total rules applied 679 place count 356 transition count 719
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 680 place count 355 transition count 712
Iterating global reduction 6 with 1 rules applied. Total rules applied 681 place count 355 transition count 712
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 682 place count 355 transition count 711
Performed 106 Post agglomeration using F-continuation condition.Transition count delta: 106
Deduced a syphon composed of 106 places in 0 ms
Reduce places removed 106 places and 0 transitions.
Iterating global reduction 7 with 212 rules applied. Total rules applied 894 place count 249 transition count 605
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 895 place count 249 transition count 604
Discarding 15 places :
Symmetric choice reduction at 8 with 15 rule applications. Total rules 910 place count 234 transition count 514
Iterating global reduction 8 with 15 rules applied. Total rules applied 925 place count 234 transition count 514
Ensure Unique test removed 12 transitions
Reduce isomorphic transitions removed 12 transitions.
Iterating post reduction 8 with 12 rules applied. Total rules applied 937 place count 234 transition count 502
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 939 place count 233 transition count 501
Drop transitions removed 8 transitions
Redundant transition composition rules discarded 8 transitions
Iterating global reduction 9 with 8 rules applied. Total rules applied 947 place count 233 transition count 493
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 9 with 4 rules applied. Total rules applied 951 place count 233 transition count 489
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 10 with 4 rules applied. Total rules applied 955 place count 229 transition count 489
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 11 with 1 Pre rules applied. Total rules applied 955 place count 229 transition count 488
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 957 place count 228 transition count 488
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 11 with 2 rules applied. Total rules applied 959 place count 226 transition count 486
Applied a total of 959 rules in 71 ms. Remains 226 /940 variables (removed 714) and now considering 486/1424 (removed 938) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 71 ms. Remains : 226/940 places, 486/1424 transitions.
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 11 ms
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 12 ms
[2023-03-08 10:15:24] [INFO ] Input system was already deterministic with 486 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 51 places :
Symmetric choice reduction at 0 with 51 rule applications. Total rules 51 place count 889 transition count 1367
Iterating global reduction 0 with 51 rules applied. Total rules applied 102 place count 889 transition count 1367
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 132 place count 859 transition count 1335
Iterating global reduction 0 with 30 rules applied. Total rules applied 162 place count 859 transition count 1335
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 177 place count 844 transition count 1314
Iterating global reduction 0 with 15 rules applied. Total rules applied 192 place count 844 transition count 1314
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 194 place count 844 transition count 1312
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 204 place count 834 transition count 1302
Iterating global reduction 1 with 10 rules applied. Total rules applied 214 place count 834 transition count 1302
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 222 place count 826 transition count 1294
Iterating global reduction 1 with 8 rules applied. Total rules applied 230 place count 826 transition count 1294
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 236 place count 820 transition count 1288
Iterating global reduction 1 with 6 rules applied. Total rules applied 242 place count 820 transition count 1288
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 246 place count 816 transition count 1284
Iterating global reduction 1 with 4 rules applied. Total rules applied 250 place count 816 transition count 1284
Applied a total of 250 rules in 135 ms. Remains 816 /940 variables (removed 124) and now considering 1284/1424 (removed 140) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 135 ms. Remains : 816/940 places, 1284/1424 transitions.
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 25 ms
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 27 ms
[2023-03-08 10:15:24] [INFO ] Input system was already deterministic with 1284 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 45 places :
Symmetric choice reduction at 0 with 45 rule applications. Total rules 45 place count 895 transition count 1373
Iterating global reduction 0 with 45 rules applied. Total rules applied 90 place count 895 transition count 1373
Discarding 26 places :
Symmetric choice reduction at 0 with 26 rule applications. Total rules 116 place count 869 transition count 1345
Iterating global reduction 0 with 26 rules applied. Total rules applied 142 place count 869 transition count 1345
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 156 place count 855 transition count 1325
Iterating global reduction 0 with 14 rules applied. Total rules applied 170 place count 855 transition count 1325
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 172 place count 855 transition count 1323
Discarding 9 places :
Symmetric choice reduction at 1 with 9 rule applications. Total rules 181 place count 846 transition count 1314
Iterating global reduction 1 with 9 rules applied. Total rules applied 190 place count 846 transition count 1314
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 197 place count 839 transition count 1307
Iterating global reduction 1 with 7 rules applied. Total rules applied 204 place count 839 transition count 1307
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 209 place count 834 transition count 1302
Iterating global reduction 1 with 5 rules applied. Total rules applied 214 place count 834 transition count 1302
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 217 place count 831 transition count 1299
Iterating global reduction 1 with 3 rules applied. Total rules applied 220 place count 831 transition count 1299
Applied a total of 220 rules in 139 ms. Remains 831 /940 variables (removed 109) and now considering 1299/1424 (removed 125) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 140 ms. Remains : 831/940 places, 1299/1424 transitions.
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 25 ms
[2023-03-08 10:15:24] [INFO ] Input system was already deterministic with 1299 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 50 places :
Symmetric choice reduction at 0 with 50 rule applications. Total rules 50 place count 890 transition count 1368
Iterating global reduction 0 with 50 rules applied. Total rules applied 100 place count 890 transition count 1368
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 130 place count 860 transition count 1336
Iterating global reduction 0 with 30 rules applied. Total rules applied 160 place count 860 transition count 1336
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 175 place count 845 transition count 1315
Iterating global reduction 0 with 15 rules applied. Total rules applied 190 place count 845 transition count 1315
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 192 place count 845 transition count 1313
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 202 place count 835 transition count 1303
Iterating global reduction 1 with 10 rules applied. Total rules applied 212 place count 835 transition count 1303
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 220 place count 827 transition count 1295
Iterating global reduction 1 with 8 rules applied. Total rules applied 228 place count 827 transition count 1295
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 234 place count 821 transition count 1289
Iterating global reduction 1 with 6 rules applied. Total rules applied 240 place count 821 transition count 1289
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 244 place count 817 transition count 1285
Iterating global reduction 1 with 4 rules applied. Total rules applied 248 place count 817 transition count 1285
Applied a total of 248 rules in 137 ms. Remains 817 /940 variables (removed 123) and now considering 1285/1424 (removed 139) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 137 ms. Remains : 817/940 places, 1285/1424 transitions.
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:15:24] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:15:24] [INFO ] Input system was already deterministic with 1285 transitions.
Starting structural reductions in LTL mode, iteration 0 : 940/940 places, 1424/1424 transitions.
Discarding 50 places :
Symmetric choice reduction at 0 with 50 rule applications. Total rules 50 place count 890 transition count 1368
Iterating global reduction 0 with 50 rules applied. Total rules applied 100 place count 890 transition count 1368
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 129 place count 861 transition count 1337
Iterating global reduction 0 with 29 rules applied. Total rules applied 158 place count 861 transition count 1337
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 173 place count 846 transition count 1316
Iterating global reduction 0 with 15 rules applied. Total rules applied 188 place count 846 transition count 1316
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 190 place count 846 transition count 1314
Discarding 10 places :
Symmetric choice reduction at 1 with 10 rule applications. Total rules 200 place count 836 transition count 1304
Iterating global reduction 1 with 10 rules applied. Total rules applied 210 place count 836 transition count 1304
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 218 place count 828 transition count 1296
Iterating global reduction 1 with 8 rules applied. Total rules applied 226 place count 828 transition count 1296
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 232 place count 822 transition count 1290
Iterating global reduction 1 with 6 rules applied. Total rules applied 238 place count 822 transition count 1290
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 242 place count 818 transition count 1286
Iterating global reduction 1 with 4 rules applied. Total rules applied 246 place count 818 transition count 1286
Applied a total of 246 rules in 135 ms. Remains 818 /940 variables (removed 122) and now considering 1286/1424 (removed 138) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 136 ms. Remains : 818/940 places, 1286/1424 transitions.
[2023-03-08 10:15:25] [INFO ] Flatten gal took : 22 ms
[2023-03-08 10:15:25] [INFO ] Flatten gal took : 23 ms
[2023-03-08 10:15:25] [INFO ] Input system was already deterministic with 1286 transitions.
[2023-03-08 10:15:25] [INFO ] Flatten gal took : 24 ms
[2023-03-08 10:15:25] [INFO ] Flatten gal took : 25 ms
[2023-03-08 10:15:25] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 10:15:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 940 places, 1424 transitions and 3855 arcs took 5 ms.
Total runtime 11990 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCround-PT-03b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA DLCround-PT-03b-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCround-PT-03b-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678270753906

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 61 (type EXCL) for 21 DLCround-PT-03b-CTLFireability-07
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 61 (type EXCL) for DLCround-PT-03b-CTLFireability-07
lola: result : true
lola: markings : 46
lola: fired transitions : 46
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 51 DLCround-PT-03b-CTLFireability-14
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for DLCround-PT-03b-CTLFireability-14
lola: result : true
lola: markings : 46
lola: fired transitions : 46
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 DLCround-PT-03b-CTLFireability-05
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 16 (type EXCL) for DLCround-PT-03b-CTLFireability-05
lola: result : false
lola: markings : 8
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-03b-CTLFireability-02
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:755
lola: rewrite Frontend/Parser/formula_rewrite.k:690
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 4/239 5/32 DLCround-PT-03b-CTLFireability-02 692243 m, 138448 m/sec, 719516 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 9/239 10/32 DLCround-PT-03b-CTLFireability-02 1509412 m, 163433 m/sec, 1571027 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 14/239 14/32 DLCround-PT-03b-CTLFireability-02 2312908 m, 160699 m/sec, 2412595 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 19/239 19/32 DLCround-PT-03b-CTLFireability-02 3120606 m, 161539 m/sec, 3261296 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 24/239 23/32 DLCround-PT-03b-CTLFireability-02 3925878 m, 161054 m/sec, 4108779 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-03b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-08: CONJ 0 4 0 0 4 0 0 0
DLCround-PT-03b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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7 CTL EXCL 29/239 28/32 DLCround-PT-03b-CTLFireability-02 4732076 m, 161239 m/sec, 4952262 t fired, .

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40 CTL EXCL 5/350 6/32 DLCround-PT-03b-CTLFireability-09 737286 m, 147457 m/sec, 794797 t fired, .

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DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/1144 4/32 DLCround-PT-03b-CTLFireability-11 630558 m, 126111 m/sec, 2990579 t fired, .

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DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/1144 6/32 DLCround-PT-03b-CTLFireability-11 1242127 m, 122313 m/sec, 5906474 t fired, .

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DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/1144 9/32 DLCround-PT-03b-CTLFireability-11 1848691 m, 121312 m/sec, 8818857 t fired, .

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DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
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DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/1144 12/32 DLCround-PT-03b-CTLFireability-11 2449696 m, 120201 m/sec, 11739000 t fired, .

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DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/1144 14/32 DLCround-PT-03b-CTLFireability-11 3044794 m, 119019 m/sec, 14660239 t fired, .

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DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/1144 17/32 DLCround-PT-03b-CTLFireability-11 3632921 m, 117625 m/sec, 17567921 t fired, .

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DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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43 CTL EXCL 35/1144 20/32 DLCround-PT-03b-CTLFireability-11 4216087 m, 116633 m/sec, 20459240 t fired, .

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DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

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DLCround-PT-03b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/1144 23/32 DLCround-PT-03b-CTLFireability-11 4792380 m, 115258 m/sec, 23339679 t fired, .

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DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/1144 25/32 DLCround-PT-03b-CTLFireability-11 5366926 m, 114909 m/sec, 26215808 t fired, .

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DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

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DLCround-PT-03b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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43 CTL EXCL 50/1144 28/32 DLCround-PT-03b-CTLFireability-11 5936217 m, 113858 m/sec, 29084280 t fired, .

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DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

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DLCround-PT-03b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-03b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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DLCround-PT-03b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 55/1144 31/32 DLCround-PT-03b-CTLFireability-11 6503268 m, 113410 m/sec, 31943765 t fired, .

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DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG

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DLCround-PT-03b-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-03b-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for DLCround-PT-03b-CTLFireability-01
lola: result : true
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lola: result : false
lola: markings : 132
lola: fired transitions : 185
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-03b-CTLFireability-00: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-01: CTL true CTL model checker
DLCround-PT-03b-CTLFireability-02: CTL unknown AGGR
DLCround-PT-03b-CTLFireability-03: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-04: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-05: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-06: CTL unknown AGGR
DLCround-PT-03b-CTLFireability-07: F false state space / EG
DLCround-PT-03b-CTLFireability-08: CONJ false CTL model checker
DLCround-PT-03b-CTLFireability-09: CTL unknown AGGR
DLCround-PT-03b-CTLFireability-11: CTL unknown AGGR
DLCround-PT-03b-CTLFireability-12: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-13: CTL false CTL model checker
DLCround-PT-03b-CTLFireability-14: DISJ true state space / EG
DLCround-PT-03b-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-03b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCround-PT-03b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478600626"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-03b.tgz
mv DLCround-PT-03b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;