About the Execution of LoLa+red for DLCflexbar-PT-3a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 13812.531 | 697703.00 | 705431.00 | 2335.80 | ??TTF?TT?FTTTT?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478400522.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCflexbar-PT-3a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478400522
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 6.7K Feb 25 16:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 16:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 25 16:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 18:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 157K Feb 25 18:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 25 17:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Feb 25 17:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 996K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-3a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678258667758
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-3a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 06:57:49] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 06:57:49] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 06:57:49] [INFO ] Load time of PNML (sax parser for PT used): 151 ms
[2023-03-08 06:57:49] [INFO ] Transformed 581 places.
[2023-03-08 06:57:49] [INFO ] Transformed 3891 transitions.
[2023-03-08 06:57:49] [INFO ] Found NUPN structural information;
[2023-03-08 06:57:49] [INFO ] Parsed PT model containing 581 places and 3891 transitions and 14956 arcs in 245 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Ensure Unique test removed 455 transitions
Reduce redundant transitions removed 455 transitions.
Support contains 114 out of 581 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 581/581 places, 3436/3436 transitions.
Discarding 53 places :
Symmetric choice reduction at 0 with 53 rule applications. Total rules 53 place count 528 transition count 3118
Iterating global reduction 0 with 53 rules applied. Total rules applied 106 place count 528 transition count 3118
Ensure Unique test removed 26 transitions
Reduce isomorphic transitions removed 26 transitions.
Iterating post reduction 0 with 26 rules applied. Total rules applied 132 place count 528 transition count 3092
Drop transitions removed 1150 transitions
Redundant transition composition rules discarded 1150 transitions
Iterating global reduction 1 with 1150 rules applied. Total rules applied 1282 place count 528 transition count 1942
Applied a total of 1282 rules in 172 ms. Remains 528 /581 variables (removed 53) and now considering 1942/3436 (removed 1494) transitions.
[2023-03-08 06:57:49] [INFO ] Flow matrix only has 303 transitions (discarded 1639 similar events)
// Phase 1: matrix 303 rows 528 cols
[2023-03-08 06:57:49] [INFO ] Computed 355 place invariants in 18 ms
[2023-03-08 06:57:51] [INFO ] Implicit Places using invariants in 1535 ms returned [208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 222, 223, 224, 225, 226, 228, 229, 230, 231, 232, 233, 236, 237, 238, 239, 240, 242, 243, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 258, 259, 260, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 274, 276, 278, 279, 280, 281, 282, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 296, 297, 298, 299, 300, 301, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 314, 315, 316, 317, 318, 319, 320, 322, 323, 324, 326, 329, 331, 333, 334, 336, 337, 338, 339, 340, 341, 342, 344, 346, 347, 348, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 371, 372, 373, 374, 375, 376, 377, 379, 380, 382, 383, 384, 385, 387, 388, 389, 390, 392, 394, 395, 396, 397, 398, 399, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 418, 419, 420, 421, 422, 423, 426, 428, 430, 431, 432, 434, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, 452, 453, 454, 455, 456, 457, 458, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 470, 471, 472, 473, 474, 476, 478, 479, 480, 482, 484, 485, 487, 488, 490, 493, 495, 496, 497, 498, 502, 503, 504, 505, 506, 508, 509, 510, 511, 512, 513, 516, 517, 519, 520, 521, 522, 523, 524, 525, 526]
Discarding 260 places :
Ensure Unique test removed 1181 transitions
Reduce isomorphic transitions removed 1181 transitions.
Implicit Place search using SMT only with invariants took 1567 ms to find 260 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 268/581 places, 761/3436 transitions.
Drop transitions removed 362 transitions
Redundant transition composition rules discarded 362 transitions
Iterating global reduction 0 with 362 rules applied. Total rules applied 362 place count 268 transition count 399
Applied a total of 362 rules in 7 ms. Remains 268 /268 variables (removed 0) and now considering 399/761 (removed 362) transitions.
[2023-03-08 06:57:51] [INFO ] Flow matrix only has 303 transitions (discarded 96 similar events)
// Phase 1: matrix 303 rows 268 cols
[2023-03-08 06:57:51] [INFO ] Computed 95 place invariants in 2 ms
[2023-03-08 06:57:51] [INFO ] Implicit Places using invariants in 50 ms returned []
[2023-03-08 06:57:51] [INFO ] Flow matrix only has 303 transitions (discarded 96 similar events)
[2023-03-08 06:57:51] [INFO ] Invariant cache hit.
[2023-03-08 06:57:51] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-08 06:57:51] [INFO ] Implicit Places using invariants and state equation in 131 ms returned []
Implicit Place search using SMT with State Equation took 184 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 268/581 places, 399/3436 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1930 ms. Remains : 268/581 places, 399/3436 transitions.
Support contains 114 out of 268 places after structural reductions.
[2023-03-08 06:57:51] [INFO ] Flatten gal took : 52 ms
[2023-03-08 06:57:51] [INFO ] Flatten gal took : 18 ms
[2023-03-08 06:57:51] [INFO ] Input system was already deterministic with 399 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 353 ms. (steps per millisecond=28 ) properties (out of 59) seen :57
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-08 06:57:52] [INFO ] Flow matrix only has 303 transitions (discarded 96 similar events)
[2023-03-08 06:57:52] [INFO ] Invariant cache hit.
[2023-03-08 06:57:52] [INFO ] After 77ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 06:57:52] [INFO ] [Nat]Absence check using 95 positive place invariants in 13 ms returned sat
[2023-03-08 06:57:52] [INFO ] After 72ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 15 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 399 transitions.
Computed a total of 61 stabilizing places and 1 stable transitions
Graph (complete) has 493 edges and 268 vertex of which 208 are kept as prefixes of interest. Removing 60 places using SCC suffix rule.3 ms
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 59 places and 0 transitions.
Iterating post reduction 0 with 59 rules applied. Total rules applied 59 place count 209 transition count 399
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 76 place count 192 transition count 365
Iterating global reduction 1 with 17 rules applied. Total rules applied 93 place count 192 transition count 365
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 97 place count 192 transition count 361
Applied a total of 97 rules in 7 ms. Remains 192 /268 variables (removed 76) and now considering 361/399 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 192/268 places, 361/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 10 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 361 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 48 places and 0 transitions.
Iterating post reduction 0 with 48 rules applied. Total rules applied 48 place count 220 transition count 399
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 62 place count 206 transition count 371
Iterating global reduction 1 with 14 rules applied. Total rules applied 76 place count 206 transition count 371
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 78 place count 206 transition count 369
Applied a total of 78 rules in 5 ms. Remains 206 /268 variables (removed 62) and now considering 369/399 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 206/268 places, 369/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 10 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 51 places and 0 transitions.
Iterating post reduction 0 with 51 rules applied. Total rules applied 51 place count 217 transition count 399
Discarding 13 places :
Symmetric choice reduction at 1 with 13 rule applications. Total rules 64 place count 204 transition count 373
Iterating global reduction 1 with 13 rules applied. Total rules applied 77 place count 204 transition count 373
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 81 place count 204 transition count 369
Applied a total of 81 rules in 6 ms. Remains 204 /268 variables (removed 64) and now considering 369/399 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 204/268 places, 369/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 369 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 56 places and 0 transitions.
Iterating post reduction 0 with 56 rules applied. Total rules applied 56 place count 212 transition count 399
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 73 place count 195 transition count 365
Iterating global reduction 1 with 17 rules applied. Total rules applied 90 place count 195 transition count 365
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 94 place count 195 transition count 361
Applied a total of 94 rules in 6 ms. Remains 195 /268 variables (removed 73) and now considering 361/399 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 195/268 places, 361/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 361 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 58 places and 0 transitions.
Iterating post reduction 0 with 58 rules applied. Total rules applied 58 place count 210 transition count 399
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 73 place count 195 transition count 369
Iterating global reduction 1 with 15 rules applied. Total rules applied 88 place count 195 transition count 369
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 92 place count 195 transition count 365
Applied a total of 92 rules in 5 ms. Remains 195 /268 variables (removed 73) and now considering 365/399 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 195/268 places, 365/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 10 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 365 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 55 places and 0 transitions.
Iterating post reduction 0 with 55 rules applied. Total rules applied 55 place count 213 transition count 399
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 71 place count 197 transition count 367
Iterating global reduction 1 with 16 rules applied. Total rules applied 87 place count 197 transition count 367
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 91 place count 197 transition count 363
Applied a total of 91 rules in 5 ms. Remains 197 /268 variables (removed 71) and now considering 363/399 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 197/268 places, 363/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 363 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Graph (trivial) has 395 edges and 268 vertex of which 204 / 268 are part of one of the 35 SCC in 2 ms
Free SCC test removed 169 places
Ensure Unique test removed 357 transitions
Reduce isomorphic transitions removed 357 transitions.
Graph (complete) has 136 edges and 99 vertex of which 40 are kept as prefixes of interest. Removing 59 places using SCC suffix rule.0 ms
Discarding 59 places :
Also discarding 0 output transitions
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 40 transition count 41
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 39 transition count 41
Discarding 33 places :
Symmetric choice reduction at 2 with 33 rule applications. Total rules 37 place count 6 transition count 8
Iterating global reduction 2 with 33 rules applied. Total rules applied 70 place count 6 transition count 8
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 71 place count 6 transition count 7
Applied a total of 71 rules in 10 ms. Remains 6 /268 variables (removed 262) and now considering 7/399 (removed 392) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 6/268 places, 7/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 0 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 60 places and 0 transitions.
Iterating post reduction 0 with 60 rules applied. Total rules applied 60 place count 208 transition count 399
Discarding 17 places :
Symmetric choice reduction at 1 with 17 rule applications. Total rules 77 place count 191 transition count 365
Iterating global reduction 1 with 17 rules applied. Total rules applied 94 place count 191 transition count 365
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 98 place count 191 transition count 361
Applied a total of 98 rules in 6 ms. Remains 191 /268 variables (removed 77) and now considering 361/399 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 191/268 places, 361/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 361 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 57 places and 0 transitions.
Iterating post reduction 0 with 57 rules applied. Total rules applied 57 place count 211 transition count 399
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 73 place count 195 transition count 367
Iterating global reduction 1 with 16 rules applied. Total rules applied 89 place count 195 transition count 367
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 93 place count 195 transition count 363
Applied a total of 93 rules in 6 ms. Remains 195 /268 variables (removed 73) and now considering 363/399 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 195/268 places, 363/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 363 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Graph (trivial) has 396 edges and 268 vertex of which 205 / 268 are part of one of the 35 SCC in 1 ms
Free SCC test removed 170 places
Ensure Unique test removed 359 transitions
Reduce isomorphic transitions removed 359 transitions.
Graph (complete) has 134 edges and 98 vertex of which 39 are kept as prefixes of interest. Removing 59 places using SCC suffix rule.1 ms
Discarding 59 places :
Also discarding 0 output transitions
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 35 place count 6 transition count 7
Iterating global reduction 0 with 33 rules applied. Total rules applied 68 place count 6 transition count 7
Applied a total of 68 rules in 4 ms. Remains 6 /268 variables (removed 262) and now considering 7/399 (removed 392) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 6/268 places, 7/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 0 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 59 places and 0 transitions.
Iterating post reduction 0 with 59 rules applied. Total rules applied 59 place count 209 transition count 399
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 75 place count 193 transition count 367
Iterating global reduction 1 with 16 rules applied. Total rules applied 91 place count 193 transition count 367
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 95 place count 193 transition count 363
Applied a total of 95 rules in 5 ms. Remains 193 /268 variables (removed 75) and now considering 363/399 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 193/268 places, 363/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 363 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 57 places and 0 transitions.
Iterating post reduction 0 with 57 rules applied. Total rules applied 57 place count 211 transition count 399
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 71 place count 197 transition count 371
Iterating global reduction 1 with 14 rules applied. Total rules applied 85 place count 197 transition count 371
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 89 place count 197 transition count 367
Applied a total of 89 rules in 5 ms. Remains 197 /268 variables (removed 71) and now considering 367/399 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 197/268 places, 367/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 367 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Graph (trivial) has 385 edges and 268 vertex of which 198 / 268 are part of one of the 35 SCC in 1 ms
Free SCC test removed 163 places
Ensure Unique test removed 341 transitions
Reduce isomorphic transitions removed 341 transitions.
Graph (complete) has 152 edges and 105 vertex of which 47 are kept as prefixes of interest. Removing 58 places using SCC suffix rule.0 ms
Discarding 58 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 47 transition count 57
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 46 transition count 57
Discarding 33 places :
Symmetric choice reduction at 2 with 33 rule applications. Total rules 37 place count 13 transition count 23
Iterating global reduction 2 with 33 rules applied. Total rules applied 70 place count 13 transition count 23
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 71 place count 13 transition count 22
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 72 place count 13 transition count 22
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 73 place count 12 transition count 21
Iterating global reduction 2 with 1 rules applied. Total rules applied 74 place count 12 transition count 21
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 75 place count 12 transition count 20
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 76 place count 12 transition count 19
Applied a total of 76 rules in 6 ms. Remains 12 /268 variables (removed 256) and now considering 19/399 (removed 380) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 12/268 places, 19/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 0 ms
[2023-03-08 06:57:52] [INFO ] Input system was already deterministic with 19 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 52 places and 0 transitions.
Iterating post reduction 0 with 52 rules applied. Total rules applied 52 place count 216 transition count 399
Discarding 12 places :
Symmetric choice reduction at 1 with 12 rule applications. Total rules 64 place count 204 transition count 375
Iterating global reduction 1 with 12 rules applied. Total rules applied 76 place count 204 transition count 375
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 79 place count 204 transition count 372
Applied a total of 79 rules in 4 ms. Remains 204 /268 variables (removed 64) and now considering 372/399 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 204/268 places, 372/399 transitions.
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:57:52] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:53] [INFO ] Input system was already deterministic with 372 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 58 places and 0 transitions.
Iterating post reduction 0 with 58 rules applied. Total rules applied 58 place count 210 transition count 399
Discarding 16 places :
Symmetric choice reduction at 1 with 16 rule applications. Total rules 74 place count 194 transition count 367
Iterating global reduction 1 with 16 rules applied. Total rules applied 90 place count 194 transition count 367
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 94 place count 194 transition count 363
Applied a total of 94 rules in 5 ms. Remains 194 /268 variables (removed 74) and now considering 363/399 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 194/268 places, 363/399 transitions.
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:53] [INFO ] Input system was already deterministic with 363 transitions.
Starting structural reductions in LTL mode, iteration 0 : 268/268 places, 399/399 transitions.
Reduce places removed 49 places and 0 transitions.
Iterating post reduction 0 with 49 rules applied. Total rules applied 49 place count 219 transition count 399
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 63 place count 205 transition count 371
Iterating global reduction 1 with 14 rules applied. Total rules applied 77 place count 205 transition count 371
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 81 place count 205 transition count 367
Applied a total of 81 rules in 5 ms. Remains 205 /268 variables (removed 63) and now considering 367/399 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 205/268 places, 367/399 transitions.
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:57:53] [INFO ] Input system was already deterministic with 367 transitions.
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:53] [INFO ] Flatten gal took : 9 ms
[2023-03-08 06:57:53] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-08 06:57:53] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 268 places, 399 transitions and 892 arcs took 2 ms.
Total runtime 3921 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCflexbar-PT-3a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA DLCflexbar-PT-3a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-3a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678259365461
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 DLCflexbar-PT-3a-CTLFireability-02
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 7 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-02
lola: result : true
lola: markings : 41
lola: fired transitions : 56
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:742
lola: LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-3a-CTLFireability-00
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 48 (type SKEL/SRCH) for 33 DLCflexbar-PT-3a-CTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 48 (type SKEL/SRCH) for DLCflexbar-PT-3a-CTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 49 (type SKEL/SRCH) for 21 DLCflexbar-PT-3a-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 49 (type SKEL/SRCH) for DLCflexbar-PT-3a-CTLFireability-07
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type SKEL/SRCH) for 27 DLCflexbar-PT-3a-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type SKEL/SRCH) for DLCflexbar-PT-3a-CTLFireability-09
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/240 1/32 DLCflexbar-PT-3a-CTLFireability-00 158673 m, 31734 m/sec, 3908772 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/240 2/32 DLCflexbar-PT-3a-CTLFireability-00 324823 m, 33230 m/sec, 7802163 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/240 3/32 DLCflexbar-PT-3a-CTLFireability-00 479734 m, 30982 m/sec, 11563515 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/240 3/32 DLCflexbar-PT-3a-CTLFireability-00 643619 m, 32777 m/sec, 15302498 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/240 4/32 DLCflexbar-PT-3a-CTLFireability-00 804074 m, 32091 m/sec, 19055973 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/240 5/32 DLCflexbar-PT-3a-CTLFireability-00 955686 m, 30322 m/sec, 22754845 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/240 6/32 DLCflexbar-PT-3a-CTLFireability-00 1116911 m, 32245 m/sec, 26465946 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/240 6/32 DLCflexbar-PT-3a-CTLFireability-00 1277306 m, 32079 m/sec, 30164864 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/240 7/32 DLCflexbar-PT-3a-CTLFireability-00 1428593 m, 30257 m/sec, 33840784 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/240 8/32 DLCflexbar-PT-3a-CTLFireability-00 1574586 m, 29198 m/sec, 37511060 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/240 8/32 DLCflexbar-PT-3a-CTLFireability-00 1719953 m, 29073 m/sec, 41174296 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/240 9/32 DLCflexbar-PT-3a-CTLFireability-00 1862568 m, 28523 m/sec, 44792178 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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1 CTL EXCL 65/240 10/32 DLCflexbar-PT-3a-CTLFireability-00 2006362 m, 28758 m/sec, 48440219 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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43 CTL EXCL 65/255 10/32 DLCflexbar-PT-3a-CTLFireability-14 2065511 m, 29022 m/sec, 47850358 t fired, .
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43 CTL EXCL 70/255 10/32 DLCflexbar-PT-3a-CTLFireability-14 2228027 m, 32503 m/sec, 51400611 t fired, .
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43 CTL EXCL 75/255 11/32 DLCflexbar-PT-3a-CTLFireability-14 2395480 m, 33490 m/sec, 54938512 t fired, .
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43 CTL EXCL 90/255 13/32 DLCflexbar-PT-3a-CTLFireability-14 2886131 m, 34187 m/sec, 65665190 t fired, .
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43 CTL EXCL 95/255 14/32 DLCflexbar-PT-3a-CTLFireability-14 3049160 m, 32605 m/sec, 69274307 t fired, .
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43 CTL EXCL 100/255 14/32 DLCflexbar-PT-3a-CTLFireability-14 3211793 m, 32526 m/sec, 72833274 t fired, .
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43 CTL EXCL 110/255 16/32 DLCflexbar-PT-3a-CTLFireability-14 3537833 m, 31893 m/sec, 80159798 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-04: CTL false CTL model checker
DLCflexbar-PT-3a-CTLFireability-07: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-10: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/590 27/32 DLCflexbar-PT-3a-CTLFireability-01 6370276 m, 215231 m/sec, 21370293 t fired, .
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DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-04: CTL false CTL model checker
DLCflexbar-PT-3a-CTLFireability-07: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-10: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/590 32/32 DLCflexbar-PT-3a-CTLFireability-01 7439658 m, 213876 m/sec, 24819893 t fired, .
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lola: CANCELED task # 4 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-04: CTL false CTL model checker
DLCflexbar-PT-3a-CTLFireability-07: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-10: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-3a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-09: AFAG 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-3a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-3a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 28 (type EXCL) for 27 DLCflexbar-PT-3a-CTLFireability-09
lola: time limit : 727 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-09
lola: result : false
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DLCflexbar-PT-3a-CTLFireability-06
lola: time limit : 970 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-06
lola: result : true
lola: markings : 4
lola: fired transitions : 75
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 DLCflexbar-PT-3a-CTLFireability-12
lola: time limit : 1455 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCflexbar-PT-3a-CTLFireability-03
lola: time limit : 2910 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DLCflexbar-PT-3a-CTLFireability-03
lola: result : true
lola: markings : 7
lola: fired transitions : 269
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-3a-CTLFireability-00: CTL unknown AGGR
DLCflexbar-PT-3a-CTLFireability-01: CTL unknown AGGR
DLCflexbar-PT-3a-CTLFireability-02: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-03: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-04: CTL false CTL model checker
DLCflexbar-PT-3a-CTLFireability-05: CTL unknown AGGR
DLCflexbar-PT-3a-CTLFireability-06: EFAGEF true tscc_search
DLCflexbar-PT-3a-CTLFireability-07: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-08: CTL unknown AGGR
DLCflexbar-PT-3a-CTLFireability-09: AFAG false CTL model checker
DLCflexbar-PT-3a-CTLFireability-10: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-12: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-13: CTL true CTL model checker
DLCflexbar-PT-3a-CTLFireability-14: CTL unknown AGGR
DLCflexbar-PT-3a-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-3a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCflexbar-PT-3a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478400522"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-3a.tgz
mv DLCflexbar-PT-3a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;