Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478400506.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DLCflexbar-PT-2a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478400506
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 948K
-rw-r--r-- 1 mcc users 6.2K Feb 25 15:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 15:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 15:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 15:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 16:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 25 16:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 16:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 25 16:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 545K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-2a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678256668884

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-2a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 06:24:30] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 06:24:30] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 06:24:30] [INFO ] Load time of PNML (sax parser for PT used): 116 ms
[2023-03-08 06:24:30] [INFO ] Transformed 353 places.
[2023-03-08 06:24:30] [INFO ] Transformed 2169 transitions.
[2023-03-08 06:24:30] [INFO ] Found NUPN structural information;
[2023-03-08 06:24:30] [INFO ] Parsed PT model containing 353 places and 2169 transitions and 8205 arcs in 189 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Ensure Unique test removed 264 transitions
Reduce redundant transitions removed 264 transitions.
Support contains 131 out of 353 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 353/353 places, 1905/1905 transitions.
Discarding 23 places :
Symmetric choice reduction at 0 with 23 rule applications. Total rules 23 place count 330 transition count 1790
Iterating global reduction 0 with 23 rules applied. Total rules applied 46 place count 330 transition count 1790
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 57 place count 330 transition count 1779
Drop transitions removed 620 transitions
Redundant transition composition rules discarded 620 transitions
Iterating global reduction 1 with 620 rules applied. Total rules applied 677 place count 330 transition count 1159
Applied a total of 677 rules in 81 ms. Remains 330 /353 variables (removed 23) and now considering 1159/1905 (removed 746) transitions.
[2023-03-08 06:24:30] [INFO ] Flow matrix only has 232 transitions (discarded 927 similar events)
// Phase 1: matrix 232 rows 330 cols
[2023-03-08 06:24:30] [INFO ] Computed 196 place invariants in 18 ms
[2023-03-08 06:24:31] [INFO ] Implicit Places using invariants in 758 ms returned [158, 160, 163, 164, 166, 167, 168, 170, 171, 172, 174, 175, 176, 177, 178, 179, 180, 182, 184, 185, 187, 190, 192, 193, 194, 198, 200, 203, 204, 206, 207, 209, 210, 212, 214, 219, 221, 222, 223, 224, 229, 230, 231, 232, 234, 235, 236, 237, 238, 239, 242, 243, 244, 246, 248, 250, 253, 254, 256, 257, 258, 260, 261, 264, 267, 268, 269, 270, 272, 273, 274, 275, 278, 279, 282, 283, 284, 285, 286, 287, 290, 291, 292, 293, 294, 295, 296, 297, 298, 300, 302, 303, 305, 306, 309, 310, 316, 317, 321, 323, 325]
Discarding 101 places :
Ensure Unique test removed 418 transitions
Reduce isomorphic transitions removed 418 transitions.
Implicit Place search using SMT only with invariants took 790 ms to find 101 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 229/353 places, 741/1905 transitions.
Drop transitions removed 423 transitions
Redundant transition composition rules discarded 423 transitions
Iterating global reduction 0 with 423 rules applied. Total rules applied 423 place count 229 transition count 318
Applied a total of 423 rules in 8 ms. Remains 229 /229 variables (removed 0) and now considering 318/741 (removed 423) transitions.
[2023-03-08 06:24:31] [INFO ] Flow matrix only has 232 transitions (discarded 86 similar events)
// Phase 1: matrix 232 rows 229 cols
[2023-03-08 06:24:31] [INFO ] Computed 95 place invariants in 2 ms
[2023-03-08 06:24:31] [INFO ] Implicit Places using invariants in 52 ms returned []
[2023-03-08 06:24:31] [INFO ] Flow matrix only has 232 transitions (discarded 86 similar events)
[2023-03-08 06:24:31] [INFO ] Invariant cache hit.
[2023-03-08 06:24:31] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-03-08 06:24:31] [INFO ] Implicit Places using invariants and state equation in 122 ms returned []
Implicit Place search using SMT with State Equation took 176 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 229/353 places, 318/1905 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1056 ms. Remains : 229/353 places, 318/1905 transitions.
Support contains 131 out of 229 places after structural reductions.
[2023-03-08 06:24:31] [INFO ] Flatten gal took : 41 ms
[2023-03-08 06:24:31] [INFO ] Flatten gal took : 18 ms
[2023-03-08 06:24:31] [INFO ] Input system was already deterministic with 318 transitions.
Support contains 123 out of 229 places (down from 131) after GAL structural reductions.
Finished random walk after 3113 steps, including 0 resets, run visited all 78 properties in 146 ms. (steps per millisecond=21 )
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 318 transitions.
Computed a total of 72 stabilizing places and 1 stable transitions
Graph (complete) has 422 edges and 229 vertex of which 162 are kept as prefixes of interest. Removing 67 places using SCC suffix rule.3 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Graph (trivial) has 306 edges and 229 vertex of which 153 / 229 are part of one of the 24 SCC in 3 ms
Free SCC test removed 129 places
Ensure Unique test removed 279 transitions
Reduce isomorphic transitions removed 279 transitions.
Graph (complete) has 143 edges and 100 vertex of which 34 are kept as prefixes of interest. Removing 66 places using SCC suffix rule.1 ms
Discarding 66 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 34 transition count 38
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 33 transition count 38
Discarding 25 places :
Symmetric choice reduction at 2 with 25 rule applications. Total rules 29 place count 8 transition count 10
Iterating global reduction 2 with 25 rules applied. Total rules applied 54 place count 8 transition count 10
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 55 place count 8 transition count 9
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 57 place count 7 transition count 8
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 58 place count 7 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 59 place count 6 transition count 7
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 60 place count 5 transition count 6
Iterating global reduction 4 with 1 rules applied. Total rules applied 61 place count 5 transition count 6
Applied a total of 61 rules in 14 ms. Remains 5 /229 variables (removed 224) and now considering 6/318 (removed 312) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 5/229 places, 6/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 0 with 64 rules applied. Total rules applied 64 place count 165 transition count 318
Discarding 26 places :
Symmetric choice reduction at 1 with 26 rule applications. Total rules 90 place count 139 transition count 266
Iterating global reduction 1 with 26 rules applied. Total rules applied 116 place count 139 transition count 266
Ensure Unique test removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 1 with 8 rules applied. Total rules applied 124 place count 139 transition count 258
Applied a total of 124 rules in 4 ms. Remains 139 /229 variables (removed 90) and now considering 258/318 (removed 60) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 139/229 places, 258/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 258 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 54 places and 0 transitions.
Iterating post reduction 0 with 54 rules applied. Total rules applied 54 place count 175 transition count 318
Discarding 23 places :
Symmetric choice reduction at 1 with 23 rule applications. Total rules 77 place count 152 transition count 272
Iterating global reduction 1 with 23 rules applied. Total rules applied 100 place count 152 transition count 272
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 109 place count 152 transition count 263
Applied a total of 109 rules in 4 ms. Remains 152 /229 variables (removed 77) and now considering 263/318 (removed 55) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 152/229 places, 263/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 263 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 59 places and 0 transitions.
Iterating post reduction 0 with 59 rules applied. Total rules applied 59 place count 170 transition count 318
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 81 place count 148 transition count 274
Iterating global reduction 1 with 22 rules applied. Total rules applied 103 place count 148 transition count 274
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 110 place count 148 transition count 267
Applied a total of 110 rules in 4 ms. Remains 148 /229 variables (removed 81) and now considering 267/318 (removed 51) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 148/229 places, 267/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 267 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 60 places and 0 transitions.
Iterating post reduction 0 with 60 rules applied. Total rules applied 60 place count 169 transition count 318
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 82 place count 147 transition count 274
Iterating global reduction 1 with 22 rules applied. Total rules applied 104 place count 147 transition count 274
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 113 place count 147 transition count 265
Applied a total of 113 rules in 5 ms. Remains 147 /229 variables (removed 82) and now considering 265/318 (removed 53) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 147/229 places, 265/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 8 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 265 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Graph (trivial) has 306 edges and 229 vertex of which 153 / 229 are part of one of the 24 SCC in 1 ms
Free SCC test removed 129 places
Ensure Unique test removed 279 transitions
Reduce isomorphic transitions removed 279 transitions.
Graph (complete) has 143 edges and 100 vertex of which 33 are kept as prefixes of interest. Removing 67 places using SCC suffix rule.1 ms
Discarding 67 places :
Also discarding 0 output transitions
Reduce places removed 1 places and 1 transitions.
Reduce places removed 26 places and 0 transitions.
Ensure Unique test removed 27 transitions
Reduce isomorphic transitions removed 27 transitions.
Graph (trivial) has 7 edges and 6 vertex of which 4 / 6 are part of one of the 1 SCC in 0 ms
Free SCC test removed 3 places
Iterating post reduction 0 with 54 rules applied. Total rules applied 56 place count 3 transition count 11
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 63 place count 2 transition count 5
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 65 place count 2 transition count 3
Applied a total of 65 rules in 4 ms. Remains 2 /229 variables (removed 227) and now considering 3/318 (removed 315) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 2/229 places, 3/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 0 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 55 places and 0 transitions.
Iterating post reduction 0 with 55 rules applied. Total rules applied 55 place count 174 transition count 318
Discarding 22 places :
Symmetric choice reduction at 1 with 22 rule applications. Total rules 77 place count 152 transition count 274
Iterating global reduction 1 with 22 rules applied. Total rules applied 99 place count 152 transition count 274
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 105 place count 152 transition count 268
Applied a total of 105 rules in 5 ms. Remains 152 /229 variables (removed 77) and now considering 268/318 (removed 50) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 152/229 places, 268/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 268 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 61 places and 0 transitions.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 168 transition count 318
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 88 place count 141 transition count 264
Iterating global reduction 1 with 27 rules applied. Total rules applied 115 place count 141 transition count 264
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 124 place count 141 transition count 255
Applied a total of 124 rules in 4 ms. Remains 141 /229 variables (removed 88) and now considering 255/318 (removed 63) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 141/229 places, 255/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 65 places and 0 transitions.
Iterating post reduction 0 with 65 rules applied. Total rules applied 65 place count 164 transition count 318
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 92 place count 137 transition count 264
Iterating global reduction 1 with 27 rules applied. Total rules applied 119 place count 137 transition count 264
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 128 place count 137 transition count 255
Applied a total of 128 rules in 4 ms. Remains 137 /229 variables (removed 92) and now considering 255/318 (removed 63) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 137/229 places, 255/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 62 places and 0 transitions.
Iterating post reduction 0 with 62 rules applied. Total rules applied 62 place count 167 transition count 318
Discarding 25 places :
Symmetric choice reduction at 1 with 25 rule applications. Total rules 87 place count 142 transition count 268
Iterating global reduction 1 with 25 rules applied. Total rules applied 112 place count 142 transition count 268
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 121 place count 142 transition count 259
Applied a total of 121 rules in 4 ms. Remains 142 /229 variables (removed 87) and now considering 259/318 (removed 59) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 142/229 places, 259/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 259 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 163 transition count 318
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 94 place count 135 transition count 262
Iterating global reduction 1 with 28 rules applied. Total rules applied 122 place count 135 transition count 262
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 131 place count 135 transition count 253
Applied a total of 131 rules in 4 ms. Remains 135 /229 variables (removed 94) and now considering 253/318 (removed 65) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 135/229 places, 253/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 253 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Graph (trivial) has 301 edges and 229 vertex of which 150 / 229 are part of one of the 24 SCC in 0 ms
Free SCC test removed 126 places
Ensure Unique test removed 273 transitions
Reduce isomorphic transitions removed 273 transitions.
Graph (complete) has 149 edges and 103 vertex of which 38 are kept as prefixes of interest. Removing 65 places using SCC suffix rule.0 ms
Discarding 65 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 3 place count 38 transition count 44
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 5 place count 37 transition count 43
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 6 place count 36 transition count 43
Discarding 23 places :
Symmetric choice reduction at 3 with 23 rule applications. Total rules 29 place count 13 transition count 17
Iterating global reduction 3 with 23 rules applied. Total rules applied 52 place count 13 transition count 17
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 53 place count 13 transition count 16
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 55 place count 12 transition count 15
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 56 place count 12 transition count 14
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 57 place count 11 transition count 14
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules 58 place count 10 transition count 13
Iterating global reduction 5 with 1 rules applied. Total rules applied 59 place count 10 transition count 13
Applied a total of 59 rules in 6 ms. Remains 10 /229 variables (removed 219) and now considering 13/318 (removed 305) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 10/229 places, 13/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 1 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 13 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 65 places and 0 transitions.
Iterating post reduction 0 with 65 rules applied. Total rules applied 65 place count 164 transition count 318
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 92 place count 137 transition count 264
Iterating global reduction 1 with 27 rules applied. Total rules applied 119 place count 137 transition count 264
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 128 place count 137 transition count 255
Applied a total of 128 rules in 3 ms. Remains 137 /229 variables (removed 92) and now considering 255/318 (removed 63) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 137/229 places, 255/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 5 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 57 places and 0 transitions.
Iterating post reduction 0 with 57 rules applied. Total rules applied 57 place count 172 transition count 318
Discarding 20 places :
Symmetric choice reduction at 1 with 20 rule applications. Total rules 77 place count 152 transition count 278
Iterating global reduction 1 with 20 rules applied. Total rules applied 97 place count 152 transition count 278
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 103 place count 152 transition count 272
Applied a total of 103 rules in 3 ms. Remains 152 /229 variables (removed 77) and now considering 272/318 (removed 46) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 152/229 places, 272/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 5 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 6 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 272 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 66 places and 0 transitions.
Iterating post reduction 0 with 66 rules applied. Total rules applied 66 place count 163 transition count 318
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 94 place count 135 transition count 262
Iterating global reduction 1 with 28 rules applied. Total rules applied 122 place count 135 transition count 262
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Iterating post reduction 1 with 9 rules applied. Total rules applied 131 place count 135 transition count 253
Applied a total of 131 rules in 3 ms. Remains 135 /229 variables (removed 94) and now considering 253/318 (removed 65) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 135/229 places, 253/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 4 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 5 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 253 transitions.
Starting structural reductions in LTL mode, iteration 0 : 229/229 places, 318/318 transitions.
Reduce places removed 61 places and 0 transitions.
Iterating post reduction 0 with 61 rules applied. Total rules applied 61 place count 168 transition count 318
Discarding 24 places :
Symmetric choice reduction at 1 with 24 rule applications. Total rules 85 place count 144 transition count 270
Iterating global reduction 1 with 24 rules applied. Total rules applied 109 place count 144 transition count 270
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed 7 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 116 place count 144 transition count 263
Applied a total of 116 rules in 4 ms. Remains 144 /229 variables (removed 85) and now considering 263/318 (removed 55) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 144/229 places, 263/318 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 5 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 5 ms
[2023-03-08 06:24:32] [INFO ] Input system was already deterministic with 263 transitions.
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Flatten gal took : 7 ms
[2023-03-08 06:24:32] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 06:24:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 229 places, 318 transitions and 746 arcs took 1 ms.
Total runtime 2385 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DLCflexbar-PT-2a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA DLCflexbar-PT-2a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-2a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678257610661

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 52 (type SKEL/SRCH) for 0 DLCflexbar-PT-2a-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-2a-CTLFireability-00
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 54 (type SKEL/FNDP) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SKEL/EQUN) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SKEL/SRCH) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 57 (type SKEL/SRCH) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type SKEL/SRCH) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 54 (type FNDP) for DLCflexbar-PT-2a-CTLFireability-06 (obsolete)
lola: CANCELED task # 55 (type EQUN) for DLCflexbar-PT-2a-CTLFireability-06 (obsolete)
lola: LAUNCH task # 4 (type EXCL) for 3 DLCflexbar-PT-2a-CTLFireability-01
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type SKEL/FNDP) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/374/CTLFireability-55.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 55 (type SKEL/EQUN) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 58 (type SKEL/SRCH) for 46 DLCflexbar-PT-2a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 58 (type SKEL/SRCH) for DLCflexbar-PT-2a-CTLFireability-14
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 59 (type FNDP) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 62 (type SRCH) for 18 DLCflexbar-PT-2a-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 62 (type SRCH) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/374/CTLFireability-60.sara.

lola: FINISHED task # 59 (type FNDP) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 60 (type EQUN) for DLCflexbar-PT-2a-CTLFireability-06 (obsolete)
lola: FINISHED task # 60 (type EQUN) for DLCflexbar-PT-2a-CTLFireability-06
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-2a-CTLFireability-06: DISJ true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-2a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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4 CTL EXCL 5/239 2/32 DLCflexbar-PT-2a-CTLFireability-01 263560 m, 52712 m/sec, 4325290 t fired, .

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4 CTL EXCL 10/239 3/32 DLCflexbar-PT-2a-CTLFireability-01 513609 m, 50009 m/sec, 8514116 t fired, .

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4 CTL EXCL 15/239 4/32 DLCflexbar-PT-2a-CTLFireability-01 754141 m, 48106 m/sec, 12646581 t fired, .

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4 CTL EXCL 20/239 5/32 DLCflexbar-PT-2a-CTLFireability-01 978495 m, 44870 m/sec, 16664594 t fired, .

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4 CTL EXCL 25/239 6/32 DLCflexbar-PT-2a-CTLFireability-01 1198180 m, 43937 m/sec, 20647752 t fired, .

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4 CTL EXCL 30/239 7/32 DLCflexbar-PT-2a-CTLFireability-01 1420947 m, 44553 m/sec, 24638138 t fired, .

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4 CTL EXCL 35/239 8/32 DLCflexbar-PT-2a-CTLFireability-01 1648007 m, 45412 m/sec, 28613513 t fired, .

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4 CTL EXCL 40/239 9/32 DLCflexbar-PT-2a-CTLFireability-01 1895458 m, 49490 m/sec, 32642214 t fired, .

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4 CTL EXCL 45/239 10/32 DLCflexbar-PT-2a-CTLFireability-01 2140586 m, 49025 m/sec, 36806514 t fired, .

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4 CTL EXCL 50/239 11/32 DLCflexbar-PT-2a-CTLFireability-01 2361511 m, 44185 m/sec, 40738725 t fired, .

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4 CTL EXCL 55/239 12/32 DLCflexbar-PT-2a-CTLFireability-01 2577594 m, 43216 m/sec, 44602048 t fired, .

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4 CTL EXCL 60/239 13/32 DLCflexbar-PT-2a-CTLFireability-01 2790297 m, 42540 m/sec, 48457036 t fired, .

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4 CTL EXCL 65/239 14/32 DLCflexbar-PT-2a-CTLFireability-01 3002908 m, 42522 m/sec, 52317398 t fired, .

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4 CTL EXCL 70/239 15/32 DLCflexbar-PT-2a-CTLFireability-01 3212774 m, 41973 m/sec, 56133329 t fired, .

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4 CTL EXCL 75/239 16/32 DLCflexbar-PT-2a-CTLFireability-01 3451035 m, 47652 m/sec, 60033606 t fired, .

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4 CTL EXCL 80/239 18/32 DLCflexbar-PT-2a-CTLFireability-01 3709562 m, 51705 m/sec, 64040258 t fired, .

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4 CTL EXCL 85/239 19/32 DLCflexbar-PT-2a-CTLFireability-01 3942144 m, 46516 m/sec, 68018523 t fired, .

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4 CTL EXCL 95/239 21/32 DLCflexbar-PT-2a-CTLFireability-01 4378617 m, 43585 m/sec, 75496285 t fired, .

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4 CTL EXCL 100/239 22/32 DLCflexbar-PT-2a-CTLFireability-01 4587486 m, 41773 m/sec, 79193066 t fired, .

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4 CTL EXCL 105/239 23/32 DLCflexbar-PT-2a-CTLFireability-01 4834447 m, 49392 m/sec, 83002586 t fired, .

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4 CTL EXCL 110/239 24/32 DLCflexbar-PT-2a-CTLFireability-01 5082346 m, 49579 m/sec, 86943248 t fired, .

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4 CTL EXCL 115/239 25/32 DLCflexbar-PT-2a-CTLFireability-01 5304257 m, 44382 m/sec, 90674999 t fired, .

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4 CTL EXCL 120/239 25/32 DLCflexbar-PT-2a-CTLFireability-01 5516439 m, 42436 m/sec, 94301343 t fired, .

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4 CTL EXCL 125/239 26/32 DLCflexbar-PT-2a-CTLFireability-01 5726586 m, 42029 m/sec, 98023651 t fired, .

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4 CTL EXCL 135/239 28/32 DLCflexbar-PT-2a-CTLFireability-01 6150419 m, 42710 m/sec, 105709633 t fired, .

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4 CTL EXCL 145/239 30/32 DLCflexbar-PT-2a-CTLFireability-01 6604312 m, 49035 m/sec, 113713936 t fired, .

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4 CTL EXCL 150/239 32/32 DLCflexbar-PT-2a-CTLFireability-01 6877197 m, 54577 m/sec, 118128048 t fired, .

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44 CTL EXCL 5/287 5/32 DLCflexbar-PT-2a-CTLFireability-13 1005115 m, 201023 m/sec, 4402286 t fired, .

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44 CTL EXCL 10/287 9/32 DLCflexbar-PT-2a-CTLFireability-13 1964355 m, 191848 m/sec, 8623522 t fired, .

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44 CTL EXCL 15/287 13/32 DLCflexbar-PT-2a-CTLFireability-13 2932185 m, 193566 m/sec, 12861377 t fired, .

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44 CTL EXCL 20/287 17/32 DLCflexbar-PT-2a-CTLFireability-13 3866667 m, 186896 m/sec, 16981560 t fired, .

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44 CTL EXCL 40/287 32/32 DLCflexbar-PT-2a-CTLFireability-13 7511750 m, 178655 m/sec, 32632795 t fired, .

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41 CTL EXCL 10/309 4/32 DLCflexbar-PT-2a-CTLFireability-12 652657 m, 64559 m/sec, 7790152 t fired, .

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41 CTL EXCL 25/309 8/32 DLCflexbar-PT-2a-CTLFireability-12 1570708 m, 59228 m/sec, 18778783 t fired, .

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41 CTL EXCL 30/309 9/32 DLCflexbar-PT-2a-CTLFireability-12 1863544 m, 58567 m/sec, 22350278 t fired, .

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41 CTL EXCL 35/309 10/32 DLCflexbar-PT-2a-CTLFireability-12 2143651 m, 56021 m/sec, 25792015 t fired, .

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41 CTL EXCL 75/309 21/32 DLCflexbar-PT-2a-CTLFireability-12 4457843 m, 55212 m/sec, 53760607 t fired, .

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41 CTL EXCL 80/309 22/32 DLCflexbar-PT-2a-CTLFireability-12 4734219 m, 55275 m/sec, 57165437 t fired, .

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41 CTL EXCL 85/309 24/32 DLCflexbar-PT-2a-CTLFireability-12 5006205 m, 54397 m/sec, 60536575 t fired, .

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41 CTL EXCL 115/309 32/32 DLCflexbar-PT-2a-CTLFireability-12 6781669 m, 57216 m/sec, 81261037 t fired, .

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32 CTL EXCL 120/359 24/32 DLCflexbar-PT-2a-CTLFireability-09 5349801 m, 43005 m/sec, 96799799 t fired, .

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32 CTL EXCL 125/359 25/32 DLCflexbar-PT-2a-CTLFireability-09 5557774 m, 41594 m/sec, 100561918 t fired, .

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DLCflexbar-PT-2a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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DLCflexbar-PT-2a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/570 3/32 DLCflexbar-PT-2a-CTLFireability-03 579701 m, 55176 m/sec, 9056837 t fired, .

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DLCflexbar-PT-2a-CTLFireability-14: CTL true CTL model checker
DLCflexbar-PT-2a-CTLFireability-15: CTL true CTL model checker

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DLCflexbar-PT-2a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/570 4/32 DLCflexbar-PT-2a-CTLFireability-03 836434 m, 51346 m/sec, 13290880 t fired, .

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DLCflexbar-PT-2a-CTLFireability-14: CTL true CTL model checker
DLCflexbar-PT-2a-CTLFireability-15: CTL true CTL model checker

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DLCflexbar-PT-2a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

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10 CTL EXCL 20/570 5/32 DLCflexbar-PT-2a-CTLFireability-03 1078753 m, 48463 m/sec, 17384286 t fired, .

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DLCflexbar-PT-2a-CTLFireability-14: CTL true CTL model checker
DLCflexbar-PT-2a-CTLFireability-15: CTL true CTL model checker

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/570 7/32 DLCflexbar-PT-2a-CTLFireability-03 1316080 m, 47465 m/sec, 21440815 t fired, .

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DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/570 8/32 DLCflexbar-PT-2a-CTLFireability-03 1549803 m, 46744 m/sec, 25427575 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/570 9/32 DLCflexbar-PT-2a-CTLFireability-03 1816177 m, 53274 m/sec, 29502299 t fired, .

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DLCflexbar-PT-2a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/570 10/32 DLCflexbar-PT-2a-CTLFireability-03 2078168 m, 52398 m/sec, 33618990 t fired, .

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DLCflexbar-PT-2a-CTLFireability-14: CTL true CTL model checker
DLCflexbar-PT-2a-CTLFireability-15: CTL true CTL model checker

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DLCflexbar-PT-2a-CTLFireability-05: AGEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2a-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
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DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/570 11/32 DLCflexbar-PT-2a-CTLFireability-03 2315676 m, 47501 m/sec, 37583946 t fired, .

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10 CTL EXCL 50/570 12/32 DLCflexbar-PT-2a-CTLFireability-03 2545078 m, 45880 m/sec, 41451151 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 55/570 13/32 DLCflexbar-PT-2a-CTLFireability-03 2769810 m, 44946 m/sec, 45323115 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 60/570 14/32 DLCflexbar-PT-2a-CTLFireability-03 2994890 m, 45016 m/sec, 49177738 t fired, .

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10 CTL EXCL 65/570 15/32 DLCflexbar-PT-2a-CTLFireability-03 3215647 m, 44151 m/sec, 52973123 t fired, .

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10 CTL EXCL 70/570 16/32 DLCflexbar-PT-2a-CTLFireability-03 3469214 m, 50713 m/sec, 56857742 t fired, .

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10 CTL EXCL 75/570 17/32 DLCflexbar-PT-2a-CTLFireability-03 3747006 m, 55558 m/sec, 60898387 t fired, .

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10 CTL EXCL 145/570 32/32 DLCflexbar-PT-2a-CTLFireability-03 7163975 m, 56442 m/sec, 115627301 t fired, .

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7 CTL EXCL 4/676 5/32 DLCflexbar-PT-2a-CTLFireability-02 1013778 m, 202755 m/sec, 3741790 t fired, .

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7 CTL EXCL 9/675 9/32 DLCflexbar-PT-2a-CTLFireability-02 2142346 m, 225713 m/sec, 7873098 t fired, .

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7 CTL EXCL 14/675 14/32 DLCflexbar-PT-2a-CTLFireability-02 3250864 m, 221703 m/sec, 11974127 t fired, .

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7 CTL EXCL 19/675 19/32 DLCflexbar-PT-2a-CTLFireability-02 4312327 m, 212292 m/sec, 15893616 t fired, .

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7 CTL EXCL 24/675 23/32 DLCflexbar-PT-2a-CTLFireability-02 5356886 m, 208911 m/sec, 19644376 t fired, .

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DLCflexbar-PT-2a-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 29/675 27/32 DLCflexbar-PT-2a-CTLFireability-02 6420403 m, 212703 m/sec, 23401271 t fired, .

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7 CTL EXCL 34/675 32/32 DLCflexbar-PT-2a-CTLFireability-02 7447233 m, 205366 m/sec, 27045504 t fired, .

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-2a-CTLFireability-00: EFEG true state space /EFEG
DLCflexbar-PT-2a-CTLFireability-01: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-02: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-03: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-04: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-05: AGEF true tscc_search
DLCflexbar-PT-2a-CTLFireability-06: DISJ true findpath
DLCflexbar-PT-2a-CTLFireability-07: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-08: CTL false CTL model checker
DLCflexbar-PT-2a-CTLFireability-09: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-10: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-11: CTL false CTL model checker
DLCflexbar-PT-2a-CTLFireability-12: CTL unknown AGGR
DLCflexbar-PT-2a-CTLFireability-13: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-2a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DLCflexbar-PT-2a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478400506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-2a.tgz
mv DLCflexbar-PT-2a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;