Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478400498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DES-PT-60b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478400498
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 576K
-rw-r--r-- 1 mcc users 8.6K Feb 26 15:44 CTLCardinality.txt
-rw-r--r-- 1 mcc users 102K Feb 26 15:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 26 15:43 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 15:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.3K Feb 26 15:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 15:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.3K Feb 26 15:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 15:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 139K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-60b-CTLFireability-00
FORMULA_NAME DES-PT-60b-CTLFireability-01
FORMULA_NAME DES-PT-60b-CTLFireability-02
FORMULA_NAME DES-PT-60b-CTLFireability-03
FORMULA_NAME DES-PT-60b-CTLFireability-04
FORMULA_NAME DES-PT-60b-CTLFireability-05
FORMULA_NAME DES-PT-60b-CTLFireability-06
FORMULA_NAME DES-PT-60b-CTLFireability-07
FORMULA_NAME DES-PT-60b-CTLFireability-08
FORMULA_NAME DES-PT-60b-CTLFireability-09
FORMULA_NAME DES-PT-60b-CTLFireability-10
FORMULA_NAME DES-PT-60b-CTLFireability-11
FORMULA_NAME DES-PT-60b-CTLFireability-12
FORMULA_NAME DES-PT-60b-CTLFireability-13
FORMULA_NAME DES-PT-60b-CTLFireability-14
FORMULA_NAME DES-PT-60b-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678255435815

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-60b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 06:03:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 06:03:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 06:03:57] [INFO ] Load time of PNML (sax parser for PT used): 69 ms
[2023-03-08 06:03:57] [INFO ] Transformed 519 places.
[2023-03-08 06:03:57] [INFO ] Transformed 470 transitions.
[2023-03-08 06:03:57] [INFO ] Found NUPN structural information;
[2023-03-08 06:03:57] [INFO ] Parsed PT model containing 519 places and 470 transitions and 1623 arcs in 136 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 127 out of 519 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 519/519 places, 470/470 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 516 transition count 470
Discarding 15 places :
Symmetric choice reduction at 1 with 15 rule applications. Total rules 18 place count 501 transition count 455
Iterating global reduction 1 with 15 rules applied. Total rules applied 33 place count 501 transition count 455
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 41 place count 493 transition count 447
Iterating global reduction 1 with 8 rules applied. Total rules applied 49 place count 493 transition count 447
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 55 place count 493 transition count 441
Applied a total of 55 rules in 113 ms. Remains 493 /519 variables (removed 26) and now considering 441/470 (removed 29) transitions.
// Phase 1: matrix 441 rows 493 cols
[2023-03-08 06:03:57] [INFO ] Computed 62 place invariants in 54 ms
[2023-03-08 06:03:58] [INFO ] Implicit Places using invariants in 623 ms returned []
[2023-03-08 06:03:58] [INFO ] Invariant cache hit.
[2023-03-08 06:03:58] [INFO ] Implicit Places using invariants and state equation in 537 ms returned []
Implicit Place search using SMT with State Equation took 1184 ms to find 0 implicit places.
[2023-03-08 06:03:58] [INFO ] Invariant cache hit.
[2023-03-08 06:03:58] [INFO ] Dead Transitions using invariants and state equation in 233 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 493/519 places, 441/470 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1533 ms. Remains : 493/519 places, 441/470 transitions.
Support contains 127 out of 493 places after structural reductions.
[2023-03-08 06:03:59] [INFO ] Flatten gal took : 65 ms
[2023-03-08 06:03:59] [INFO ] Flatten gal took : 31 ms
[2023-03-08 06:03:59] [INFO ] Input system was already deterministic with 441 transitions.
Incomplete random walk after 10000 steps, including 87 resets, run finished after 517 ms. (steps per millisecond=19 ) properties (out of 89) seen :41
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 48) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 48) seen :0
Running SMT prover for 48 properties.
[2023-03-08 06:04:00] [INFO ] Invariant cache hit.
[2023-03-08 06:04:00] [INFO ] After 514ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:48
[2023-03-08 06:04:01] [INFO ] [Nat]Absence check using 32 positive place invariants in 8 ms returned sat
[2023-03-08 06:04:01] [INFO ] [Nat]Absence check using 32 positive and 30 generalized place invariants in 41 ms returned sat
[2023-03-08 06:04:03] [INFO ] After 2331ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :45
[2023-03-08 06:04:04] [INFO ] Deduced a trap composed of 16 places in 54 ms of which 2 ms to minimize.
[2023-03-08 06:04:04] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 117 ms
[2023-03-08 06:04:04] [INFO ] Deduced a trap composed of 15 places in 105 ms of which 1 ms to minimize.
[2023-03-08 06:04:04] [INFO ] Deduced a trap composed of 19 places in 42 ms of which 1 ms to minimize.
[2023-03-08 06:04:04] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 272 ms
[2023-03-08 06:04:04] [INFO ] Deduced a trap composed of 17 places in 118 ms of which 1 ms to minimize.
[2023-03-08 06:04:04] [INFO ] Deduced a trap composed of 10 places in 98 ms of which 1 ms to minimize.
[2023-03-08 06:04:04] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 370 ms
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 32 places in 94 ms of which 0 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 26 places in 79 ms of which 1 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 239 ms
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 25 places in 102 ms of which 1 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 21 places in 85 ms of which 1 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 29 places in 90 ms of which 1 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Deduced a trap composed of 26 places in 82 ms of which 1 ms to minimize.
[2023-03-08 06:04:05] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 551 ms
[2023-03-08 06:04:06] [INFO ] Deduced a trap composed of 48 places in 127 ms of which 0 ms to minimize.
[2023-03-08 06:04:06] [INFO ] Deduced a trap composed of 68 places in 116 ms of which 1 ms to minimize.
[2023-03-08 06:04:06] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 354 ms
[2023-03-08 06:04:06] [INFO ] Deduced a trap composed of 33 places in 150 ms of which 0 ms to minimize.
[2023-03-08 06:04:07] [INFO ] Deduced a trap composed of 19 places in 110 ms of which 0 ms to minimize.
[2023-03-08 06:04:07] [INFO ] Deduced a trap composed of 32 places in 106 ms of which 0 ms to minimize.
[2023-03-08 06:04:07] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 458 ms
[2023-03-08 06:04:07] [INFO ] Deduced a trap composed of 53 places in 116 ms of which 1 ms to minimize.
[2023-03-08 06:04:07] [INFO ] Deduced a trap composed of 53 places in 113 ms of which 0 ms to minimize.
[2023-03-08 06:04:07] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 330 ms
[2023-03-08 06:04:07] [INFO ] Deduced a trap composed of 40 places in 104 ms of which 0 ms to minimize.
[2023-03-08 06:04:08] [INFO ] Deduced a trap composed of 44 places in 111 ms of which 0 ms to minimize.
[2023-03-08 06:04:08] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 292 ms
[2023-03-08 06:04:08] [INFO ] Deduced a trap composed of 33 places in 92 ms of which 1 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 10 places in 90 ms of which 1 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 24 places in 83 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 15 places in 98 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 34 places in 86 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 19 places in 49 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 18 places in 44 ms of which 1 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 11 places in 45 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Trap strengthening (SAT) tested/added 9/8 trap constraints in 913 ms
[2023-03-08 06:04:09] [INFO ] Deduced a trap composed of 11 places in 33 ms of which 0 ms to minimize.
[2023-03-08 06:04:09] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 73 ms
[2023-03-08 06:04:10] [INFO ] Deduced a trap composed of 23 places in 91 ms of which 0 ms to minimize.
[2023-03-08 06:04:10] [INFO ] Deduced a trap composed of 21 places in 39 ms of which 0 ms to minimize.
[2023-03-08 06:04:10] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 237 ms
[2023-03-08 06:04:10] [INFO ] Deduced a trap composed of 8 places in 90 ms of which 1 ms to minimize.
[2023-03-08 06:04:10] [INFO ] Deduced a trap composed of 13 places in 85 ms of which 1 ms to minimize.
[2023-03-08 06:04:10] [INFO ] Deduced a trap composed of 13 places in 58 ms of which 0 ms to minimize.
[2023-03-08 06:04:10] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 323 ms
[2023-03-08 06:04:11] [INFO ] Deduced a trap composed of 14 places in 75 ms of which 1 ms to minimize.
[2023-03-08 06:04:11] [INFO ] Deduced a trap composed of 22 places in 71 ms of which 0 ms to minimize.
[2023-03-08 06:04:11] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 211 ms
[2023-03-08 06:04:11] [INFO ] After 10289ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :45
Attempting to minimize the solution found.
Minimization took 3900 ms.
[2023-03-08 06:04:15] [INFO ] After 15142ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :45
Fused 48 Parikh solutions to 45 different solutions.
Parikh walk visited 2 properties in 9663 ms.
Support contains 58 out of 493 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 493/493 places, 441/441 transitions.
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.2 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 9 transitions
Trivial Post-agglo rules discarded 9 transitions
Performed 9 trivial Post agglomeration. Transition count delta: 9
Iterating post reduction 0 with 11 rules applied. Total rules applied 12 place count 487 transition count 427
Reduce places removed 9 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 11 rules applied. Total rules applied 23 place count 478 transition count 425
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 25 place count 476 transition count 425
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 25 place count 476 transition count 416
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 43 place count 467 transition count 416
Discarding 9 places :
Symmetric choice reduction at 3 with 9 rule applications. Total rules 52 place count 458 transition count 407
Iterating global reduction 3 with 9 rules applied. Total rules applied 61 place count 458 transition count 407
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 3 rules applied. Total rules applied 64 place count 458 transition count 404
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 65 place count 457 transition count 404
Discarding 4 places :
Symmetric choice reduction at 5 with 4 rule applications. Total rules 69 place count 453 transition count 400
Iterating global reduction 5 with 4 rules applied. Total rules applied 73 place count 453 transition count 400
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 5 with 5 rules applied. Total rules applied 78 place count 453 transition count 395
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 79 place count 452 transition count 395
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 2 Pre rules applied. Total rules applied 79 place count 452 transition count 393
Deduced a syphon composed of 2 places in 5 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 7 with 4 rules applied. Total rules applied 83 place count 450 transition count 393
Performed 71 Post agglomeration using F-continuation condition.Transition count delta: 71
Deduced a syphon composed of 71 places in 3 ms
Reduce places removed 71 places and 0 transitions.
Iterating global reduction 7 with 142 rules applied. Total rules applied 225 place count 379 transition count 322
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 7 with 1 rules applied. Total rules applied 226 place count 379 transition count 321
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -5
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 8 with 4 rules applied. Total rules applied 230 place count 377 transition count 326
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 8 with 1 rules applied. Total rules applied 231 place count 377 transition count 325
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 232 place count 376 transition count 325
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 9 with 1 rules applied. Total rules applied 233 place count 375 transition count 324
Applied a total of 233 rules in 183 ms. Remains 375 /493 variables (removed 118) and now considering 324/441 (removed 117) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 184 ms. Remains : 375/493 places, 324/441 transitions.
Incomplete random walk after 10000 steps, including 298 resets, run finished after 283 ms. (steps per millisecond=35 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 9 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 4 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1000 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 43) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 43) seen :0
Interrupted probabilistic random walk after 470279 steps, run timeout after 3001 ms. (steps per millisecond=156 ) properties seen :{}
Probabilistic random walk after 470279 steps, saw 69574 distinct states, run finished after 3002 ms. (steps per millisecond=156 ) properties seen :0
Running SMT prover for 43 properties.
// Phase 1: matrix 324 rows 375 cols
[2023-03-08 06:04:29] [INFO ] Computed 61 place invariants in 14 ms
[2023-03-08 06:04:29] [INFO ] After 310ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:43
[2023-03-08 06:04:29] [INFO ] [Nat]Absence check using 37 positive place invariants in 5 ms returned sat
[2023-03-08 06:04:30] [INFO ] [Nat]Absence check using 37 positive and 24 generalized place invariants in 326 ms returned sat
[2023-03-08 06:04:32] [INFO ] After 1393ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :43
[2023-03-08 06:04:32] [INFO ] State equation strengthened by 12 read => feed constraints.
[2023-03-08 06:04:33] [INFO ] After 1391ms SMT Verify possible using 12 Read/Feed constraints in natural domain returned unsat :0 sat :43
[2023-03-08 06:04:33] [INFO ] Deduced a trap composed of 11 places in 59 ms of which 0 ms to minimize.
[2023-03-08 06:04:33] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 88 ms
[2023-03-08 06:04:34] [INFO ] Deduced a trap composed of 19 places in 85 ms of which 0 ms to minimize.
[2023-03-08 06:04:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 118 ms
[2023-03-08 06:04:34] [INFO ] Deduced a trap composed of 9 places in 42 ms of which 1 ms to minimize.
[2023-03-08 06:04:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 78 ms
[2023-03-08 06:04:34] [INFO ] Deduced a trap composed of 4 places in 43 ms of which 0 ms to minimize.
[2023-03-08 06:04:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 70 ms
[2023-03-08 06:04:35] [INFO ] Deduced a trap composed of 4 places in 47 ms of which 0 ms to minimize.
[2023-03-08 06:04:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 83 ms
[2023-03-08 06:04:35] [INFO ] Deduced a trap composed of 17 places in 52 ms of which 0 ms to minimize.
[2023-03-08 06:04:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 87 ms
[2023-03-08 06:04:35] [INFO ] Deduced a trap composed of 9 places in 30 ms of which 1 ms to minimize.
[2023-03-08 06:04:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 62 ms
[2023-03-08 06:04:35] [INFO ] Deduced a trap composed of 4 places in 47 ms of which 0 ms to minimize.
[2023-03-08 06:04:35] [INFO ] Deduced a trap composed of 4 places in 92 ms of which 1 ms to minimize.
[2023-03-08 06:04:36] [INFO ] Deduced a trap composed of 6 places in 95 ms of which 0 ms to minimize.
[2023-03-08 06:04:36] [INFO ] Deduced a trap composed of 4 places in 68 ms of which 1 ms to minimize.
[2023-03-08 06:04:36] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 435 ms
[2023-03-08 06:04:36] [INFO ] After 4377ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :43
Attempting to minimize the solution found.
Minimization took 2277 ms.
[2023-03-08 06:04:38] [INFO ] After 9331ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :43
Parikh walk visited 7 properties in 4121 ms.
Support contains 49 out of 375 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 375/375 places, 324/324 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 375 transition count 323
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 374 transition count 323
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 374 transition count 322
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 373 transition count 322
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 6 place count 372 transition count 321
Applied a total of 6 rules in 34 ms. Remains 372 /375 variables (removed 3) and now considering 321/324 (removed 3) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 34 ms. Remains : 372/375 places, 321/324 transitions.
Incomplete random walk after 10000 steps, including 317 resets, run finished after 325 ms. (steps per millisecond=30 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 8 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 8 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Interrupted probabilistic random walk after 511554 steps, run timeout after 3001 ms. (steps per millisecond=170 ) properties seen :{}
Probabilistic random walk after 511554 steps, saw 69772 distinct states, run finished after 3001 ms. (steps per millisecond=170 ) properties seen :0
Running SMT prover for 36 properties.
// Phase 1: matrix 321 rows 372 cols
[2023-03-08 06:04:46] [INFO ] Computed 61 place invariants in 8 ms
[2023-03-08 06:04:47] [INFO ] After 244ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:36
[2023-03-08 06:04:47] [INFO ] [Nat]Absence check using 37 positive place invariants in 6 ms returned sat
[2023-03-08 06:04:47] [INFO ] [Nat]Absence check using 37 positive and 24 generalized place invariants in 29 ms returned sat
[2023-03-08 06:04:49] [INFO ] After 1508ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :36
[2023-03-08 06:04:49] [INFO ] State equation strengthened by 12 read => feed constraints.
[2023-03-08 06:04:50] [INFO ] After 1238ms SMT Verify possible using 12 Read/Feed constraints in natural domain returned unsat :0 sat :36
[2023-03-08 06:04:50] [INFO ] Deduced a trap composed of 14 places in 46 ms of which 0 ms to minimize.
[2023-03-08 06:04:50] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 81 ms
[2023-03-08 06:04:50] [INFO ] Deduced a trap composed of 14 places in 66 ms of which 0 ms to minimize.
[2023-03-08 06:04:50] [INFO ] Deduced a trap composed of 12 places in 47 ms of which 1 ms to minimize.
[2023-03-08 06:04:50] [INFO ] Deduced a trap composed of 11 places in 43 ms of which 0 ms to minimize.
[2023-03-08 06:04:50] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 221 ms
[2023-03-08 06:04:50] [INFO ] Deduced a trap composed of 9 places in 32 ms of which 1 ms to minimize.
[2023-03-08 06:04:50] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 67 ms
[2023-03-08 06:04:51] [INFO ] Deduced a trap composed of 18 places in 80 ms of which 0 ms to minimize.
[2023-03-08 06:04:51] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 105 ms
[2023-03-08 06:04:51] [INFO ] Deduced a trap composed of 4 places in 50 ms of which 0 ms to minimize.
[2023-03-08 06:04:51] [INFO ] Deduced a trap composed of 6 places in 42 ms of which 3 ms to minimize.
[2023-03-08 06:04:51] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 144 ms
[2023-03-08 06:04:51] [INFO ] Deduced a trap composed of 12 places in 79 ms of which 0 ms to minimize.
[2023-03-08 06:04:51] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 117 ms
[2023-03-08 06:04:52] [INFO ] Deduced a trap composed of 5 places in 89 ms of which 1 ms to minimize.
[2023-03-08 06:04:52] [INFO ] Deduced a trap composed of 5 places in 56 ms of which 0 ms to minimize.
[2023-03-08 06:04:52] [INFO ] Deduced a trap composed of 4 places in 44 ms of which 0 ms to minimize.
[2023-03-08 06:04:52] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 315 ms
[2023-03-08 06:04:52] [INFO ] Deduced a trap composed of 16 places in 62 ms of which 1 ms to minimize.
[2023-03-08 06:04:52] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 97 ms
[2023-03-08 06:04:53] [INFO ] After 3994ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :36
Attempting to minimize the solution found.
Minimization took 1667 ms.
[2023-03-08 06:04:54] [INFO ] After 7859ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :36
Parikh walk visited 0 properties in 3288 ms.
Support contains 49 out of 372 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 372/372 places, 321/321 transitions.
Applied a total of 0 rules in 18 ms. Remains 372 /372 variables (removed 0) and now considering 321/321 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 18 ms. Remains : 372/372 places, 321/321 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 372/372 places, 321/321 transitions.
Applied a total of 0 rules in 16 ms. Remains 372 /372 variables (removed 0) and now considering 321/321 (removed 0) transitions.
[2023-03-08 06:04:58] [INFO ] Invariant cache hit.
[2023-03-08 06:04:58] [INFO ] Implicit Places using invariants in 157 ms returned [256]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 159 ms to find 1 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 371/372 places, 321/321 transitions.
Applied a total of 0 rules in 10 ms. Remains 371 /371 variables (removed 0) and now considering 321/321 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 185 ms. Remains : 371/372 places, 321/321 transitions.
Incomplete random walk after 10000 steps, including 329 resets, run finished after 282 ms. (steps per millisecond=35 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 10 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 9 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1000 steps, including 7 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 8 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 36) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 36) seen :0
Interrupted probabilistic random walk after 606196 steps, run timeout after 3001 ms. (steps per millisecond=201 ) properties seen :{}
Probabilistic random walk after 606196 steps, saw 83196 distinct states, run finished after 3001 ms. (steps per millisecond=201 ) properties seen :0
Running SMT prover for 36 properties.
// Phase 1: matrix 321 rows 371 cols
[2023-03-08 06:05:01] [INFO ] Computed 60 place invariants in 4 ms
[2023-03-08 06:05:02] [INFO ] After 245ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:36
[2023-03-08 06:05:02] [INFO ] [Nat]Absence check using 36 positive place invariants in 6 ms returned sat
[2023-03-08 06:05:02] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 221 ms returned sat
[2023-03-08 06:05:04] [INFO ] After 1669ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :36
[2023-03-08 06:05:04] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-08 06:05:06] [INFO ] After 1561ms SMT Verify possible using 9 Read/Feed constraints in natural domain returned unsat :0 sat :36
[2023-03-08 06:05:06] [INFO ] Deduced a trap composed of 12 places in 41 ms of which 1 ms to minimize.
[2023-03-08 06:05:06] [INFO ] Deduced a trap composed of 11 places in 36 ms of which 1 ms to minimize.
[2023-03-08 06:05:06] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 134 ms
[2023-03-08 06:05:06] [INFO ] Deduced a trap composed of 17 places in 73 ms of which 2 ms to minimize.
[2023-03-08 06:05:06] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 109 ms
[2023-03-08 06:05:07] [INFO ] Deduced a trap composed of 25 places in 98 ms of which 0 ms to minimize.
[2023-03-08 06:05:07] [INFO ] Deduced a trap composed of 28 places in 80 ms of which 1 ms to minimize.
[2023-03-08 06:05:07] [INFO ] Deduced a trap composed of 23 places in 83 ms of which 0 ms to minimize.
[2023-03-08 06:05:07] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 334 ms
[2023-03-08 06:05:07] [INFO ] Deduced a trap composed of 4 places in 102 ms of which 1 ms to minimize.
[2023-03-08 06:05:07] [INFO ] Deduced a trap composed of 12 places in 95 ms of which 1 ms to minimize.
[2023-03-08 06:05:07] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 246 ms
[2023-03-08 06:05:08] [INFO ] Deduced a trap composed of 4 places in 43 ms of which 0 ms to minimize.
[2023-03-08 06:05:08] [INFO ] Deduced a trap composed of 4 places in 47 ms of which 0 ms to minimize.
[2023-03-08 06:05:08] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 139 ms
[2023-03-08 06:05:09] [INFO ] Deduced a trap composed of 4 places in 106 ms of which 0 ms to minimize.
[2023-03-08 06:05:09] [INFO ] Deduced a trap composed of 4 places in 86 ms of which 1 ms to minimize.
[2023-03-08 06:05:09] [INFO ] Deduced a trap composed of 4 places in 86 ms of which 0 ms to minimize.
[2023-03-08 06:05:09] [INFO ] Deduced a trap composed of 6 places in 64 ms of which 0 ms to minimize.
[2023-03-08 06:05:09] [INFO ] Deduced a trap composed of 4 places in 53 ms of which 0 ms to minimize.
[2023-03-08 06:05:09] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 492 ms
[2023-03-08 06:05:10] [INFO ] After 5060ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :36
Attempting to minimize the solution found.
Minimization took 1828 ms.
[2023-03-08 06:05:11] [INFO ] After 9676ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :36
Parikh walk visited 0 properties in 4665 ms.
Support contains 49 out of 371 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 371/371 places, 321/321 transitions.
Applied a total of 0 rules in 22 ms. Remains 371 /371 variables (removed 0) and now considering 321/321 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 22 ms. Remains : 371/371 places, 321/321 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 371/371 places, 321/321 transitions.
Applied a total of 0 rules in 9 ms. Remains 371 /371 variables (removed 0) and now considering 321/321 (removed 0) transitions.
[2023-03-08 06:05:16] [INFO ] Invariant cache hit.
[2023-03-08 06:05:16] [INFO ] Implicit Places using invariants in 174 ms returned []
[2023-03-08 06:05:16] [INFO ] Invariant cache hit.
[2023-03-08 06:05:16] [INFO ] State equation strengthened by 9 read => feed constraints.
[2023-03-08 06:05:17] [INFO ] Implicit Places using invariants and state equation in 406 ms returned []
Implicit Place search using SMT with State Equation took 581 ms to find 0 implicit places.
[2023-03-08 06:05:17] [INFO ] Redundant transitions in 20 ms returned []
[2023-03-08 06:05:17] [INFO ] Invariant cache hit.
[2023-03-08 06:05:17] [INFO ] Dead Transitions using invariants and state equation in 154 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 776 ms. Remains : 371/371 places, 321/321 transitions.
Applied a total of 0 rules in 10 ms. Remains 371 /371 variables (removed 0) and now considering 321/321 (removed 0) transitions.
Running SMT prover for 36 properties.
[2023-03-08 06:05:17] [INFO ] Invariant cache hit.
[2023-03-08 06:05:17] [INFO ] After 236ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:36
[2023-03-08 06:05:17] [INFO ] [Nat]Absence check using 36 positive place invariants in 6 ms returned sat
[2023-03-08 06:05:17] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 153 ms returned sat
[2023-03-08 06:05:19] [INFO ] After 1201ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :36
[2023-03-08 06:05:19] [INFO ] Deduced a trap composed of 14 places in 73 ms of which 1 ms to minimize.
[2023-03-08 06:05:19] [INFO ] Deduced a trap composed of 14 places in 67 ms of which 1 ms to minimize.
[2023-03-08 06:05:19] [INFO ] Deduced a trap composed of 25 places in 63 ms of which 1 ms to minimize.
[2023-03-08 06:05:19] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 268 ms
[2023-03-08 06:05:19] [INFO ] Deduced a trap composed of 11 places in 46 ms of which 1 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 80 ms
[2023-03-08 06:05:20] [INFO ] Deduced a trap composed of 6 places in 41 ms of which 1 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 68 ms
[2023-03-08 06:05:20] [INFO ] Deduced a trap composed of 17 places in 55 ms of which 1 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Deduced a trap composed of 17 places in 46 ms of which 0 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 208 ms
[2023-03-08 06:05:20] [INFO ] Deduced a trap composed of 12 places in 90 ms of which 0 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 121 ms
[2023-03-08 06:05:20] [INFO ] Deduced a trap composed of 8 places in 45 ms of which 0 ms to minimize.
[2023-03-08 06:05:20] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 84 ms
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 4 places in 24 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 58 ms
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 5 places in 95 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 6 places in 92 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 232 ms
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 9 places in 27 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 54 ms
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 9 places in 45 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Deduced a trap composed of 9 places in 45 ms of which 0 ms to minimize.
[2023-03-08 06:05:21] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 148 ms
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 4 places in 60 ms of which 0 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 4 places in 57 ms of which 1 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 157 ms
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 4 places in 47 ms of which 0 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 9 places in 69 ms of which 1 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 8 places in 65 ms of which 0 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 239 ms
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 21 places in 79 ms of which 0 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Deduced a trap composed of 17 places in 53 ms of which 0 ms to minimize.
[2023-03-08 06:05:22] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 173 ms
[2023-03-08 06:05:22] [INFO ] After 4442ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :36
Attempting to minimize the solution found.
Minimization took 1190 ms.
[2023-03-08 06:05:24] [INFO ] After 6440ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :36
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
FORMULA DES-PT-60b-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 34 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 29 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 441 transitions.
Computed a total of 301 stabilizing places and 293 stable transitions
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.14 ms
Starting structural reductions in SI_CTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.2 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 0 with 13 rules applied. Total rules applied 14 place count 486 transition count 424
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 27 place count 473 transition count 424
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 12 Pre rules applied. Total rules applied 27 place count 473 transition count 412
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 51 place count 461 transition count 412
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 62 place count 450 transition count 401
Iterating global reduction 2 with 11 rules applied. Total rules applied 73 place count 450 transition count 401
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 75 place count 450 transition count 399
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 75 place count 450 transition count 397
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 79 place count 448 transition count 397
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 84 place count 443 transition count 392
Iterating global reduction 3 with 5 rules applied. Total rules applied 89 place count 443 transition count 392
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 3 with 7 rules applied. Total rules applied 96 place count 443 transition count 385
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 99 place count 441 transition count 384
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 2 Pre rules applied. Total rules applied 99 place count 441 transition count 382
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 5 with 4 rules applied. Total rules applied 103 place count 439 transition count 382
Performed 68 Post agglomeration using F-continuation condition.Transition count delta: 68
Deduced a syphon composed of 68 places in 0 ms
Reduce places removed 68 places and 0 transitions.
Iterating global reduction 5 with 136 rules applied. Total rules applied 239 place count 371 transition count 314
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 241 place count 369 transition count 312
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 242 place count 368 transition count 312
Applied a total of 242 rules in 103 ms. Remains 368 /493 variables (removed 125) and now considering 312/441 (removed 129) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 105 ms. Remains : 368/493 places, 312/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 17 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 17 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 312 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.1 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 0 with 13 rules applied. Total rules applied 14 place count 486 transition count 424
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 27 place count 473 transition count 424
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 11 Pre rules applied. Total rules applied 27 place count 473 transition count 413
Deduced a syphon composed of 11 places in 1 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 2 with 22 rules applied. Total rules applied 49 place count 462 transition count 413
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 60 place count 451 transition count 402
Iterating global reduction 2 with 11 rules applied. Total rules applied 71 place count 451 transition count 402
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 73 place count 451 transition count 400
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 73 place count 451 transition count 398
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 77 place count 449 transition count 398
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 82 place count 444 transition count 393
Iterating global reduction 3 with 5 rules applied. Total rules applied 87 place count 444 transition count 393
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 3 with 7 rules applied. Total rules applied 94 place count 444 transition count 386
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 97 place count 442 transition count 385
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 2 Pre rules applied. Total rules applied 97 place count 442 transition count 383
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 5 with 4 rules applied. Total rules applied 101 place count 440 transition count 383
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 0 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 5 with 140 rules applied. Total rules applied 241 place count 370 transition count 313
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 243 place count 368 transition count 311
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 244 place count 367 transition count 311
Applied a total of 244 rules in 106 ms. Remains 367 /493 variables (removed 126) and now considering 311/441 (removed 130) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 106 ms. Remains : 367/493 places, 311/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 15 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 15 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 311 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 28 place count 480 transition count 426
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 33 place count 475 transition count 421
Iterating global reduction 1 with 5 rules applied. Total rules applied 38 place count 475 transition count 421
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 43 place count 475 transition count 416
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 44 place count 474 transition count 415
Iterating global reduction 2 with 1 rules applied. Total rules applied 45 place count 474 transition count 415
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 46 place count 474 transition count 414
Applied a total of 46 rules in 28 ms. Remains 474 /493 variables (removed 19) and now considering 414/441 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 474/493 places, 414/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 16 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 16 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 414 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 27 place count 480 transition count 427
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 31 place count 476 transition count 423
Iterating global reduction 1 with 4 rules applied. Total rules applied 35 place count 476 transition count 423
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 39 place count 476 transition count 419
Applied a total of 39 rules in 21 ms. Remains 476 /493 variables (removed 17) and now considering 419/441 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 476/493 places, 419/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 419 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 28 place count 480 transition count 426
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 32 place count 476 transition count 422
Iterating global reduction 1 with 4 rules applied. Total rules applied 36 place count 476 transition count 422
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 40 place count 476 transition count 418
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 475 transition count 417
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 475 transition count 417
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 43 place count 475 transition count 416
Applied a total of 43 rules in 38 ms. Remains 475 /493 variables (removed 18) and now considering 416/441 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 38 ms. Remains : 475/493 places, 416/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 416 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 479 transition count 427
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 479 transition count 427
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 30 place count 479 transition count 425
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 35 place count 474 transition count 420
Iterating global reduction 1 with 5 rules applied. Total rules applied 40 place count 474 transition count 420
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 45 place count 474 transition count 415
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 46 place count 473 transition count 414
Iterating global reduction 2 with 1 rules applied. Total rules applied 47 place count 473 transition count 414
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 48 place count 473 transition count 413
Applied a total of 48 rules in 74 ms. Remains 473 /493 variables (removed 20) and now considering 413/441 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 75 ms. Remains : 473/493 places, 413/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:24] [INFO ] Input system was already deterministic with 413 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 481 transition count 429
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 481 transition count 429
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 26 place count 481 transition count 427
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 30 place count 477 transition count 423
Iterating global reduction 1 with 4 rules applied. Total rules applied 34 place count 477 transition count 423
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 38 place count 477 transition count 419
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 39 place count 476 transition count 418
Iterating global reduction 2 with 1 rules applied. Total rules applied 40 place count 476 transition count 418
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 41 place count 476 transition count 417
Applied a total of 41 rules in 57 ms. Remains 476 /493 variables (removed 17) and now considering 417/441 (removed 24) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58 ms. Remains : 476/493 places, 417/441 transitions.
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:24] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 417 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 28 place count 480 transition count 426
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 33 place count 475 transition count 421
Iterating global reduction 1 with 5 rules applied. Total rules applied 38 place count 475 transition count 421
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 43 place count 475 transition count 416
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 44 place count 474 transition count 415
Iterating global reduction 2 with 1 rules applied. Total rules applied 45 place count 474 transition count 415
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 46 place count 474 transition count 414
Applied a total of 46 rules in 33 ms. Remains 474 /493 variables (removed 19) and now considering 414/441 (removed 27) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 474/493 places, 414/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 16 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 414 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 28 place count 480 transition count 426
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 32 place count 476 transition count 422
Iterating global reduction 1 with 4 rules applied. Total rules applied 36 place count 476 transition count 422
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 40 place count 476 transition count 418
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 475 transition count 417
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 475 transition count 417
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 43 place count 475 transition count 416
Applied a total of 43 rules in 32 ms. Remains 475 /493 variables (removed 18) and now considering 416/441 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 475/493 places, 416/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 416 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.1 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded 12 transitions
Performed 12 trivial Post agglomeration. Transition count delta: 12
Iterating post reduction 0 with 12 rules applied. Total rules applied 13 place count 486 transition count 425
Reduce places removed 12 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 13 rules applied. Total rules applied 26 place count 474 transition count 424
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 27 place count 473 transition count 424
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 27 place count 473 transition count 414
Deduced a syphon composed of 10 places in 1 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 47 place count 463 transition count 414
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 54 place count 456 transition count 407
Iterating global reduction 3 with 7 rules applied. Total rules applied 61 place count 456 transition count 407
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 3 rules applied. Total rules applied 64 place count 456 transition count 404
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 65 place count 455 transition count 404
Discarding 3 places :
Symmetric choice reduction at 5 with 3 rule applications. Total rules 68 place count 452 transition count 401
Iterating global reduction 5 with 3 rules applied. Total rules applied 71 place count 452 transition count 401
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 5 with 4 rules applied. Total rules applied 75 place count 452 transition count 397
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 76 place count 451 transition count 397
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 2 Pre rules applied. Total rules applied 76 place count 451 transition count 395
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 7 with 4 rules applied. Total rules applied 80 place count 449 transition count 395
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 0 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 7 with 140 rules applied. Total rules applied 220 place count 379 transition count 325
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 7 with 1 rules applied. Total rules applied 221 place count 379 transition count 324
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 223 place count 377 transition count 322
Applied a total of 223 rules in 105 ms. Remains 377 /493 variables (removed 116) and now considering 322/441 (removed 119) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 105 ms. Remains : 377/493 places, 322/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 16 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 322 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Graph (complete) has 1167 edges and 493 vertex of which 487 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.1 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 14 transitions
Trivial Post-agglo rules discarded 14 transitions
Performed 14 trivial Post agglomeration. Transition count delta: 14
Iterating post reduction 0 with 14 rules applied. Total rules applied 15 place count 486 transition count 423
Reduce places removed 14 places and 0 transitions.
Iterating post reduction 1 with 14 rules applied. Total rules applied 29 place count 472 transition count 423
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 10 Pre rules applied. Total rules applied 29 place count 472 transition count 413
Deduced a syphon composed of 10 places in 1 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 49 place count 462 transition count 413
Discarding 9 places :
Symmetric choice reduction at 2 with 9 rule applications. Total rules 58 place count 453 transition count 404
Iterating global reduction 2 with 9 rules applied. Total rules applied 67 place count 453 transition count 404
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 69 place count 453 transition count 402
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 69 place count 453 transition count 401
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 71 place count 452 transition count 401
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 75 place count 448 transition count 397
Iterating global reduction 3 with 4 rules applied. Total rules applied 79 place count 448 transition count 397
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 5 rules applied. Total rules applied 84 place count 448 transition count 392
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 85 place count 447 transition count 392
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 2 Pre rules applied. Total rules applied 85 place count 447 transition count 390
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 5 with 4 rules applied. Total rules applied 89 place count 445 transition count 390
Performed 67 Post agglomeration using F-continuation condition.Transition count delta: 67
Deduced a syphon composed of 67 places in 0 ms
Reduce places removed 67 places and 0 transitions.
Iterating global reduction 5 with 134 rules applied. Total rules applied 223 place count 378 transition count 323
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 224 place count 378 transition count 322
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 226 place count 376 transition count 320
Applied a total of 226 rules in 63 ms. Remains 376 /493 variables (removed 117) and now considering 320/441 (removed 121) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 63 ms. Remains : 376/493 places, 320/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 320 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 481 transition count 429
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 481 transition count 429
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 25 place count 481 transition count 428
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 29 place count 477 transition count 424
Iterating global reduction 1 with 4 rules applied. Total rules applied 33 place count 477 transition count 424
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 37 place count 477 transition count 420
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 38 place count 476 transition count 419
Iterating global reduction 2 with 1 rules applied. Total rules applied 39 place count 476 transition count 419
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 40 place count 476 transition count 418
Applied a total of 40 rules in 27 ms. Remains 476 /493 variables (removed 17) and now considering 418/441 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 476/493 places, 418/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 418 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 480 transition count 428
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 480 transition count 428
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 28 place count 480 transition count 426
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 32 place count 476 transition count 422
Iterating global reduction 1 with 4 rules applied. Total rules applied 36 place count 476 transition count 422
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 40 place count 476 transition count 418
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 41 place count 475 transition count 417
Iterating global reduction 2 with 1 rules applied. Total rules applied 42 place count 475 transition count 417
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 43 place count 475 transition count 416
Applied a total of 43 rules in 26 ms. Remains 475 /493 variables (removed 18) and now considering 416/441 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 475/493 places, 416/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 416 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 479 transition count 427
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 479 transition count 427
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 30 place count 479 transition count 425
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 34 place count 475 transition count 421
Iterating global reduction 1 with 4 rules applied. Total rules applied 38 place count 475 transition count 421
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 42 place count 475 transition count 417
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 43 place count 474 transition count 416
Iterating global reduction 2 with 1 rules applied. Total rules applied 44 place count 474 transition count 416
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 45 place count 474 transition count 415
Applied a total of 45 rules in 31 ms. Remains 474 /493 variables (removed 19) and now considering 415/441 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 474/493 places, 415/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 10 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 415 transitions.
Starting structural reductions in LTL mode, iteration 0 : 493/493 places, 441/441 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 479 transition count 427
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 479 transition count 427
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 30 place count 479 transition count 425
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 35 place count 474 transition count 420
Iterating global reduction 1 with 5 rules applied. Total rules applied 40 place count 474 transition count 420
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 45 place count 474 transition count 415
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 46 place count 473 transition count 414
Iterating global reduction 2 with 1 rules applied. Total rules applied 47 place count 473 transition count 414
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 48 place count 473 transition count 413
Applied a total of 48 rules in 26 ms. Remains 473 /493 variables (removed 20) and now considering 413/441 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 473/493 places, 413/441 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 11 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 12 ms
[2023-03-08 06:05:25] [INFO ] Input system was already deterministic with 413 transitions.
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 13 ms
[2023-03-08 06:05:25] [INFO ] Flatten gal took : 14 ms
[2023-03-08 06:05:25] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 06:05:25] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 493 places, 441 transitions and 1549 arcs took 2 ms.
Total runtime 88676 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DES-PT-60b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA DES-PT-60b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-60b-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-60b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-60b-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-60b-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-60b-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678256890770

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type EXCL) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 52 (type SRCH) for DES-PT-60b-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 51 (type EXCL) for DES-PT-60b-CTLFireability-00
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 49 (type FNDP) for DES-PT-60b-CTLFireability-00 (obsolete)
lola: CANCELED task # 50 (type EQUN) for DES-PT-60b-CTLFireability-00 (obsolete)
lola: LAUNCH task # 53 (type EXCL) for 7 DES-PT-60b-CTLFireability-01
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type FNDP) for DES-PT-60b-CTLFireability-00
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 53 (type EXCL) for DES-PT-60b-CTLFireability-01
lola: result : true
lola: markings : 29
lola: fired transitions : 28
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
sara: try reading problem file /home/mcc/execution/373/CTLFireability-50.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 26 (type EXCL) for 25 DES-PT-60b-CTLFireability-08
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: place or transition ordering is non-deterministic

lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 50 (type EQUN) for DES-PT-60b-CTLFireability-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 54 (type FNDP) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type SRCH) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type SRCH) for DES-PT-60b-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/373/CTLFireability-57.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/257 3/32 DES-PT-60b-CTLFireability-08 441807 m, 88361 m/sec, 1682169 t fired, .
54 EF FNDP 5/3599 0/5 DES-PT-60b-CTLFireability-00 5838608 t fired, 235354 attempts, .
57 EF STEQ 5/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/257 5/32 DES-PT-60b-CTLFireability-08 814623 m, 74563 m/sec, 3446804 t fired, .
54 EF FNDP 10/3599 0/5 DES-PT-60b-CTLFireability-00 12216745 t fired, 495099 attempts, .
57 EF STEQ 10/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 11 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/257 5/32 DES-PT-60b-CTLFireability-08 816559 m, 387 m/sec, 5213527 t fired, .
54 EF FNDP 15/3599 0/5 DES-PT-60b-CTLFireability-00 18592146 t fired, 755068 attempts, .
57 EF STEQ 15/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 16 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/257 5/32 DES-PT-60b-CTLFireability-08 818413 m, 370 m/sec, 6986236 t fired, .
54 EF FNDP 20/3599 0/5 DES-PT-60b-CTLFireability-00 24977936 t fired, 1016213 attempts, .
57 EF STEQ 20/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 21 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/257 5/32 DES-PT-60b-CTLFireability-08 820262 m, 369 m/sec, 8755791 t fired, .
54 EF FNDP 25/3599 0/5 DES-PT-60b-CTLFireability-00 31341039 t fired, 1276256 attempts, .
57 EF STEQ 25/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 26 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/257 5/32 DES-PT-60b-CTLFireability-08 835702 m, 3088 m/sec, 10538864 t fired, .
54 EF FNDP 30/3599 0/5 DES-PT-60b-CTLFireability-00 37721988 t fired, 1536518 attempts, .
57 EF STEQ 30/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 31 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/257 5/32 DES-PT-60b-CTLFireability-08 838153 m, 490 m/sec, 12318539 t fired, .
54 EF FNDP 35/3599 0/5 DES-PT-60b-CTLFireability-00 44103710 t fired, 1797155 attempts, .
57 EF STEQ 35/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 36 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/257 7/32 DES-PT-60b-CTLFireability-08 1192647 m, 70898 m/sec, 14086209 t fired, .
54 EF FNDP 40/3599 0/5 DES-PT-60b-CTLFireability-00 50480312 t fired, 2057455 attempts, .
57 EF STEQ 40/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 41 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/257 8/32 DES-PT-60b-CTLFireability-08 1438171 m, 49104 m/sec, 15830154 t fired, .
54 EF FNDP 45/3599 0/5 DES-PT-60b-CTLFireability-00 56852244 t fired, 2317924 attempts, .
57 EF STEQ 45/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 46 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 50/257 8/32 DES-PT-60b-CTLFireability-08 1439772 m, 320 m/sec, 17580427 t fired, .
54 EF FNDP 50/3599 0/5 DES-PT-60b-CTLFireability-00 63210833 t fired, 2577539 attempts, .
57 EF STEQ 50/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 51 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 55/257 8/32 DES-PT-60b-CTLFireability-08 1441332 m, 312 m/sec, 19342686 t fired, .
54 EF FNDP 55/3599 0/5 DES-PT-60b-CTLFireability-00 69574981 t fired, 2837864 attempts, .
57 EF STEQ 55/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 56 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 60/257 8/32 DES-PT-60b-CTLFireability-08 1442891 m, 311 m/sec, 21107294 t fired, .
54 EF FNDP 60/3599 0/5 DES-PT-60b-CTLFireability-00 75937895 t fired, 3098358 attempts, .
57 EF STEQ 60/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 61 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 65/257 8/32 DES-PT-60b-CTLFireability-08 1445164 m, 454 m/sec, 22882216 t fired, .
54 EF FNDP 65/3599 0/5 DES-PT-60b-CTLFireability-00 82305822 t fired, 3359086 attempts, .
57 EF STEQ 65/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 66 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 70/257 8/32 DES-PT-60b-CTLFireability-08 1459194 m, 2806 m/sec, 24642327 t fired, .
54 EF FNDP 70/3599 0/5 DES-PT-60b-CTLFireability-00 88663289 t fired, 3618273 attempts, .
57 EF STEQ 70/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 71 secs. Pages in use: 8
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 75/257 9/32 DES-PT-60b-CTLFireability-08 1603035 m, 28768 m/sec, 26404239 t fired, .
54 EF FNDP 75/3599 0/5 DES-PT-60b-CTLFireability-00 95033735 t fired, 3878985 attempts, .
57 EF STEQ 75/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 76 secs. Pages in use: 9
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 80/257 10/32 DES-PT-60b-CTLFireability-08 1954627 m, 70318 m/sec, 28160006 t fired, .
54 EF FNDP 80/3599 0/5 DES-PT-60b-CTLFireability-00 101393049 t fired, 4138909 attempts, .
57 EF STEQ 80/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 81 secs. Pages in use: 10
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 85/257 11/32 DES-PT-60b-CTLFireability-08 2068143 m, 22703 m/sec, 29917042 t fired, .
54 EF FNDP 85/3599 0/5 DES-PT-60b-CTLFireability-00 107764954 t fired, 4399895 attempts, .
57 EF STEQ 85/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 86 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 90/257 11/32 DES-PT-60b-CTLFireability-08 2069692 m, 309 m/sec, 31678746 t fired, .
54 EF FNDP 90/3599 0/5 DES-PT-60b-CTLFireability-00 114130899 t fired, 4659673 attempts, .
57 EF STEQ 90/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 91 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 95/257 11/32 DES-PT-60b-CTLFireability-08 2071247 m, 311 m/sec, 33446673 t fired, .
54 EF FNDP 95/3599 0/5 DES-PT-60b-CTLFireability-00 120507786 t fired, 4920829 attempts, .
57 EF STEQ 95/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 96 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 100/257 11/32 DES-PT-60b-CTLFireability-08 2072892 m, 329 m/sec, 35209634 t fired, .
54 EF FNDP 100/3599 0/5 DES-PT-60b-CTLFireability-00 126869292 t fired, 5180629 attempts, .
57 EF STEQ 100/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 101 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 105/257 11/32 DES-PT-60b-CTLFireability-08 2088084 m, 3038 m/sec, 36963783 t fired, .
54 EF FNDP 105/3599 0/5 DES-PT-60b-CTLFireability-00 133250288 t fired, 5442287 attempts, .
57 EF STEQ 105/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 106 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 110/257 11/32 DES-PT-60b-CTLFireability-08 2089254 m, 234 m/sec, 38716516 t fired, .
54 EF FNDP 110/3599 0/5 DES-PT-60b-CTLFireability-00 139619139 t fired, 5702016 attempts, .
57 EF STEQ 110/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 111 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 115/257 13/32 DES-PT-60b-CTLFireability-08 2399164 m, 61982 m/sec, 40484704 t fired, .
54 EF FNDP 115/3599 0/5 DES-PT-60b-CTLFireability-00 145982405 t fired, 5962336 attempts, .
57 EF STEQ 115/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 116 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 120/257 13/32 DES-PT-60b-CTLFireability-08 2444157 m, 8998 m/sec, 42241800 t fired, .
54 EF FNDP 120/3599 0/5 DES-PT-60b-CTLFireability-00 152355035 t fired, 6222330 attempts, .
57 EF STEQ 120/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 121 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 125/257 13/32 DES-PT-60b-CTLFireability-08 2446903 m, 549 m/sec, 44007095 t fired, .
54 EF FNDP 125/3599 0/5 DES-PT-60b-CTLFireability-00 158728036 t fired, 6483171 attempts, .
57 EF STEQ 125/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 126 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 130/257 13/32 DES-PT-60b-CTLFireability-08 2461666 m, 2952 m/sec, 45779033 t fired, .
54 EF FNDP 130/3599 0/5 DES-PT-60b-CTLFireability-00 165106260 t fired, 6744509 attempts, .
57 EF STEQ 130/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 131 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 135/257 14/32 DES-PT-60b-CTLFireability-08 2730435 m, 53753 m/sec, 47515834 t fired, .
54 EF FNDP 135/3599 0/5 DES-PT-60b-CTLFireability-00 171474848 t fired, 7005873 attempts, .
57 EF STEQ 135/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 136 secs. Pages in use: 14
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 140/257 15/32 DES-PT-60b-CTLFireability-08 2800346 m, 13982 m/sec, 49267492 t fired, .
54 EF FNDP 140/3599 0/5 DES-PT-60b-CTLFireability-00 177844141 t fired, 7266585 attempts, .
57 EF STEQ 140/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 141 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 145/257 15/32 DES-PT-60b-CTLFireability-08 2802722 m, 475 m/sec, 51026782 t fired, .
54 EF FNDP 145/3599 0/5 DES-PT-60b-CTLFireability-00 184208605 t fired, 7527049 attempts, .
57 EF STEQ 145/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 146 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 150/257 15/32 DES-PT-60b-CTLFireability-08 2817842 m, 3024 m/sec, 52791610 t fired, .
54 EF FNDP 150/3599 0/5 DES-PT-60b-CTLFireability-00 190575403 t fired, 7787502 attempts, .
57 EF STEQ 150/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 151 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 155/257 15/32 DES-PT-60b-CTLFireability-08 2911379 m, 18707 m/sec, 54553947 t fired, .
54 EF FNDP 155/3599 0/5 DES-PT-60b-CTLFireability-00 196943994 t fired, 8048965 attempts, .
57 EF STEQ 155/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 156 secs. Pages in use: 15
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 160/257 16/32 DES-PT-60b-CTLFireability-08 3159034 m, 49531 m/sec, 56324313 t fired, .
54 EF FNDP 160/3599 0/5 DES-PT-60b-CTLFireability-00 203303464 t fired, 8309105 attempts, .
57 EF STEQ 160/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 161 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 165/257 16/32 DES-PT-60b-CTLFireability-08 3161388 m, 470 m/sec, 58077873 t fired, .
54 EF FNDP 165/3599 0/5 DES-PT-60b-CTLFireability-00 209675763 t fired, 8569987 attempts, .
57 EF STEQ 165/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 166 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 170/257 16/32 DES-PT-60b-CTLFireability-08 3164270 m, 576 m/sec, 59836872 t fired, .
54 EF FNDP 170/3599 0/5 DES-PT-60b-CTLFireability-00 216036678 t fired, 8829578 attempts, .
57 EF STEQ 170/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 171 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 175/257 16/32 DES-PT-60b-CTLFireability-08 3178254 m, 2796 m/sec, 61595477 t fired, .
54 EF FNDP 175/3599 0/5 DES-PT-60b-CTLFireability-00 222400726 t fired, 9089651 attempts, .
57 EF STEQ 175/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 176 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 180/257 17/32 DES-PT-60b-CTLFireability-08 3270722 m, 18493 m/sec, 63349388 t fired, .
54 EF FNDP 180/3599 0/5 DES-PT-60b-CTLFireability-00 228767472 t fired, 9350571 attempts, .
57 EF STEQ 180/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 181 secs. Pages in use: 17
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 185/257 17/32 DES-PT-60b-CTLFireability-08 3360429 m, 17941 m/sec, 65094208 t fired, .
54 EF FNDP 185/3599 0/5 DES-PT-60b-CTLFireability-00 235134011 t fired, 9610580 attempts, .
57 EF STEQ 185/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 186 secs. Pages in use: 17
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 190/257 18/32 DES-PT-60b-CTLFireability-08 3450590 m, 18032 m/sec, 66823098 t fired, .
54 EF FNDP 190/3599 0/5 DES-PT-60b-CTLFireability-00 241503563 t fired, 9871093 attempts, .
57 EF STEQ 190/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 191 secs. Pages in use: 18
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 195/257 18/32 DES-PT-60b-CTLFireability-08 3529165 m, 15715 m/sec, 68561205 t fired, .
54 EF FNDP 195/3599 0/5 DES-PT-60b-CTLFireability-00 247870894 t fired, 10130481 attempts, .
57 EF STEQ 195/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 196 secs. Pages in use: 18
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 200/257 19/32 DES-PT-60b-CTLFireability-08 3618636 m, 17894 m/sec, 70292376 t fired, .
54 EF FNDP 200/3599 0/5 DES-PT-60b-CTLFireability-00 254242829 t fired, 10391499 attempts, .
57 EF STEQ 200/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 201 secs. Pages in use: 19
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 205/257 19/32 DES-PT-60b-CTLFireability-08 3632675 m, 2807 m/sec, 72020405 t fired, .
54 EF FNDP 205/3599 0/5 DES-PT-60b-CTLFireability-00 260622233 t fired, 10652563 attempts, .
57 EF STEQ 205/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 206 secs. Pages in use: 19
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 210/257 19/32 DES-PT-60b-CTLFireability-08 3710739 m, 15612 m/sec, 73742043 t fired, .
54 EF FNDP 210/3599 0/5 DES-PT-60b-CTLFireability-00 266998301 t fired, 10913899 attempts, .
57 EF STEQ 210/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 211 secs. Pages in use: 19
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 215/257 20/32 DES-PT-60b-CTLFireability-08 3906645 m, 39181 m/sec, 75473336 t fired, .
54 EF FNDP 215/3599 0/5 DES-PT-60b-CTLFireability-00 273373330 t fired, 11174660 attempts, .
57 EF STEQ 215/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 216 secs. Pages in use: 20
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 220/257 21/32 DES-PT-60b-CTLFireability-08 4145489 m, 47768 m/sec, 77214135 t fired, .
54 EF FNDP 220/3599 0/5 DES-PT-60b-CTLFireability-00 279746778 t fired, 11435789 attempts, .
57 EF STEQ 220/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 221 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 225/257 21/32 DES-PT-60b-CTLFireability-08 4147924 m, 487 m/sec, 78960031 t fired, .
54 EF FNDP 225/3599 0/5 DES-PT-60b-CTLFireability-00 286124023 t fired, 11696604 attempts, .
57 EF STEQ 225/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 226 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 230/257 21/32 DES-PT-60b-CTLFireability-08 4150880 m, 591 m/sec, 80710916 t fired, .
54 EF FNDP 230/3599 0/5 DES-PT-60b-CTLFireability-00 292501092 t fired, 11957573 attempts, .
57 EF STEQ 230/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 231 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 235/257 21/32 DES-PT-60b-CTLFireability-08 4165630 m, 2950 m/sec, 82468468 t fired, .
54 EF FNDP 235/3599 0/5 DES-PT-60b-CTLFireability-00 298872508 t fired, 12217632 attempts, .
57 EF STEQ 235/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 236 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 240/257 23/32 DES-PT-60b-CTLFireability-08 4457616 m, 58397 m/sec, 84211401 t fired, .
54 EF FNDP 240/3599 0/5 DES-PT-60b-CTLFireability-00 305254889 t fired, 12479053 attempts, .
57 EF STEQ 240/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 241 secs. Pages in use: 23
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 245/257 23/32 DES-PT-60b-CTLFireability-08 4563965 m, 21269 m/sec, 85945743 t fired, .
54 EF FNDP 245/3599 0/5 DES-PT-60b-CTLFireability-00 311631024 t fired, 12739923 attempts, .
57 EF STEQ 245/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 246 secs. Pages in use: 23
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 250/257 23/32 DES-PT-60b-CTLFireability-08 4565979 m, 402 m/sec, 87684985 t fired, .
54 EF FNDP 250/3599 0/5 DES-PT-60b-CTLFireability-00 318004243 t fired, 13001044 attempts, .
57 EF STEQ 250/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 251 secs. Pages in use: 23
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 255/257 23/32 DES-PT-60b-CTLFireability-08 4568136 m, 431 m/sec, 89435368 t fired, .
54 EF FNDP 255/3599 0/5 DES-PT-60b-CTLFireability-00 324378178 t fired, 13261772 attempts, .
57 EF STEQ 255/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 256 secs. Pages in use: 23
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 26 (type EXCL) for DES-PT-60b-CTLFireability-08 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 1 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 260/3599 0/5 DES-PT-60b-CTLFireability-00 330752525 t fired, 13522531 attempts, .
57 EF STEQ 260/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 261 secs. Pages in use: 24
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 47 (type EXCL) for 46 DES-PT-60b-CTLFireability-15
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 26 (type EXCL) for 25 DES-PT-60b-CTLFireability-08
lola: time limit : 3339 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/3339 2/5 DES-PT-60b-CTLFireability-08 375924 m, -838442 m/sec, 1407032 t fired, .
47 CTL EXCL 5/256 3/32 DES-PT-60b-CTLFireability-15 487383 m, 97476 m/sec, 1381000 t fired, .
54 EF FNDP 265/3599 0/5 DES-PT-60b-CTLFireability-00 335925398 t fired, 13734148 attempts, .
57 EF STEQ 265/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 266 secs. Pages in use: 30
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/3339 4/5 DES-PT-60b-CTLFireability-08 686095 m, 62034 m/sec, 2729337 t fired, .
47 CTL EXCL 10/238 5/32 DES-PT-60b-CTLFireability-15 816679 m, 65859 m/sec, 2799730 t fired, .
54 EF FNDP 270/3599 0/5 DES-PT-60b-CTLFireability-00 341107436 t fired, 13946153 attempts, .
57 EF STEQ 270/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 271 secs. Pages in use: 35
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/3339 5/5 DES-PT-60b-CTLFireability-08 815403 m, 25861 m/sec, 4106286 t fired, .
47 CTL EXCL 15/238 6/32 DES-PT-60b-CTLFireability-15 1086007 m, 53865 m/sec, 4279675 t fired, .
54 EF FNDP 275/3599 0/5 DES-PT-60b-CTLFireability-00 345880049 t fired, 14141482 attempts, .
57 EF STEQ 275/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 276 secs. Pages in use: 38
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/3339 5/5 DES-PT-60b-CTLFireability-08 816827 m, 284 m/sec, 5478064 t fired, .
47 CTL EXCL 20/238 8/32 DES-PT-60b-CTLFireability-15 1329681 m, 48734 m/sec, 5680687 t fired, .
54 EF FNDP 280/3599 0/5 DES-PT-60b-CTLFireability-00 350766395 t fired, 14341774 attempts, .
57 EF STEQ 280/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 281 secs. Pages in use: 40
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/3339 5/5 DES-PT-60b-CTLFireability-08 818198 m, 274 m/sec, 6784957 t fired, .
47 CTL EXCL 25/238 9/32 DES-PT-60b-CTLFireability-15 1543460 m, 42755 m/sec, 7070799 t fired, .
54 EF FNDP 285/3599 0/5 DES-PT-60b-CTLFireability-00 356046243 t fired, 14558082 attempts, .
57 EF STEQ 285/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 286 secs. Pages in use: 41
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/3339 5/5 DES-PT-60b-CTLFireability-08 819662 m, 292 m/sec, 8215846 t fired, .
47 CTL EXCL 30/238 10/32 DES-PT-60b-CTLFireability-15 1767646 m, 44837 m/sec, 8510137 t fired, .
54 EF FNDP 290/3599 0/5 DES-PT-60b-CTLFireability-00 361024750 t fired, 14761996 attempts, .
57 EF STEQ 290/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 291 secs. Pages in use: 42
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/3339 5/5 DES-PT-60b-CTLFireability-08 821805 m, 428 m/sec, 9648950 t fired, .
47 CTL EXCL 35/238 11/32 DES-PT-60b-CTLFireability-15 1985091 m, 43489 m/sec, 9922003 t fired, .
54 EF FNDP 295/3599 0/5 DES-PT-60b-CTLFireability-00 366078472 t fired, 14969059 attempts, .
57 EF STEQ 295/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 296 secs. Pages in use: 43
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 40/3339 5/5 DES-PT-60b-CTLFireability-08 835920 m, 2823 m/sec, 11060763 t fired, .
47 CTL EXCL 40/238 12/32 DES-PT-60b-CTLFireability-15 2186760 m, 40333 m/sec, 11231552 t fired, .
54 EF FNDP 300/3599 0/5 DES-PT-60b-CTLFireability-00 371197057 t fired, 15178341 attempts, .
57 EF STEQ 300/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 301 secs. Pages in use: 45
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 45/3339 5/5 DES-PT-60b-CTLFireability-08 870803 m, 6976 m/sec, 12524045 t fired, .
47 CTL EXCL 45/238 13/32 DES-PT-60b-CTLFireability-15 2406386 m, 43925 m/sec, 12642168 t fired, .
54 EF FNDP 305/3599 0/5 DES-PT-60b-CTLFireability-00 376166288 t fired, 15382039 attempts, .
57 EF STEQ 305/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 306 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 15
lola: CANCELED task # 26 (type EXCL) for DES-PT-60b-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 50/238 14/32 DES-PT-60b-CTLFireability-15 2658149 m, 50352 m/sec, 14237269 t fired, .
54 EF FNDP 310/3599 0/5 DES-PT-60b-CTLFireability-00 381980402 t fired, 15620586 attempts, .
57 EF STEQ 310/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 311 secs. Pages in use: 46
# running tasks: 4 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 55/256 16/32 DES-PT-60b-CTLFireability-15 2957119 m, 59794 m/sec, 16021441 t fired, .
54 EF FNDP 315/3599 0/5 DES-PT-60b-CTLFireability-00 388340846 t fired, 15881224 attempts, .
57 EF STEQ 315/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 316 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 60/256 17/32 DES-PT-60b-CTLFireability-15 3217459 m, 52068 m/sec, 17799381 t fired, .
54 EF FNDP 320/3599 0/5 DES-PT-60b-CTLFireability-00 394696087 t fired, 16141447 attempts, .
57 EF STEQ 320/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 321 secs. Pages in use: 46
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 65/256 18/32 DES-PT-60b-CTLFireability-15 3479523 m, 52412 m/sec, 19569008 t fired, .
54 EF FNDP 325/3599 0/5 DES-PT-60b-CTLFireability-00 401064063 t fired, 16402052 attempts, .
57 EF STEQ 325/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 326 secs. Pages in use: 47
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 70/256 20/32 DES-PT-60b-CTLFireability-15 3765793 m, 57254 m/sec, 21324141 t fired, .
54 EF FNDP 330/3599 0/5 DES-PT-60b-CTLFireability-00 407439049 t fired, 16662762 attempts, .
57 EF STEQ 330/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 331 secs. Pages in use: 50
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 75/256 21/32 DES-PT-60b-CTLFireability-15 4018391 m, 50519 m/sec, 23065827 t fired, .
54 EF FNDP 335/3599 0/5 DES-PT-60b-CTLFireability-00 413805158 t fired, 16923249 attempts, .
57 EF STEQ 335/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 336 secs. Pages in use: 51
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 80/256 22/32 DES-PT-60b-CTLFireability-15 4243282 m, 44978 m/sec, 24818511 t fired, .
54 EF FNDP 340/3599 0/5 DES-PT-60b-CTLFireability-00 420165039 t fired, 17182872 attempts, .
57 EF STEQ 340/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 341 secs. Pages in use: 52
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 85/256 24/32 DES-PT-60b-CTLFireability-15 4557871 m, 62917 m/sec, 26607256 t fired, .
54 EF FNDP 345/3599 0/5 DES-PT-60b-CTLFireability-00 426521305 t fired, 17442765 attempts, .
57 EF STEQ 345/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 346 secs. Pages in use: 55
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 90/256 25/32 DES-PT-60b-CTLFireability-15 4834524 m, 55330 m/sec, 28383061 t fired, .
54 EF FNDP 350/3599 0/5 DES-PT-60b-CTLFireability-00 432878505 t fired, 17703495 attempts, .
57 EF STEQ 350/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 351 secs. Pages in use: 56
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 95/256 27/32 DES-PT-60b-CTLFireability-15 5101908 m, 53476 m/sec, 30153846 t fired, .
54 EF FNDP 355/3599 0/5 DES-PT-60b-CTLFireability-00 439230586 t fired, 17963978 attempts, .
57 EF STEQ 355/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 356 secs. Pages in use: 58
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 100/256 28/32 DES-PT-60b-CTLFireability-15 5368456 m, 53309 m/sec, 31927954 t fired, .
54 EF FNDP 360/3599 0/5 DES-PT-60b-CTLFireability-00 445599034 t fired, 18224169 attempts, .
57 EF STEQ 360/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 361 secs. Pages in use: 60
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 105/256 29/32 DES-PT-60b-CTLFireability-15 5651600 m, 56628 m/sec, 33699886 t fired, .
54 EF FNDP 365/3599 0/5 DES-PT-60b-CTLFireability-00 451961472 t fired, 18484981 attempts, .
57 EF STEQ 365/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 366 secs. Pages in use: 61
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 110/256 31/32 DES-PT-60b-CTLFireability-15 5916933 m, 53066 m/sec, 35457666 t fired, .
54 EF FNDP 370/3599 0/5 DES-PT-60b-CTLFireability-00 458315230 t fired, 18744612 attempts, .
57 EF STEQ 370/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 371 secs. Pages in use: 64
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 115/256 32/32 DES-PT-60b-CTLFireability-15 6171166 m, 50846 m/sec, 37211811 t fired, .
54 EF FNDP 375/3599 0/5 DES-PT-60b-CTLFireability-00 464668687 t fired, 19004039 attempts, .
57 EF STEQ 375/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 376 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 47 (type EXCL) for DES-PT-60b-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 380/3599 0/5 DES-PT-60b-CTLFireability-00 471034576 t fired, 19265280 attempts, .
57 EF STEQ 380/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 381 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 44 (type EXCL) for 43 DES-PT-60b-CTLFireability-14
lola: time limit : 268 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/268 4/32 DES-PT-60b-CTLFireability-14 592808 m, 118561 m/sec, 1779203 t fired, .
54 EF FNDP 385/3599 0/5 DES-PT-60b-CTLFireability-00 477398684 t fired, 19525506 attempts, .
57 EF STEQ 385/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 386 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/268 8/32 DES-PT-60b-CTLFireability-14 1190359 m, 119510 m/sec, 3534748 t fired, .
54 EF FNDP 390/3599 0/5 DES-PT-60b-CTLFireability-00 483758354 t fired, 19786074 attempts, .
57 EF STEQ 390/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 391 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/268 11/32 DES-PT-60b-CTLFireability-14 1780543 m, 118036 m/sec, 5270750 t fired, .
54 EF FNDP 395/3599 0/5 DES-PT-60b-CTLFireability-00 490125027 t fired, 20046697 attempts, .
57 EF STEQ 395/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 396 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/268 14/32 DES-PT-60b-CTLFireability-14 2324695 m, 108830 m/sec, 7044331 t fired, .
54 EF FNDP 400/3599 0/5 DES-PT-60b-CTLFireability-00 496486725 t fired, 20307794 attempts, .
57 EF STEQ 400/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 401 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/268 16/32 DES-PT-60b-CTLFireability-14 2658276 m, 66716 m/sec, 8837535 t fired, .
54 EF FNDP 405/3599 0/5 DES-PT-60b-CTLFireability-00 502843873 t fired, 20567216 attempts, .
57 EF STEQ 405/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 406 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/268 17/32 DES-PT-60b-CTLFireability-14 2952873 m, 58919 m/sec, 10619850 t fired, .
54 EF FNDP 410/3599 0/5 DES-PT-60b-CTLFireability-00 509206824 t fired, 20827552 attempts, .
57 EF STEQ 410/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 411 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 35/268 19/32 DES-PT-60b-CTLFireability-14 3227654 m, 54956 m/sec, 12388498 t fired, .
54 EF FNDP 415/3599 0/5 DES-PT-60b-CTLFireability-00 515573086 t fired, 21088136 attempts, .
57 EF STEQ 415/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 416 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 40/268 20/32 DES-PT-60b-CTLFireability-14 3523822 m, 59233 m/sec, 14171642 t fired, .
54 EF FNDP 420/3599 0/5 DES-PT-60b-CTLFireability-00 521934150 t fired, 21347928 attempts, .
57 EF STEQ 420/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 421 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 45/268 22/32 DES-PT-60b-CTLFireability-14 3790050 m, 53245 m/sec, 15940877 t fired, .
54 EF FNDP 425/3599 0/5 DES-PT-60b-CTLFireability-00 528295754 t fired, 21607780 attempts, .
57 EF STEQ 425/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 426 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 50/268 23/32 DES-PT-60b-CTLFireability-14 4074796 m, 56949 m/sec, 17714109 t fired, .
54 EF FNDP 430/3599 0/5 DES-PT-60b-CTLFireability-00 534658480 t fired, 21868182 attempts, .
57 EF STEQ 430/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 431 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 55/268 25/32 DES-PT-60b-CTLFireability-14 4356378 m, 56316 m/sec, 19491062 t fired, .
54 EF FNDP 435/3599 0/5 DES-PT-60b-CTLFireability-00 541026870 t fired, 22128564 attempts, .
57 EF STEQ 435/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 436 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 60/268 26/32 DES-PT-60b-CTLFireability-14 4616638 m, 52052 m/sec, 21253833 t fired, .
54 EF FNDP 440/3599 0/5 DES-PT-60b-CTLFireability-00 547389981 t fired, 22389678 attempts, .
57 EF STEQ 440/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 441 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 65/268 27/32 DES-PT-60b-CTLFireability-14 4848098 m, 46292 m/sec, 23001932 t fired, .
54 EF FNDP 445/3599 0/5 DES-PT-60b-CTLFireability-00 553752030 t fired, 22650210 attempts, .
57 EF STEQ 445/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 446 secs. Pages in use: 65
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 70/268 29/32 DES-PT-60b-CTLFireability-14 5141885 m, 58757 m/sec, 24774671 t fired, .
54 EF FNDP 450/3599 0/5 DES-PT-60b-CTLFireability-00 560117725 t fired, 22910438 attempts, .
57 EF STEQ 450/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 451 secs. Pages in use: 67
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 75/268 30/32 DES-PT-60b-CTLFireability-14 5416993 m, 55021 m/sec, 26533710 t fired, .
54 EF FNDP 455/3599 0/5 DES-PT-60b-CTLFireability-00 566477835 t fired, 23170886 attempts, .
57 EF STEQ 455/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 456 secs. Pages in use: 68
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 80/268 31/32 DES-PT-60b-CTLFireability-14 5661732 m, 48947 m/sec, 28237759 t fired, .
54 EF FNDP 460/3599 0/5 DES-PT-60b-CTLFireability-00 572692832 t fired, 23425432 attempts, .
57 EF STEQ 460/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 461 secs. Pages in use: 70
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 85/268 32/32 DES-PT-60b-CTLFireability-14 5889424 m, 45538 m/sec, 29922678 t fired, .
54 EF FNDP 465/3599 0/5 DES-PT-60b-CTLFireability-00 578854693 t fired, 23677106 attempts, .
57 EF STEQ 465/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 466 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 44 (type EXCL) for DES-PT-60b-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 470/3599 0/5 DES-PT-60b-CTLFireability-00 585036267 t fired, 23930679 attempts, .
57 EF STEQ 470/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 471 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 41 (type EXCL) for 40 DES-PT-60b-CTLFireability-13
lola: time limit : 284 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for DES-PT-60b-CTLFireability-13
lola: result : false
lola: markings : 85
lola: fired transitions : 338
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 DES-PT-60b-CTLFireability-12
lola: time limit : 312 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for DES-PT-60b-CTLFireability-12
lola: result : true
lola: markings : 85
lola: fired transitions : 338
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 DES-PT-60b-CTLFireability-09
lola: time limit : 347 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/347 2/32 DES-PT-60b-CTLFireability-09 236000 m, 47200 m/sec, 1702465 t fired, .
54 EF FNDP 475/3599 0/5 DES-PT-60b-CTLFireability-00 591260937 t fired, 24185303 attempts, .
57 EF STEQ 475/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 476 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/347 3/32 DES-PT-60b-CTLFireability-09 469510 m, 46702 m/sec, 3449012 t fired, .
54 EF FNDP 480/3599 0/5 DES-PT-60b-CTLFireability-00 597624572 t fired, 24446442 attempts, .
57 EF STEQ 480/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 481 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/347 4/32 DES-PT-60b-CTLFireability-09 694899 m, 45077 m/sec, 5188641 t fired, .
54 EF FNDP 485/3599 0/5 DES-PT-60b-CTLFireability-00 603987848 t fired, 24706552 attempts, .
57 EF STEQ 485/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 486 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/347 5/32 DES-PT-60b-CTLFireability-09 901936 m, 41407 m/sec, 6931750 t fired, .
54 EF FNDP 490/3599 0/5 DES-PT-60b-CTLFireability-00 610355712 t fired, 24967213 attempts, .
57 EF STEQ 490/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 491 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/347 6/32 DES-PT-60b-CTLFireability-09 1107302 m, 41073 m/sec, 8677624 t fired, .
54 EF FNDP 495/3599 0/5 DES-PT-60b-CTLFireability-00 616722132 t fired, 25227194 attempts, .
57 EF STEQ 495/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 496 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/347 7/32 DES-PT-60b-CTLFireability-09 1309327 m, 40405 m/sec, 10414850 t fired, .
54 EF FNDP 500/3599 0/5 DES-PT-60b-CTLFireability-00 623094477 t fired, 25488430 attempts, .
57 EF STEQ 500/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 501 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/347 8/32 DES-PT-60b-CTLFireability-09 1518256 m, 41785 m/sec, 12154976 t fired, .
54 EF FNDP 505/3599 0/5 DES-PT-60b-CTLFireability-00 629457525 t fired, 25749011 attempts, .
57 EF STEQ 505/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 506 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/347 9/32 DES-PT-60b-CTLFireability-09 1724171 m, 41183 m/sec, 13896919 t fired, .
54 EF FNDP 510/3599 0/5 DES-PT-60b-CTLFireability-00 635827901 t fired, 26009879 attempts, .
57 EF STEQ 510/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 511 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/347 10/32 DES-PT-60b-CTLFireability-09 1921934 m, 39552 m/sec, 15634408 t fired, .
54 EF FNDP 515/3599 0/5 DES-PT-60b-CTLFireability-00 642188770 t fired, 26270791 attempts, .
57 EF STEQ 515/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 516 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 50/347 11/32 DES-PT-60b-CTLFireability-09 2146774 m, 44968 m/sec, 17357423 t fired, .
54 EF FNDP 520/3599 0/5 DES-PT-60b-CTLFireability-00 648562599 t fired, 26531814 attempts, .
57 EF STEQ 520/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 521 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 55/347 12/32 DES-PT-60b-CTLFireability-09 2359477 m, 42540 m/sec, 19075899 t fired, .
54 EF FNDP 525/3599 0/5 DES-PT-60b-CTLFireability-00 654937987 t fired, 26792566 attempts, .
57 EF STEQ 525/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 526 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 60/347 13/32 DES-PT-60b-CTLFireability-09 2549625 m, 38029 m/sec, 20751784 t fired, .
54 EF FNDP 530/3599 0/5 DES-PT-60b-CTLFireability-00 661111761 t fired, 27044796 attempts, .
57 EF STEQ 530/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 531 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 65/347 14/32 DES-PT-60b-CTLFireability-09 2740848 m, 38244 m/sec, 22422767 t fired, .
54 EF FNDP 535/3599 0/5 DES-PT-60b-CTLFireability-00 667303310 t fired, 27298544 attempts, .
57 EF STEQ 535/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 536 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 70/347 15/32 DES-PT-60b-CTLFireability-09 2930586 m, 37947 m/sec, 24099480 t fired, .
54 EF FNDP 540/3599 0/5 DES-PT-60b-CTLFireability-00 673494506 t fired, 27551965 attempts, .
57 EF STEQ 540/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 541 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 75/347 16/32 DES-PT-60b-CTLFireability-09 3136587 m, 41200 m/sec, 25737074 t fired, .
54 EF FNDP 545/3599 0/5 DES-PT-60b-CTLFireability-00 679658499 t fired, 27804078 attempts, .
57 EF STEQ 545/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 546 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 80/347 17/32 DES-PT-60b-CTLFireability-09 3332871 m, 39256 m/sec, 27360330 t fired, .
54 EF FNDP 550/3599 0/5 DES-PT-60b-CTLFireability-00 685789854 t fired, 28054828 attempts, .
57 EF STEQ 550/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 551 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 85/347 18/32 DES-PT-60b-CTLFireability-09 3492379 m, 31901 m/sec, 29030338 t fired, .
54 EF FNDP 555/3599 0/5 DES-PT-60b-CTLFireability-00 692036394 t fired, 28310296 attempts, .
57 EF STEQ 555/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 556 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 90/347 19/32 DES-PT-60b-CTLFireability-09 3687515 m, 39027 m/sec, 30738855 t fired, .
54 EF FNDP 560/3599 0/5 DES-PT-60b-CTLFireability-00 698370102 t fired, 28569668 attempts, .
57 EF STEQ 560/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 561 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 95/347 20/32 DES-PT-60b-CTLFireability-09 3909214 m, 44339 m/sec, 32429411 t fired, .
54 EF FNDP 565/3599 0/5 DES-PT-60b-CTLFireability-00 704604572 t fired, 28824640 attempts, .
57 EF STEQ 565/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 566 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 100/347 21/32 DES-PT-60b-CTLFireability-09 4112293 m, 40615 m/sec, 34092425 t fired, .
54 EF FNDP 570/3599 0/5 DES-PT-60b-CTLFireability-00 710766608 t fired, 29077154 attempts, .
57 EF STEQ 570/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 571 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 105/347 22/32 DES-PT-60b-CTLFireability-09 4305662 m, 38673 m/sec, 35765216 t fired, .
54 EF FNDP 575/3599 0/5 DES-PT-60b-CTLFireability-00 716935731 t fired, 29329699 attempts, .
57 EF STEQ 575/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 576 secs. Pages in use: 71
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 110/347 23/32 DES-PT-60b-CTLFireability-09 4499013 m, 38670 m/sec, 37430591 t fired, .
54 EF FNDP 580/3599 0/5 DES-PT-60b-CTLFireability-00 723103575 t fired, 29581290 attempts, .
57 EF STEQ 580/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 581 secs. Pages in use: 72
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 115/347 24/32 DES-PT-60b-CTLFireability-09 4691828 m, 38563 m/sec, 39098364 t fired, .
54 EF FNDP 585/3599 0/5 DES-PT-60b-CTLFireability-00 729263354 t fired, 29833163 attempts, .
57 EF STEQ 585/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 586 secs. Pages in use: 73
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 120/347 25/32 DES-PT-60b-CTLFireability-09 4885791 m, 38792 m/sec, 40770716 t fired, .
54 EF FNDP 590/3599 0/5 DES-PT-60b-CTLFireability-00 735469124 t fired, 30086637 attempts, .
57 EF STEQ 590/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 591 secs. Pages in use: 74
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 125/347 26/32 DES-PT-60b-CTLFireability-09 5093180 m, 41477 m/sec, 42424374 t fired, .
54 EF FNDP 595/3599 0/5 DES-PT-60b-CTLFireability-00 741655910 t fired, 30339750 attempts, .
57 EF STEQ 595/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 596 secs. Pages in use: 77
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 130/347 27/32 DES-PT-60b-CTLFireability-09 5282775 m, 37919 m/sec, 44081830 t fired, .
54 EF FNDP 600/3599 0/5 DES-PT-60b-CTLFireability-00 747862136 t fired, 30593639 attempts, .
57 EF STEQ 600/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 601 secs. Pages in use: 78
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 135/347 28/32 DES-PT-60b-CTLFireability-09 5468923 m, 37229 m/sec, 45734430 t fired, .
54 EF FNDP 605/3599 0/5 DES-PT-60b-CTLFireability-00 754052491 t fired, 30846432 attempts, .
57 EF STEQ 605/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 606 secs. Pages in use: 79
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 140/347 29/32 DES-PT-60b-CTLFireability-09 5662527 m, 38720 m/sec, 47382185 t fired, .
54 EF FNDP 610/3599 0/5 DES-PT-60b-CTLFireability-00 760248260 t fired, 31099657 attempts, .
57 EF STEQ 610/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 611 secs. Pages in use: 80
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 145/347 30/32 DES-PT-60b-CTLFireability-09 5863852 m, 40265 m/sec, 49005224 t fired, .
54 EF FNDP 615/3599 0/5 DES-PT-60b-CTLFireability-00 766450698 t fired, 31353477 attempts, .
57 EF STEQ 615/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 616 secs. Pages in use: 82
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 150/347 31/32 DES-PT-60b-CTLFireability-09 6021651 m, 31559 m/sec, 50664420 t fired, .
54 EF FNDP 620/3599 0/5 DES-PT-60b-CTLFireability-00 772685157 t fired, 31608645 attempts, .
57 EF STEQ 620/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 621 secs. Pages in use: 84
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 155/347 32/32 DES-PT-60b-CTLFireability-09 6199339 m, 35537 m/sec, 52351265 t fired, .
54 EF FNDP 625/3599 0/5 DES-PT-60b-CTLFireability-00 778925723 t fired, 31863842 attempts, .
57 EF STEQ 625/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 626 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 160/347 32/32 DES-PT-60b-CTLFireability-09 6378039 m, 35740 m/sec, 54045974 t fired, .
54 EF FNDP 630/3599 0/5 DES-PT-60b-CTLFireability-00 785182496 t fired, 32120014 attempts, .
57 EF STEQ 630/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 631 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 29 (type EXCL) for DES-PT-60b-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 635/3599 0/5 DES-PT-60b-CTLFireability-00 791472443 t fired, 32377988 attempts, .
57 EF STEQ 635/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 636 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 23 (type EXCL) for 22 DES-PT-60b-CTLFireability-07
lola: time limit : 370 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/370 2/32 DES-PT-60b-CTLFireability-07 369918 m, 73983 m/sec, 1782999 t fired, .
54 EF FNDP 640/3599 0/5 DES-PT-60b-CTLFireability-00 797679378 t fired, 32631241 attempts, .
57 EF STEQ 640/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 641 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/370 4/32 DES-PT-60b-CTLFireability-07 729131 m, 71842 m/sec, 3601424 t fired, .
54 EF FNDP 645/3599 0/5 DES-PT-60b-CTLFireability-00 803955695 t fired, 32887860 attempts, .
57 EF STEQ 645/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 646 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/370 6/32 DES-PT-60b-CTLFireability-07 1071688 m, 68511 m/sec, 5425891 t fired, .
54 EF FNDP 650/3599 0/5 DES-PT-60b-CTLFireability-00 810287253 t fired, 33146224 attempts, .
57 EF STEQ 650/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 651 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/370 8/32 DES-PT-60b-CTLFireability-07 1439576 m, 73577 m/sec, 7249923 t fired, .
54 EF FNDP 655/3599 0/5 DES-PT-60b-CTLFireability-00 816635442 t fired, 33405847 attempts, .
57 EF STEQ 655/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 656 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/370 10/32 DES-PT-60b-CTLFireability-07 1782412 m, 68567 m/sec, 9072196 t fired, .
54 EF FNDP 660/3599 0/5 DES-PT-60b-CTLFireability-00 822967292 t fired, 33665020 attempts, .
57 EF STEQ 660/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 661 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/370 13/32 DES-PT-60b-CTLFireability-07 2132449 m, 70007 m/sec, 10901118 t fired, .
54 EF FNDP 665/3599 0/5 DES-PT-60b-CTLFireability-00 829311962 t fired, 33925365 attempts, .
57 EF STEQ 665/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 666 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/370 14/32 DES-PT-60b-CTLFireability-07 2469879 m, 67486 m/sec, 12725752 t fired, .
54 EF FNDP 670/3599 0/5 DES-PT-60b-CTLFireability-00 835642016 t fired, 34184160 attempts, .
57 EF STEQ 670/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 671 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/370 16/32 DES-PT-60b-CTLFireability-07 2788318 m, 63687 m/sec, 14539454 t fired, .
54 EF FNDP 675/3599 0/5 DES-PT-60b-CTLFireability-00 841975492 t fired, 34443583 attempts, .
57 EF STEQ 675/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 676 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/370 18/32 DES-PT-60b-CTLFireability-07 3103006 m, 62937 m/sec, 16346506 t fired, .
54 EF FNDP 680/3599 0/5 DES-PT-60b-CTLFireability-00 848318046 t fired, 34703548 attempts, .
57 EF STEQ 680/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 681 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/370 20/32 DES-PT-60b-CTLFireability-07 3415427 m, 62484 m/sec, 18152906 t fired, .
54 EF FNDP 685/3599 0/5 DES-PT-60b-CTLFireability-00 854664036 t fired, 34962981 attempts, .
57 EF STEQ 685/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 686 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/370 22/32 DES-PT-60b-CTLFireability-07 3738079 m, 64530 m/sec, 19973756 t fired, .
54 EF FNDP 690/3599 0/5 DES-PT-60b-CTLFireability-00 861006596 t fired, 35222742 attempts, .
57 EF STEQ 690/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 691 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/370 23/32 DES-PT-60b-CTLFireability-07 4026250 m, 57634 m/sec, 21779963 t fired, .
54 EF FNDP 695/3599 0/5 DES-PT-60b-CTLFireability-00 867341274 t fired, 35482161 attempts, .
57 EF STEQ 695/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 696 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 65/370 25/32 DES-PT-60b-CTLFireability-07 4349570 m, 64664 m/sec, 23550097 t fired, .
54 EF FNDP 700/3599 0/5 DES-PT-60b-CTLFireability-00 873561456 t fired, 35737962 attempts, .
57 EF STEQ 700/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 701 secs. Pages in use: 85
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 70/370 27/32 DES-PT-60b-CTLFireability-07 4649374 m, 59960 m/sec, 25318551 t fired, .
54 EF FNDP 705/3599 0/5 DES-PT-60b-CTLFireability-00 879753886 t fired, 35991547 attempts, .
57 EF STEQ 705/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 706 secs. Pages in use: 87
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 75/370 29/32 DES-PT-60b-CTLFireability-07 4969915 m, 64108 m/sec, 27078222 t fired, .
54 EF FNDP 710/3599 0/5 DES-PT-60b-CTLFireability-00 885932659 t fired, 36244300 attempts, .
57 EF STEQ 710/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 711 secs. Pages in use: 89
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 80/370 31/32 DES-PT-60b-CTLFireability-07 5271457 m, 60308 m/sec, 28840209 t fired, .
54 EF FNDP 715/3599 0/5 DES-PT-60b-CTLFireability-00 892136739 t fired, 36498552 attempts, .
57 EF STEQ 715/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 716 secs. Pages in use: 91
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 23 (type EXCL) for DES-PT-60b-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 720/3599 0/5 DES-PT-60b-CTLFireability-00 898324017 t fired, 36752150 attempts, .
57 EF STEQ 720/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 721 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 20 (type EXCL) for 19 DES-PT-60b-CTLFireability-06
lola: time limit : 411 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/411 3/32 DES-PT-60b-CTLFireability-06 406611 m, 81322 m/sec, 1788714 t fired, .
54 EF FNDP 725/3599 0/5 DES-PT-60b-CTLFireability-00 904506956 t fired, 37005527 attempts, .
57 EF STEQ 725/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 726 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/411 6/32 DES-PT-60b-CTLFireability-06 886222 m, 95922 m/sec, 3591190 t fired, .
54 EF FNDP 730/3599 0/5 DES-PT-60b-CTLFireability-00 910701215 t fired, 37259189 attempts, .
57 EF STEQ 730/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 731 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/411 8/32 DES-PT-60b-CTLFireability-06 1355626 m, 93880 m/sec, 5352571 t fired, .
54 EF FNDP 735/3599 0/5 DES-PT-60b-CTLFireability-00 916870371 t fired, 37511184 attempts, .
57 EF STEQ 735/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 736 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/411 11/32 DES-PT-60b-CTLFireability-06 1824790 m, 93832 m/sec, 7115393 t fired, .
54 EF FNDP 740/3599 0/5 DES-PT-60b-CTLFireability-00 923075866 t fired, 37765498 attempts, .
57 EF STEQ 740/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 741 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/411 14/32 DES-PT-60b-CTLFireability-06 2253334 m, 85708 m/sec, 8907280 t fired, .
54 EF FNDP 745/3599 0/5 DES-PT-60b-CTLFireability-00 929262152 t fired, 38019897 attempts, .
57 EF STEQ 745/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 746 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/411 15/32 DES-PT-60b-CTLFireability-06 2536979 m, 56729 m/sec, 10708563 t fired, .
54 EF FNDP 750/3599 0/5 DES-PT-60b-CTLFireability-00 935431988 t fired, 38272640 attempts, .
57 EF STEQ 750/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 751 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/411 16/32 DES-PT-60b-CTLFireability-06 2803546 m, 53313 m/sec, 12513099 t fired, .
54 EF FNDP 755/3599 0/5 DES-PT-60b-CTLFireability-00 941612643 t fired, 38525244 attempts, .
57 EF STEQ 755/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 756 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 40/411 18/32 DES-PT-60b-CTLFireability-06 3096480 m, 58586 m/sec, 14306368 t fired, .
54 EF FNDP 760/3599 0/5 DES-PT-60b-CTLFireability-00 947796212 t fired, 38778816 attempts, .
57 EF STEQ 760/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 761 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 45/411 19/32 DES-PT-60b-CTLFireability-06 3363260 m, 53356 m/sec, 16094800 t fired, .
54 EF FNDP 765/3599 0/5 DES-PT-60b-CTLFireability-00 953984872 t fired, 39032186 attempts, .
57 EF STEQ 765/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 766 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 50/411 21/32 DES-PT-60b-CTLFireability-06 3630217 m, 53391 m/sec, 17876868 t fired, .
54 EF FNDP 770/3599 0/5 DES-PT-60b-CTLFireability-00 960154694 t fired, 39285147 attempts, .
57 EF STEQ 770/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 771 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 55/411 22/32 DES-PT-60b-CTLFireability-06 3900105 m, 53977 m/sec, 19674075 t fired, .
54 EF FNDP 775/3599 0/5 DES-PT-60b-CTLFireability-00 966345173 t fired, 39538602 attempts, .
57 EF STEQ 775/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 776 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 60/411 23/32 DES-PT-60b-CTLFireability-06 4167377 m, 53454 m/sec, 21467360 t fired, .
54 EF FNDP 780/3599 0/5 DES-PT-60b-CTLFireability-00 972547838 t fired, 39792260 attempts, .
57 EF STEQ 780/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 781 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 65/411 25/32 DES-PT-60b-CTLFireability-06 4429955 m, 52515 m/sec, 23273226 t fired, .
54 EF FNDP 785/3599 0/5 DES-PT-60b-CTLFireability-00 978828030 t fired, 40049412 attempts, .
57 EF STEQ 785/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 786 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 70/411 26/32 DES-PT-60b-CTLFireability-06 4688900 m, 51789 m/sec, 25096311 t fired, .
54 EF FNDP 790/3599 0/5 DES-PT-60b-CTLFireability-00 985183630 t fired, 40310077 attempts, .
57 EF STEQ 790/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 791 secs. Pages in use: 93
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 75/411 28/32 DES-PT-60b-CTLFireability-06 4942878 m, 50795 m/sec, 26910919 t fired, .
54 EF FNDP 795/3599 0/5 DES-PT-60b-CTLFireability-00 991543332 t fired, 40569515 attempts, .
57 EF STEQ 795/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 796 secs. Pages in use: 94
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 80/411 29/32 DES-PT-60b-CTLFireability-06 5122125 m, 35849 m/sec, 28692748 t fired, .
54 EF FNDP 800/3599 0/5 DES-PT-60b-CTLFireability-00 997886940 t fired, 40829109 attempts, .
57 EF STEQ 800/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 801 secs. Pages in use: 96
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 85/411 30/32 DES-PT-60b-CTLFireability-06 5304432 m, 36461 m/sec, 30470413 t fired, .
54 EF FNDP 805/3599 0/5 DES-PT-60b-CTLFireability-00 1004233245 t fired, 41088524 attempts, .
57 EF STEQ 805/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 806 secs. Pages in use: 98
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 90/411 31/32 DES-PT-60b-CTLFireability-06 5571922 m, 53498 m/sec, 32293546 t fired, .
54 EF FNDP 810/3599 0/5 DES-PT-60b-CTLFireability-00 1010578763 t fired, 41348095 attempts, .
57 EF STEQ 810/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 811 secs. Pages in use: 99
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 95/411 32/32 DES-PT-60b-CTLFireability-06 5849050 m, 55425 m/sec, 34125372 t fired, .
54 EF FNDP 815/3599 0/5 DES-PT-60b-CTLFireability-00 1016928045 t fired, 41608127 attempts, .
57 EF STEQ 815/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 816 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 20 (type EXCL) for DES-PT-60b-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 820/3599 0/5 DES-PT-60b-CTLFireability-00 1023274786 t fired, 41867846 attempts, .
57 EF STEQ 820/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 821 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 17 (type EXCL) for 16 DES-PT-60b-CTLFireability-04
lola: time limit : 463 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/463 1/32 DES-PT-60b-CTLFireability-04 142395 m, 28479 m/sec, 1739300 t fired, .
54 EF FNDP 825/3599 0/5 DES-PT-60b-CTLFireability-00 1029625638 t fired, 42128237 attempts, .
57 EF STEQ 825/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 826 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/463 2/32 DES-PT-60b-CTLFireability-04 274936 m, 26508 m/sec, 3492936 t fired, .
54 EF FNDP 830/3599 0/5 DES-PT-60b-CTLFireability-00 1035674083 t fired, 42376862 attempts, .
57 EF STEQ 830/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 831 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 15/463 3/32 DES-PT-60b-CTLFireability-04 409305 m, 26873 m/sec, 5273409 t fired, .
54 EF FNDP 835/3599 0/5 DES-PT-60b-CTLFireability-00 1041832513 t fired, 42628607 attempts, .
57 EF STEQ 835/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 836 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 20/463 3/32 DES-PT-60b-CTLFireability-04 542196 m, 26578 m/sec, 7025235 t fired, .
54 EF FNDP 840/3599 0/5 DES-PT-60b-CTLFireability-00 1047904760 t fired, 42877256 attempts, .
57 EF STEQ 840/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 841 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 25/463 4/32 DES-PT-60b-CTLFireability-04 664322 m, 24425 m/sec, 8761973 t fired, .
54 EF FNDP 845/3599 0/5 DES-PT-60b-CTLFireability-00 1053956159 t fired, 43124824 attempts, .
57 EF STEQ 845/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 846 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 30/463 4/32 DES-PT-60b-CTLFireability-04 786987 m, 24533 m/sec, 10550967 t fired, .
54 EF FNDP 850/3599 0/5 DES-PT-60b-CTLFireability-00 1060176164 t fired, 43379815 attempts, .
57 EF STEQ 850/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 851 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 35/463 5/32 DES-PT-60b-CTLFireability-04 905533 m, 23709 m/sec, 12357282 t fired, .
54 EF FNDP 855/3599 0/5 DES-PT-60b-CTLFireability-00 1066482751 t fired, 43639105 attempts, .
57 EF STEQ 855/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 856 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 40/463 6/32 DES-PT-60b-CTLFireability-04 1025051 m, 23903 m/sec, 14179473 t fired, .
54 EF FNDP 860/3599 0/5 DES-PT-60b-CTLFireability-00 1072835482 t fired, 43899493 attempts, .
57 EF STEQ 860/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 861 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 45/463 6/32 DES-PT-60b-CTLFireability-04 1144363 m, 23862 m/sec, 15996644 t fired, .
54 EF FNDP 865/3599 0/5 DES-PT-60b-CTLFireability-00 1079162583 t fired, 44158148 attempts, .
57 EF STEQ 865/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 866 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 50/463 7/32 DES-PT-60b-CTLFireability-04 1255704 m, 22268 m/sec, 17801479 t fired, .
54 EF FNDP 870/3599 0/5 DES-PT-60b-CTLFireability-00 1085509582 t fired, 44418882 attempts, .
57 EF STEQ 870/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 871 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 55/463 7/32 DES-PT-60b-CTLFireability-04 1381588 m, 25176 m/sec, 19621940 t fired, .
54 EF FNDP 875/3599 0/5 DES-PT-60b-CTLFireability-00 1091867119 t fired, 44678585 attempts, .
57 EF STEQ 875/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 876 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 60/463 8/32 DES-PT-60b-CTLFireability-04 1500696 m, 23821 m/sec, 21436952 t fired, .
54 EF FNDP 880/3599 0/5 DES-PT-60b-CTLFireability-00 1098220782 t fired, 44938494 attempts, .
57 EF STEQ 880/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 881 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 65/463 9/32 DES-PT-60b-CTLFireability-04 1619336 m, 23728 m/sec, 23245506 t fired, .
54 EF FNDP 885/3599 0/5 DES-PT-60b-CTLFireability-00 1104530334 t fired, 45196378 attempts, .
57 EF STEQ 885/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 886 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 70/463 9/32 DES-PT-60b-CTLFireability-04 1737804 m, 23693 m/sec, 25050524 t fired, .
54 EF FNDP 890/3599 0/5 DES-PT-60b-CTLFireability-00 1110829719 t fired, 45454603 attempts, .
57 EF STEQ 890/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 891 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 75/463 10/32 DES-PT-60b-CTLFireability-04 1853131 m, 23065 m/sec, 26852417 t fired, .
54 EF FNDP 895/3599 0/5 DES-PT-60b-CTLFireability-00 1117148197 t fired, 45713461 attempts, .
57 EF STEQ 895/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 896 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 80/463 10/32 DES-PT-60b-CTLFireability-04 1974282 m, 24230 m/sec, 28651678 t fired, .
54 EF FNDP 900/3599 0/5 DES-PT-60b-CTLFireability-00 1123457706 t fired, 45972577 attempts, .
57 EF STEQ 900/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 901 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 85/463 11/32 DES-PT-60b-CTLFireability-04 2104346 m, 26012 m/sec, 30457704 t fired, .
54 EF FNDP 905/3599 0/5 DES-PT-60b-CTLFireability-00 1129803054 t fired, 46232349 attempts, .
57 EF STEQ 905/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 906 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 90/463 12/32 DES-PT-60b-CTLFireability-04 2234146 m, 25960 m/sec, 32263408 t fired, .
54 EF FNDP 910/3599 0/5 DES-PT-60b-CTLFireability-00 1136144729 t fired, 46491164 attempts, .
57 EF STEQ 910/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 911 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 95/463 12/32 DES-PT-60b-CTLFireability-04 2355350 m, 24240 m/sec, 34059880 t fired, .
54 EF FNDP 915/3599 0/5 DES-PT-60b-CTLFireability-00 1142499807 t fired, 46751249 attempts, .
57 EF STEQ 915/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 916 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 100/463 13/32 DES-PT-60b-CTLFireability-04 2468171 m, 22564 m/sec, 35850993 t fired, .
54 EF FNDP 920/3599 0/5 DES-PT-60b-CTLFireability-00 1148830451 t fired, 47010409 attempts, .
57 EF STEQ 920/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 921 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 105/463 13/32 DES-PT-60b-CTLFireability-04 2578926 m, 22151 m/sec, 37599963 t fired, .
54 EF FNDP 925/3599 0/5 DES-PT-60b-CTLFireability-00 1154994824 t fired, 47262482 attempts, .
57 EF STEQ 925/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 926 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 110/463 14/32 DES-PT-60b-CTLFireability-04 2687233 m, 21661 m/sec, 39337304 t fired, .
54 EF FNDP 930/3599 0/5 DES-PT-60b-CTLFireability-00 1161171277 t fired, 47515612 attempts, .
57 EF STEQ 930/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 931 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 115/463 15/32 DES-PT-60b-CTLFireability-04 2797378 m, 22029 m/sec, 41077653 t fired, .
54 EF FNDP 935/3599 0/5 DES-PT-60b-CTLFireability-00 1167346916 t fired, 47768694 attempts, .
57 EF STEQ 935/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 936 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 120/463 15/32 DES-PT-60b-CTLFireability-04 2907227 m, 21969 m/sec, 42826483 t fired, .
54 EF FNDP 940/3599 0/5 DES-PT-60b-CTLFireability-00 1173523670 t fired, 48021393 attempts, .
57 EF STEQ 940/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 941 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 125/463 16/32 DES-PT-60b-CTLFireability-04 3013105 m, 21175 m/sec, 44561131 t fired, .
54 EF FNDP 945/3599 0/5 DES-PT-60b-CTLFireability-00 1179689426 t fired, 48274079 attempts, .
57 EF STEQ 945/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 946 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 130/463 16/32 DES-PT-60b-CTLFireability-04 3146922 m, 26763 m/sec, 46272868 t fired, .
54 EF FNDP 950/3599 0/5 DES-PT-60b-CTLFireability-00 1185868637 t fired, 48526885 attempts, .
57 EF STEQ 950/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 951 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 135/463 17/32 DES-PT-60b-CTLFireability-04 3268604 m, 24336 m/sec, 47983937 t fired, .
54 EF FNDP 955/3599 0/5 DES-PT-60b-CTLFireability-00 1192054930 t fired, 48780394 attempts, .
57 EF STEQ 955/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 956 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 140/463 17/32 DES-PT-60b-CTLFireability-04 3370254 m, 20330 m/sec, 49698329 t fired, .
54 EF FNDP 960/3599 0/5 DES-PT-60b-CTLFireability-00 1198248070 t fired, 49034133 attempts, .
57 EF STEQ 960/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 961 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 145/463 18/32 DES-PT-60b-CTLFireability-04 3458903 m, 17729 m/sec, 51417502 t fired, .
54 EF FNDP 965/3599 0/5 DES-PT-60b-CTLFireability-00 1204446369 t fired, 49288151 attempts, .
57 EF STEQ 965/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 966 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 150/463 18/32 DES-PT-60b-CTLFireability-04 3545792 m, 17377 m/sec, 53136863 t fired, .
54 EF FNDP 970/3599 0/5 DES-PT-60b-CTLFireability-00 1210635465 t fired, 49541605 attempts, .
57 EF STEQ 970/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 971 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 155/463 19/32 DES-PT-60b-CTLFireability-04 3668176 m, 24476 m/sec, 54904244 t fired, .
54 EF FNDP 975/3599 0/5 DES-PT-60b-CTLFireability-00 1216857892 t fired, 49796325 attempts, .
57 EF STEQ 975/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 976 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 160/463 20/32 DES-PT-60b-CTLFireability-04 3799004 m, 26165 m/sec, 56682305 t fired, .
54 EF FNDP 980/3599 0/5 DES-PT-60b-CTLFireability-00 1223065941 t fired, 50051142 attempts, .
57 EF STEQ 980/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 981 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 165/463 20/32 DES-PT-60b-CTLFireability-04 3929997 m, 26198 m/sec, 58452192 t fired, .
54 EF FNDP 985/3599 0/5 DES-PT-60b-CTLFireability-00 1229239316 t fired, 50303488 attempts, .
57 EF STEQ 985/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 986 secs. Pages in use: 100
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 170/463 21/32 DES-PT-60b-CTLFireability-04 4052785 m, 24557 m/sec, 60217974 t fired, .
54 EF FNDP 990/3599 0/5 DES-PT-60b-CTLFireability-00 1235439866 t fired, 50556830 attempts, .
57 EF STEQ 990/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 991 secs. Pages in use: 101
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 175/463 21/32 DES-PT-60b-CTLFireability-04 4164781 m, 22399 m/sec, 61973451 t fired, .
54 EF FNDP 995/3599 0/5 DES-PT-60b-CTLFireability-00 1241617319 t fired, 50809372 attempts, .
57 EF STEQ 995/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 996 secs. Pages in use: 101
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 180/463 22/32 DES-PT-60b-CTLFireability-04 4278495 m, 22742 m/sec, 63745238 t fired, .
54 EF FNDP 1000/3599 0/5 DES-PT-60b-CTLFireability-00 1247843883 t fired, 51064471 attempts, .
57 EF STEQ 1000/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1001 secs. Pages in use: 103
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 185/463 23/32 DES-PT-60b-CTLFireability-04 4389846 m, 22270 m/sec, 65512278 t fired, .
54 EF FNDP 1005/3599 0/5 DES-PT-60b-CTLFireability-00 1254072448 t fired, 51319269 attempts, .
57 EF STEQ 1005/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1006 secs. Pages in use: 105
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 190/463 23/32 DES-PT-60b-CTLFireability-04 4505168 m, 23064 m/sec, 67275267 t fired, .
54 EF FNDP 1010/3599 0/5 DES-PT-60b-CTLFireability-00 1260328060 t fired, 51575943 attempts, .
57 EF STEQ 1010/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1011 secs. Pages in use: 106
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 195/463 24/32 DES-PT-60b-CTLFireability-04 4619192 m, 22804 m/sec, 69051537 t fired, .
54 EF FNDP 1015/3599 0/5 DES-PT-60b-CTLFireability-00 1266598152 t fired, 51833198 attempts, .
57 EF STEQ 1015/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1016 secs. Pages in use: 108
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 200/463 24/32 DES-PT-60b-CTLFireability-04 4734046 m, 22970 m/sec, 70841415 t fired, .
54 EF FNDP 1020/3599 0/5 DES-PT-60b-CTLFireability-00 1272883817 t fired, 52090822 attempts, .
57 EF STEQ 1020/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1021 secs. Pages in use: 108
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 205/463 25/32 DES-PT-60b-CTLFireability-04 4844154 m, 22021 m/sec, 72625684 t fired, .
54 EF FNDP 1025/3599 0/5 DES-PT-60b-CTLFireability-00 1279182939 t fired, 52348146 attempts, .
57 EF STEQ 1025/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1026 secs. Pages in use: 109
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 210/463 25/32 DES-PT-60b-CTLFireability-04 4970363 m, 25241 m/sec, 74406157 t fired, .
54 EF FNDP 1030/3599 0/5 DES-PT-60b-CTLFireability-00 1285485873 t fired, 52606245 attempts, .
57 EF STEQ 1030/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1031 secs. Pages in use: 109
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 215/463 26/32 DES-PT-60b-CTLFireability-04 5094675 m, 24862 m/sec, 76180702 t fired, .
54 EF FNDP 1035/3599 0/5 DES-PT-60b-CTLFireability-00 1291789076 t fired, 52864429 attempts, .
57 EF STEQ 1035/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1036 secs. Pages in use: 110
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 220/463 27/32 DES-PT-60b-CTLFireability-04 5208806 m, 22826 m/sec, 77953218 t fired, .
54 EF FNDP 1040/3599 0/5 DES-PT-60b-CTLFireability-00 1298108623 t fired, 53123021 attempts, .
57 EF STEQ 1040/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1041 secs. Pages in use: 111
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 225/463 27/32 DES-PT-60b-CTLFireability-04 5318891 m, 22017 m/sec, 79726640 t fired, .
54 EF FNDP 1045/3599 0/5 DES-PT-60b-CTLFireability-00 1304414382 t fired, 53381361 attempts, .
57 EF STEQ 1045/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1046 secs. Pages in use: 111
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 230/463 28/32 DES-PT-60b-CTLFireability-04 5427749 m, 21771 m/sec, 81478577 t fired, .
54 EF FNDP 1050/3599 0/5 DES-PT-60b-CTLFireability-00 1310691043 t fired, 53638562 attempts, .
57 EF STEQ 1050/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1051 secs. Pages in use: 112
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 235/463 28/32 DES-PT-60b-CTLFireability-04 5536584 m, 21767 m/sec, 83238932 t fired, .
54 EF FNDP 1055/3599 0/5 DES-PT-60b-CTLFireability-00 1316966199 t fired, 53895654 attempts, .
57 EF STEQ 1055/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1056 secs. Pages in use: 114
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 240/463 29/32 DES-PT-60b-CTLFireability-04 5650819 m, 22847 m/sec, 84974634 t fired, .
54 EF FNDP 1060/3599 0/5 DES-PT-60b-CTLFireability-00 1323200117 t fired, 54151191 attempts, .
57 EF STEQ 1060/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1061 secs. Pages in use: 116
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 245/463 29/32 DES-PT-60b-CTLFireability-04 5776717 m, 25179 m/sec, 86698278 t fired, .
54 EF FNDP 1065/3599 0/5 DES-PT-60b-CTLFireability-00 1329488031 t fired, 54409514 attempts, .
57 EF STEQ 1065/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1066 secs. Pages in use: 116
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 250/463 30/32 DES-PT-60b-CTLFireability-04 5887839 m, 22224 m/sec, 88431456 t fired, .
54 EF FNDP 1070/3599 0/5 DES-PT-60b-CTLFireability-00 1335764304 t fired, 54665959 attempts, .
57 EF STEQ 1070/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1071 secs. Pages in use: 117
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 255/463 30/32 DES-PT-60b-CTLFireability-04 5976456 m, 17723 m/sec, 90150819 t fired, .
54 EF FNDP 1075/3599 0/5 DES-PT-60b-CTLFireability-00 1342010808 t fired, 54921769 attempts, .
57 EF STEQ 1075/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1076 secs. Pages in use: 117
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 260/463 31/32 DES-PT-60b-CTLFireability-04 6062191 m, 17147 m/sec, 91890057 t fired, .
54 EF FNDP 1080/3599 0/5 DES-PT-60b-CTLFireability-00 1348299658 t fired, 55179362 attempts, .
57 EF STEQ 1080/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1081 secs. Pages in use: 118
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 265/463 31/32 DES-PT-60b-CTLFireability-04 6169721 m, 21506 m/sec, 93662711 t fired, .
54 EF FNDP 1085/3599 0/5 DES-PT-60b-CTLFireability-00 1354567867 t fired, 55435975 attempts, .
57 EF STEQ 1085/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1086 secs. Pages in use: 118
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 270/463 32/32 DES-PT-60b-CTLFireability-04 6276391 m, 21334 m/sec, 95435663 t fired, .
54 EF FNDP 1090/3599 0/5 DES-PT-60b-CTLFireability-00 1360842906 t fired, 55692707 attempts, .
57 EF STEQ 1090/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1091 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 275/463 32/32 DES-PT-60b-CTLFireability-04 6375229 m, 19767 m/sec, 97198993 t fired, .
54 EF FNDP 1095/3599 0/5 DES-PT-60b-CTLFireability-00 1367095059 t fired, 55947977 attempts, .
57 EF STEQ 1095/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1096 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 17 (type EXCL) for DES-PT-60b-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 1100/3599 0/5 DES-PT-60b-CTLFireability-00 1373407592 t fired, 56205893 attempts, .
57 EF STEQ 1100/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1101 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 14 (type EXCL) for 13 DES-PT-60b-CTLFireability-03
lola: time limit : 499 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/499 2/32 DES-PT-60b-CTLFireability-03 245038 m, 49007 m/sec, 1771205 t fired, .
54 EF FNDP 1105/3599 0/5 DES-PT-60b-CTLFireability-00 1379651752 t fired, 56462012 attempts, .
57 EF STEQ 1105/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1106 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/499 3/32 DES-PT-60b-CTLFireability-03 482229 m, 47438 m/sec, 3545890 t fired, .
54 EF FNDP 1110/3599 0/5 DES-PT-60b-CTLFireability-00 1385903041 t fired, 56717006 attempts, .
57 EF STEQ 1110/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1111 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/499 4/32 DES-PT-60b-CTLFireability-03 711913 m, 45936 m/sec, 5318475 t fired, .
54 EF FNDP 1115/3599 0/5 DES-PT-60b-CTLFireability-00 1392185936 t fired, 56974400 attempts, .
57 EF STEQ 1115/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1116 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 20/499 5/32 DES-PT-60b-CTLFireability-03 919229 m, 41463 m/sec, 7080944 t fired, .
54 EF FNDP 1120/3599 0/5 DES-PT-60b-CTLFireability-00 1398427613 t fired, 57229511 attempts, .
57 EF STEQ 1120/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1121 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 25/499 6/32 DES-PT-60b-CTLFireability-03 1128111 m, 41776 m/sec, 8856588 t fired, .
54 EF FNDP 1125/3599 0/5 DES-PT-60b-CTLFireability-00 1404721313 t fired, 57486680 attempts, .
57 EF STEQ 1125/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1126 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 30/499 7/32 DES-PT-60b-CTLFireability-03 1336650 m, 41707 m/sec, 10622741 t fired, .
54 EF FNDP 1130/3599 0/5 DES-PT-60b-CTLFireability-00 1411010296 t fired, 57744642 attempts, .
57 EF STEQ 1130/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1131 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 35/499 8/32 DES-PT-60b-CTLFireability-03 1545748 m, 41819 m/sec, 12384225 t fired, .
54 EF FNDP 1135/3599 0/5 DES-PT-60b-CTLFireability-00 1417268541 t fired, 58000144 attempts, .
57 EF STEQ 1135/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1136 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 40/499 9/32 DES-PT-60b-CTLFireability-03 1750767 m, 41003 m/sec, 14125824 t fired, .
54 EF FNDP 1140/3599 0/5 DES-PT-60b-CTLFireability-00 1423446103 t fired, 58253622 attempts, .
57 EF STEQ 1140/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1141 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 45/499 10/32 DES-PT-60b-CTLFireability-03 1961085 m, 42063 m/sec, 15908007 t fired, .
54 EF FNDP 1145/3599 0/5 DES-PT-60b-CTLFireability-00 1429787804 t fired, 58513393 attempts, .
57 EF STEQ 1145/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1146 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 50/499 11/32 DES-PT-60b-CTLFireability-03 2185314 m, 44845 m/sec, 17686964 t fired, .
54 EF FNDP 1150/3599 0/5 DES-PT-60b-CTLFireability-00 1436138433 t fired, 58773654 attempts, .
57 EF STEQ 1150/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1151 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 55/499 12/32 DES-PT-60b-CTLFireability-03 2396565 m, 42250 m/sec, 19457516 t fired, .
54 EF FNDP 1155/3599 0/5 DES-PT-60b-CTLFireability-00 1442495846 t fired, 59033291 attempts, .
57 EF STEQ 1155/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1156 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 60/499 13/32 DES-PT-60b-CTLFireability-03 2594878 m, 39662 m/sec, 21229104 t fired, .
54 EF FNDP 1160/3599 0/5 DES-PT-60b-CTLFireability-00 1448854513 t fired, 59293564 attempts, .
57 EF STEQ 1160/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1161 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 65/499 14/32 DES-PT-60b-CTLFireability-03 2792678 m, 39560 m/sec, 22994988 t fired, .
54 EF FNDP 1165/3599 0/5 DES-PT-60b-CTLFireability-00 1455207067 t fired, 59553669 attempts, .
57 EF STEQ 1165/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1166 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 70/499 15/32 DES-PT-60b-CTLFireability-03 2988694 m, 39203 m/sec, 24758703 t fired, .
54 EF FNDP 1170/3599 0/5 DES-PT-60b-CTLFireability-00 1461546590 t fired, 59812745 attempts, .
57 EF STEQ 1170/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1171 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 75/499 17/32 DES-PT-60b-CTLFireability-03 3211489 m, 44559 m/sec, 26486678 t fired, .
54 EF FNDP 1175/3599 0/5 DES-PT-60b-CTLFireability-00 1467873828 t fired, 60071379 attempts, .
57 EF STEQ 1175/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1176 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 80/499 18/32 DES-PT-60b-CTLFireability-03 3403079 m, 38318 m/sec, 28214084 t fired, .
54 EF FNDP 1180/3599 0/5 DES-PT-60b-CTLFireability-00 1474185646 t fired, 60328917 attempts, .
57 EF STEQ 1180/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1181 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 85/499 18/32 DES-PT-60b-CTLFireability-03 3563251 m, 32034 m/sec, 29947859 t fired, .
54 EF FNDP 1185/3599 0/5 DES-PT-60b-CTLFireability-00 1480494606 t fired, 60587436 attempts, .
57 EF STEQ 1185/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1186 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 90/499 20/32 DES-PT-60b-CTLFireability-03 3796537 m, 46657 m/sec, 31720077 t fired, .
54 EF FNDP 1190/3599 0/5 DES-PT-60b-CTLFireability-00 1486794034 t fired, 60845705 attempts, .
57 EF STEQ 1190/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1191 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 95/499 21/32 DES-PT-60b-CTLFireability-03 4022335 m, 45159 m/sec, 33480834 t fired, .
54 EF FNDP 1195/3599 0/5 DES-PT-60b-CTLFireability-00 1493073767 t fired, 61103055 attempts, .
57 EF STEQ 1195/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1196 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 100/499 22/32 DES-PT-60b-CTLFireability-03 4228471 m, 41227 m/sec, 35245772 t fired, .
54 EF FNDP 1200/3599 0/5 DES-PT-60b-CTLFireability-00 1499389762 t fired, 61361831 attempts, .
57 EF STEQ 1200/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1201 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 105/499 23/32 DES-PT-60b-CTLFireability-03 4426585 m, 39622 m/sec, 36994897 t fired, .
54 EF FNDP 1205/3599 0/5 DES-PT-60b-CTLFireability-00 1505650821 t fired, 61618841 attempts, .
57 EF STEQ 1205/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1206 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 110/499 24/32 DES-PT-60b-CTLFireability-03 4633496 m, 41382 m/sec, 38744678 t fired, .
54 EF FNDP 1210/3599 0/5 DES-PT-60b-CTLFireability-00 1511922386 t fired, 61876068 attempts, .
57 EF STEQ 1210/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1211 secs. Pages in use: 119
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 115/499 25/32 DES-PT-60b-CTLFireability-03 4834202 m, 40141 m/sec, 40501499 t fired, .
54 EF FNDP 1215/3599 0/5 DES-PT-60b-CTLFireability-00 1518204973 t fired, 62133883 attempts, .
57 EF STEQ 1215/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1216 secs. Pages in use: 120
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 120/499 26/32 DES-PT-60b-CTLFireability-03 5049650 m, 43089 m/sec, 42240586 t fired, .
54 EF FNDP 1220/3599 0/5 DES-PT-60b-CTLFireability-00 1524459502 t fired, 62389384 attempts, .
57 EF STEQ 1220/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1221 secs. Pages in use: 121
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 125/499 27/32 DES-PT-60b-CTLFireability-03 5248126 m, 39695 m/sec, 43964599 t fired, .
54 EF FNDP 1225/3599 0/5 DES-PT-60b-CTLFireability-00 1530698237 t fired, 62644544 attempts, .
57 EF STEQ 1225/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1226 secs. Pages in use: 122
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 130/499 28/32 DES-PT-60b-CTLFireability-03 5440455 m, 38465 m/sec, 45695737 t fired, .
54 EF FNDP 1230/3599 0/5 DES-PT-60b-CTLFireability-00 1536970057 t fired, 62900627 attempts, .
57 EF STEQ 1230/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1231 secs. Pages in use: 124
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 135/499 29/32 DES-PT-60b-CTLFireability-03 5633406 m, 38590 m/sec, 47422869 t fired, .
54 EF FNDP 1235/3599 0/5 DES-PT-60b-CTLFireability-00 1543236019 t fired, 63157945 attempts, .
57 EF STEQ 1235/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1236 secs. Pages in use: 126
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 140/499 30/32 DES-PT-60b-CTLFireability-03 5852323 m, 43783 m/sec, 49134230 t fired, .
54 EF FNDP 1240/3599 0/5 DES-PT-60b-CTLFireability-00 1549561693 t fired, 63417442 attempts, .
57 EF STEQ 1240/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1241 secs. Pages in use: 127
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 145/499 31/32 DES-PT-60b-CTLFireability-03 6018316 m, 33198 m/sec, 50869409 t fired, .
54 EF FNDP 1245/3599 0/5 DES-PT-60b-CTLFireability-00 1555901145 t fired, 63676587 attempts, .
57 EF STEQ 1245/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1246 secs. Pages in use: 128
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 150/499 32/32 DES-PT-60b-CTLFireability-03 6204095 m, 37155 m/sec, 52634596 t fired, .
54 EF FNDP 1250/3599 0/5 DES-PT-60b-CTLFireability-00 1562250685 t fired, 63935816 attempts, .
57 EF STEQ 1250/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1251 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 14 (type EXCL) for DES-PT-60b-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 1255/3599 0/5 DES-PT-60b-CTLFireability-00 1568605844 t fired, 64195978 attempts, .
57 EF STEQ 1255/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1256 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 11 (type EXCL) for 10 DES-PT-60b-CTLFireability-02
lola: time limit : 586 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/586 3/32 DES-PT-60b-CTLFireability-02 406731 m, 81346 m/sec, 1717751 t fired, .
54 EF FNDP 1260/3599 0/5 DES-PT-60b-CTLFireability-00 1574961249 t fired, 64455690 attempts, .
57 EF STEQ 1260/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1261 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/586 4/32 DES-PT-60b-CTLFireability-02 750868 m, 68827 m/sec, 3458237 t fired, .
54 EF FNDP 1265/3599 0/5 DES-PT-60b-CTLFireability-00 1581310194 t fired, 64714857 attempts, .
57 EF STEQ 1265/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1266 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/586 6/32 DES-PT-60b-CTLFireability-02 1127371 m, 75300 m/sec, 5185177 t fired, .
54 EF FNDP 1270/3599 0/5 DES-PT-60b-CTLFireability-00 1587484877 t fired, 64967163 attempts, .
57 EF STEQ 1270/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1271 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/586 8/32 DES-PT-60b-CTLFireability-02 1441381 m, 62802 m/sec, 6920384 t fired, .
54 EF FNDP 1275/3599 0/5 DES-PT-60b-CTLFireability-00 1593638004 t fired, 65219227 attempts, .
57 EF STEQ 1275/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1276 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/586 9/32 DES-PT-60b-CTLFireability-02 1734242 m, 58572 m/sec, 8665626 t fired, .
54 EF FNDP 1280/3599 0/5 DES-PT-60b-CTLFireability-00 1598919313 t fired, 65435386 attempts, .
57 EF STEQ 1280/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1281 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/586 11/32 DES-PT-60b-CTLFireability-02 2038292 m, 60810 m/sec, 10400620 t fired, .
54 EF FNDP 1285/3599 0/5 DES-PT-60b-CTLFireability-00 1605247081 t fired, 65694941 attempts, .
57 EF STEQ 1285/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1286 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 35/586 12/32 DES-PT-60b-CTLFireability-02 2405615 m, 73464 m/sec, 12101355 t fired, .
54 EF FNDP 1290/3599 0/5 DES-PT-60b-CTLFireability-00 1611505637 t fired, 65950899 attempts, .
57 EF STEQ 1290/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1291 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 40/586 14/32 DES-PT-60b-CTLFireability-02 2714084 m, 61693 m/sec, 13810590 t fired, .
54 EF FNDP 1295/3599 0/5 DES-PT-60b-CTLFireability-00 1617758948 t fired, 66207617 attempts, .
57 EF STEQ 1295/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1296 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 45/586 15/32 DES-PT-60b-CTLFireability-02 3003544 m, 57892 m/sec, 15532186 t fired, .
54 EF FNDP 1300/3599 0/5 DES-PT-60b-CTLFireability-00 1624031541 t fired, 66464019 attempts, .
57 EF STEQ 1300/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1301 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 50/586 17/32 DES-PT-60b-CTLFireability-02 3296880 m, 58667 m/sec, 17242182 t fired, .
54 EF FNDP 1305/3599 0/5 DES-PT-60b-CTLFireability-00 1630284273 t fired, 66720443 attempts, .
57 EF STEQ 1305/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1306 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 55/586 19/32 DES-PT-60b-CTLFireability-02 3664215 m, 73467 m/sec, 18922377 t fired, .
54 EF FNDP 1310/3599 0/5 DES-PT-60b-CTLFireability-00 1636528839 t fired, 66975703 attempts, .
57 EF STEQ 1310/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1311 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 60/586 20/32 DES-PT-60b-CTLFireability-02 3991505 m, 65458 m/sec, 20616278 t fired, .
54 EF FNDP 1315/3599 0/5 DES-PT-60b-CTLFireability-00 1642774580 t fired, 67231456 attempts, .
57 EF STEQ 1315/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1316 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 65/586 22/32 DES-PT-60b-CTLFireability-02 4309784 m, 63655 m/sec, 22317679 t fired, .
54 EF FNDP 1320/3599 0/5 DES-PT-60b-CTLFireability-00 1649009245 t fired, 67486264 attempts, .
57 EF STEQ 1320/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1321 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 70/586 23/32 DES-PT-60b-CTLFireability-02 4618381 m, 61719 m/sec, 24007710 t fired, .
54 EF FNDP 1325/3599 0/5 DES-PT-60b-CTLFireability-00 1655239882 t fired, 67741266 attempts, .
57 EF STEQ 1325/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1326 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 75/586 25/32 DES-PT-60b-CTLFireability-02 4927021 m, 61728 m/sec, 25650287 t fired, .
54 EF FNDP 1330/3599 0/5 DES-PT-60b-CTLFireability-00 1661044902 t fired, 67978997 attempts, .
57 EF STEQ 1330/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1331 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 80/586 26/32 DES-PT-60b-CTLFireability-02 5163242 m, 47244 m/sec, 27030728 t fired, .
54 EF FNDP 1335/3599 0/5 DES-PT-60b-CTLFireability-00 1667252519 t fired, 68232808 attempts, .
57 EF STEQ 1335/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1336 secs. Pages in use: 129
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 85/586 28/32 DES-PT-60b-CTLFireability-02 5498072 m, 66966 m/sec, 28704440 t fired, .
54 EF FNDP 1340/3599 0/5 DES-PT-60b-CTLFireability-00 1673498843 t fired, 68488200 attempts, .
57 EF STEQ 1340/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1341 secs. Pages in use: 131
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 90/586 29/32 DES-PT-60b-CTLFireability-02 5771042 m, 54594 m/sec, 30406268 t fired, .
54 EF FNDP 1345/3599 0/5 DES-PT-60b-CTLFireability-00 1679717351 t fired, 68742512 attempts, .
57 EF STEQ 1345/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1346 secs. Pages in use: 132
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 95/586 30/32 DES-PT-60b-CTLFireability-02 6048072 m, 55406 m/sec, 32124426 t fired, .
54 EF FNDP 1350/3599 0/5 DES-PT-60b-CTLFireability-00 1685982296 t fired, 68998696 attempts, .
57 EF STEQ 1350/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1351 secs. Pages in use: 134
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 100/586 32/32 DES-PT-60b-CTLFireability-02 6292995 m, 48984 m/sec, 33838633 t fired, .
54 EF FNDP 1355/3599 0/5 DES-PT-60b-CTLFireability-00 1692223157 t fired, 69255013 attempts, .
57 EF STEQ 1355/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1356 secs. Pages in use: 136
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 11 (type EXCL) for DES-PT-60b-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-60b-CTLFireability-00: CONJ 0 1 2 0 7 0 0 0
DES-PT-60b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
DES-PT-60b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DES-PT-60b-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 EF FNDP 1360/3599 0/5 DES-PT-60b-CTLFireability-00 1698502408 t fired, 69511791 attempts, .
57 EF STEQ 1360/3599 0/5 DES-PT-60b-CTLFireability-00 sara is running.

Time elapsed: 1361 secs. Pages in use: 136
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 58 (type EXCL) for 0 DES-PT-60b-CTLFireability-00
lola: time limit : 746 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for DES-PT-60b-CTLFireability-00
lola: result : true
lola: markings : 43789
lola: fired transitions : 51121
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 54 (type FNDP) for DES-PT-60b-CTLFireability-00 (obsolete)
lola: CANCELED task # 57 (type EQUN) for DES-PT-60b-CTLFireability-00 (obsolete)
lola: LAUNCH task # 56 (type EXCL) for 34 DES-PT-60b-CTLFireability-11
lola: time limit : 1119 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type FNDP) for DES-PT-60b-CTLFireability-00
lola: result : unknown
lola: fired transitions : 1698708688
lola: tried executions : 69520216
lola: time used : 1361.000000
lola: memory pages used : 0
lola: FINISHED task # 57 (type EQUN) for DES-PT-60b-CTLFireability-00
lola: result : unknown
lola: FINISHED task # 56 (type EXCL) for DES-PT-60b-CTLFireability-11
lola: result : false
lola: markings : 515149
lola: fired transitions : 804095
lola: time used : 2.000000
lola: memory pages used : 5
lola: LAUNCH task # 32 (type EXCL) for 31 DES-PT-60b-CTLFireability-10
lola: time limit : 2236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for DES-PT-60b-CTLFireability-10
lola: result : true
lola: markings : 25
lola: fired transitions : 51
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-60b-CTLFireability-00: CONJ true CONJ
DES-PT-60b-CTLFireability-01: F false state space / EG
DES-PT-60b-CTLFireability-02: CTL unknown AGGR
DES-PT-60b-CTLFireability-03: CTL unknown AGGR
DES-PT-60b-CTLFireability-04: CTL unknown AGGR
DES-PT-60b-CTLFireability-06: CTL unknown AGGR
DES-PT-60b-CTLFireability-07: CTL unknown AGGR
DES-PT-60b-CTLFireability-08: CTL unknown AGGR
DES-PT-60b-CTLFireability-09: CTL unknown AGGR
DES-PT-60b-CTLFireability-10: CTL true CTL model checker
DES-PT-60b-CTLFireability-11: SP ECTL true LTL model checker
DES-PT-60b-CTLFireability-12: CTL true CTL model checker
DES-PT-60b-CTLFireability-13: CTL false CTL model checker
DES-PT-60b-CTLFireability-14: CTL unknown AGGR
DES-PT-60b-CTLFireability-15: CTL unknown AGGR


Time elapsed: 1364 secs. Pages in use: 136