About the Execution of LoLa+red for DES-PT-40b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
6211.172 | 849665.00 | 2221142.00 | 2350.40 | ?F?TFT??TF?FT??T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478300466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DES-PT-40b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478300466
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 5.8K Feb 26 15:36 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K Feb 26 15:36 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 15:36 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 15:36 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 15:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 15:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 15:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 15:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 115K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-40b-CTLFireability-00
FORMULA_NAME DES-PT-40b-CTLFireability-01
FORMULA_NAME DES-PT-40b-CTLFireability-02
FORMULA_NAME DES-PT-40b-CTLFireability-03
FORMULA_NAME DES-PT-40b-CTLFireability-04
FORMULA_NAME DES-PT-40b-CTLFireability-05
FORMULA_NAME DES-PT-40b-CTLFireability-06
FORMULA_NAME DES-PT-40b-CTLFireability-07
FORMULA_NAME DES-PT-40b-CTLFireability-08
FORMULA_NAME DES-PT-40b-CTLFireability-09
FORMULA_NAME DES-PT-40b-CTLFireability-10
FORMULA_NAME DES-PT-40b-CTLFireability-11
FORMULA_NAME DES-PT-40b-CTLFireability-12
FORMULA_NAME DES-PT-40b-CTLFireability-13
FORMULA_NAME DES-PT-40b-CTLFireability-14
FORMULA_NAME DES-PT-40b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678253183743
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-40b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 05:26:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 05:26:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 05:26:25] [INFO ] Load time of PNML (sax parser for PT used): 59 ms
[2023-03-08 05:26:25] [INFO ] Transformed 439 places.
[2023-03-08 05:26:25] [INFO ] Transformed 390 transitions.
[2023-03-08 05:26:25] [INFO ] Found NUPN structural information;
[2023-03-08 05:26:25] [INFO ] Parsed PT model containing 439 places and 390 transitions and 1303 arcs in 122 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 156 out of 439 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 439/439 places, 390/390 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 436 transition count 390
Discarding 14 places :
Symmetric choice reduction at 1 with 14 rule applications. Total rules 17 place count 422 transition count 376
Iterating global reduction 1 with 14 rules applied. Total rules applied 31 place count 422 transition count 376
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 34 place count 419 transition count 373
Iterating global reduction 1 with 3 rules applied. Total rules applied 37 place count 419 transition count 373
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 39 place count 419 transition count 371
Applied a total of 39 rules in 71 ms. Remains 419 /439 variables (removed 20) and now considering 371/390 (removed 19) transitions.
// Phase 1: matrix 371 rows 419 cols
[2023-03-08 05:26:25] [INFO ] Computed 62 place invariants in 38 ms
[2023-03-08 05:26:25] [INFO ] Implicit Places using invariants in 348 ms returned []
[2023-03-08 05:26:25] [INFO ] Invariant cache hit.
[2023-03-08 05:26:26] [INFO ] Implicit Places using invariants and state equation in 348 ms returned []
Implicit Place search using SMT with State Equation took 721 ms to find 0 implicit places.
[2023-03-08 05:26:26] [INFO ] Invariant cache hit.
[2023-03-08 05:26:26] [INFO ] Dead Transitions using invariants and state equation in 205 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 419/439 places, 371/390 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 998 ms. Remains : 419/439 places, 371/390 transitions.
Support contains 156 out of 419 places after structural reductions.
[2023-03-08 05:26:26] [INFO ] Flatten gal took : 57 ms
[2023-03-08 05:26:26] [INFO ] Flatten gal took : 25 ms
[2023-03-08 05:26:26] [INFO ] Input system was already deterministic with 371 transitions.
Incomplete random walk after 10000 steps, including 86 resets, run finished after 452 ms. (steps per millisecond=22 ) properties (out of 118) seen :63
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 55) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 55) seen :0
Running SMT prover for 55 properties.
[2023-03-08 05:26:27] [INFO ] Invariant cache hit.
[2023-03-08 05:26:28] [INFO ] [Real]Absence check using 33 positive place invariants in 9 ms returned sat
[2023-03-08 05:26:28] [INFO ] [Real]Absence check using 33 positive and 29 generalized place invariants in 22 ms returned sat
[2023-03-08 05:26:28] [INFO ] After 535ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:55
[2023-03-08 05:26:28] [INFO ] [Nat]Absence check using 33 positive place invariants in 8 ms returned sat
[2023-03-08 05:26:28] [INFO ] [Nat]Absence check using 33 positive and 29 generalized place invariants in 21 ms returned sat
[2023-03-08 05:26:31] [INFO ] After 2183ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :53
[2023-03-08 05:26:31] [INFO ] Deduced a trap composed of 10 places in 118 ms of which 5 ms to minimize.
[2023-03-08 05:26:31] [INFO ] Deduced a trap composed of 8 places in 122 ms of which 1 ms to minimize.
[2023-03-08 05:26:31] [INFO ] Deduced a trap composed of 35 places in 101 ms of which 0 ms to minimize.
[2023-03-08 05:26:31] [INFO ] Deduced a trap composed of 33 places in 105 ms of which 1 ms to minimize.
[2023-03-08 05:26:31] [INFO ] Deduced a trap composed of 14 places in 105 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 16 places in 95 ms of which 0 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 35 places in 85 ms of which 0 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 11 places in 90 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 22 places in 84 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 13 places in 30 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 16 places in 34 ms of which 0 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 12 places in 29 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Trap strengthening (SAT) tested/added 13/12 trap constraints in 1359 ms
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 12 places in 30 ms of which 1 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 82 ms
[2023-03-08 05:26:32] [INFO ] Deduced a trap composed of 22 places in 40 ms of which 0 ms to minimize.
[2023-03-08 05:26:32] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 75 ms
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 23 places in 78 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 35 places in 79 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 54 places in 79 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 320 ms
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 19 places in 61 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 20 places in 57 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 22 places in 47 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 24 places in 51 ms of which 1 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 31 places in 52 ms of which 0 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 402 ms
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 18 places in 54 ms of which 1 ms to minimize.
[2023-03-08 05:26:33] [INFO ] Deduced a trap composed of 17 places in 64 ms of which 1 ms to minimize.
[2023-03-08 05:26:34] [INFO ] Deduced a trap composed of 14 places in 67 ms of which 0 ms to minimize.
[2023-03-08 05:26:34] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 3 trap constraints in 236 ms
[2023-03-08 05:26:34] [INFO ] Deduced a trap composed of 9 places in 43 ms of which 0 ms to minimize.
[2023-03-08 05:26:34] [INFO ] Deduced a trap composed of 10 places in 38 ms of which 1 ms to minimize.
[2023-03-08 05:26:34] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 138 ms
[2023-03-08 05:26:34] [INFO ] Deduced a trap composed of 37 places in 83 ms of which 0 ms to minimize.
[2023-03-08 05:26:34] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 116 ms
[2023-03-08 05:26:35] [INFO ] Deduced a trap composed of 15 places in 73 ms of which 0 ms to minimize.
[2023-03-08 05:26:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 111 ms
[2023-03-08 05:26:35] [INFO ] Deduced a trap composed of 46 places in 101 ms of which 1 ms to minimize.
[2023-03-08 05:26:35] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 152 ms
[2023-03-08 05:26:36] [INFO ] Deduced a trap composed of 22 places in 36 ms of which 0 ms to minimize.
[2023-03-08 05:26:36] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 78 ms
[2023-03-08 05:26:36] [INFO ] Deduced a trap composed of 31 places in 93 ms of which 1 ms to minimize.
[2023-03-08 05:26:36] [INFO ] Deduced a trap composed of 36 places in 93 ms of which 0 ms to minimize.
[2023-03-08 05:26:36] [INFO ] Deduced a trap composed of 36 places in 73 ms of which 1 ms to minimize.
[2023-03-08 05:26:37] [INFO ] Deduced a trap composed of 38 places in 71 ms of which 1 ms to minimize.
[2023-03-08 05:26:37] [INFO ] Deduced a trap composed of 39 places in 70 ms of which 0 ms to minimize.
[2023-03-08 05:26:37] [INFO ] Deduced a trap composed of 34 places in 65 ms of which 1 ms to minimize.
[2023-03-08 05:26:37] [INFO ] Trap strengthening (SAT) tested/added 7/6 trap constraints in 570 ms
[2023-03-08 05:26:37] [INFO ] Deduced a trap composed of 14 places in 46 ms of which 0 ms to minimize.
[2023-03-08 05:26:37] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 99 ms
[2023-03-08 05:26:38] [INFO ] Deduced a trap composed of 28 places in 50 ms of which 0 ms to minimize.
[2023-03-08 05:26:38] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 95 ms
[2023-03-08 05:26:38] [INFO ] Deduced a trap composed of 46 places in 95 ms of which 1 ms to minimize.
[2023-03-08 05:26:38] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 147 ms
[2023-03-08 05:26:38] [INFO ] After 9334ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :52
Attempting to minimize the solution found.
Minimization took 2568 ms.
[2023-03-08 05:26:41] [INFO ] After 12840ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :52
Fused 55 Parikh solutions to 52 different solutions.
Parikh walk visited 2 properties in 6082 ms.
Support contains 70 out of 419 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 419/419 places, 371/371 transitions.
Graph (complete) has 941 edges and 419 vertex of which 413 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.2 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 11 transitions
Trivial Post-agglo rules discarded 11 transitions
Performed 11 trivial Post agglomeration. Transition count delta: 11
Iterating post reduction 0 with 12 rules applied. Total rules applied 13 place count 413 transition count 356
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 1 with 11 rules applied. Total rules applied 24 place count 402 transition count 356
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 24 place count 402 transition count 348
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 40 place count 394 transition count 348
Discarding 11 places :
Symmetric choice reduction at 2 with 11 rule applications. Total rules 51 place count 383 transition count 337
Iterating global reduction 2 with 11 rules applied. Total rules applied 62 place count 383 transition count 337
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 67 place count 383 transition count 332
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 67 place count 383 transition count 331
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 69 place count 382 transition count 331
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 73 place count 378 transition count 327
Iterating global reduction 3 with 4 rules applied. Total rules applied 77 place count 378 transition count 327
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 4 rules applied. Total rules applied 81 place count 378 transition count 323
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 82 place count 377 transition count 323
Performed 63 Post agglomeration using F-continuation condition.Transition count delta: 63
Deduced a syphon composed of 63 places in 1 ms
Reduce places removed 63 places and 0 transitions.
Iterating global reduction 5 with 126 rules applied. Total rules applied 208 place count 314 transition count 260
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 209 place count 314 transition count 259
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: -15
Deduced a syphon composed of 3 places in 1 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 6 with 6 rules applied. Total rules applied 215 place count 311 transition count 274
Free-agglomeration rule applied 3 times.
Iterating global reduction 6 with 3 rules applied. Total rules applied 218 place count 311 transition count 271
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 6 with 3 rules applied. Total rules applied 221 place count 308 transition count 271
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 7 with 2 rules applied. Total rules applied 223 place count 308 transition count 269
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 7 with 2 rules applied. Total rules applied 225 place count 306 transition count 269
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 8 with 1 rules applied. Total rules applied 226 place count 306 transition count 269
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 8 with 1 rules applied. Total rules applied 227 place count 305 transition count 268
Applied a total of 227 rules in 148 ms. Remains 305 /419 variables (removed 114) and now considering 268/371 (removed 103) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 148 ms. Remains : 305/419 places, 268/371 transitions.
Incomplete random walk after 10000 steps, including 252 resets, run finished after 295 ms. (steps per millisecond=33 ) properties (out of 50) seen :1
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 49) seen :0
Interrupted probabilistic random walk after 522063 steps, run timeout after 3001 ms. (steps per millisecond=173 ) properties seen :{}
Probabilistic random walk after 522063 steps, saw 70921 distinct states, run finished after 3002 ms. (steps per millisecond=173 ) properties seen :0
Running SMT prover for 49 properties.
// Phase 1: matrix 268 rows 305 cols
[2023-03-08 05:26:50] [INFO ] Computed 60 place invariants in 5 ms
[2023-03-08 05:26:51] [INFO ] [Real]Absence check using 34 positive place invariants in 6 ms returned sat
[2023-03-08 05:26:51] [INFO ] [Real]Absence check using 34 positive and 26 generalized place invariants in 14 ms returned sat
[2023-03-08 05:26:51] [INFO ] After 536ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:49
[2023-03-08 05:26:51] [INFO ] [Nat]Absence check using 34 positive place invariants in 5 ms returned sat
[2023-03-08 05:26:51] [INFO ] [Nat]Absence check using 34 positive and 26 generalized place invariants in 45 ms returned sat
[2023-03-08 05:26:55] [INFO ] After 3800ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :49
[2023-03-08 05:26:55] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-08 05:26:59] [INFO ] After 4181ms SMT Verify possible using 21 Read/Feed constraints in natural domain returned unsat :0 sat :49
[2023-03-08 05:27:00] [INFO ] Deduced a trap composed of 8 places in 41 ms of which 0 ms to minimize.
[2023-03-08 05:27:00] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 67 ms
[2023-03-08 05:27:00] [INFO ] Deduced a trap composed of 8 places in 54 ms of which 1 ms to minimize.
[2023-03-08 05:27:00] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 85 ms
[2023-03-08 05:27:00] [INFO ] Deduced a trap composed of 17 places in 51 ms of which 0 ms to minimize.
[2023-03-08 05:27:00] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 76 ms
[2023-03-08 05:27:01] [INFO ] Deduced a trap composed of 8 places in 49 ms of which 0 ms to minimize.
[2023-03-08 05:27:01] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 76 ms
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 5 places in 80 ms of which 1 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 3 places in 72 ms of which 1 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 3 places in 52 ms of which 1 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 276 ms
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 14 places in 48 ms of which 0 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 79 ms
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 18 places in 57 ms of which 1 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 101 ms
[2023-03-08 05:27:03] [INFO ] Deduced a trap composed of 16 places in 64 ms of which 1 ms to minimize.
[2023-03-08 05:27:03] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 84 ms
[2023-03-08 05:27:05] [INFO ] Deduced a trap composed of 18 places in 46 ms of which 1 ms to minimize.
[2023-03-08 05:27:05] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 76 ms
[2023-03-08 05:27:06] [INFO ] After 10671ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :49
Attempting to minimize the solution found.
Minimization took 4584 ms.
[2023-03-08 05:27:11] [INFO ] After 19643ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :49
Parikh walk visited 2 properties in 2701 ms.
Support contains 65 out of 305 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 305/305 places, 268/268 transitions.
Graph (complete) has 971 edges and 305 vertex of which 304 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.4 ms
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 2 rules applied. Total rules applied 3 place count 304 transition count 265
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 4 place count 303 transition count 265
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 4 place count 303 transition count 264
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 6 place count 302 transition count 264
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 10 place count 300 transition count 262
Free-agglomeration rule applied 1 times.
Iterating global reduction 2 with 1 rules applied. Total rules applied 11 place count 300 transition count 261
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 12 place count 299 transition count 261
Applied a total of 12 rules in 37 ms. Remains 299 /305 variables (removed 6) and now considering 261/268 (removed 7) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 38 ms. Remains : 299/305 places, 261/268 transitions.
Incomplete random walk after 10000 steps, including 246 resets, run finished after 274 ms. (steps per millisecond=36 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 7 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 6 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1001 steps, including 5 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 47) seen :0
Incomplete Best-First random walk after 1000 steps, including 4 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 47) seen :0
Interrupted probabilistic random walk after 585605 steps, run timeout after 3001 ms. (steps per millisecond=195 ) properties seen :{}
Probabilistic random walk after 585605 steps, saw 79748 distinct states, run finished after 3002 ms. (steps per millisecond=195 ) properties seen :0
Running SMT prover for 47 properties.
// Phase 1: matrix 261 rows 299 cols
[2023-03-08 05:27:17] [INFO ] Computed 61 place invariants in 11 ms
[2023-03-08 05:27:17] [INFO ] [Real]Absence check using 36 positive place invariants in 6 ms returned sat
[2023-03-08 05:27:17] [INFO ] [Real]Absence check using 36 positive and 25 generalized place invariants in 13 ms returned sat
[2023-03-08 05:27:17] [INFO ] After 286ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:47
[2023-03-08 05:27:17] [INFO ] [Nat]Absence check using 36 positive place invariants in 6 ms returned sat
[2023-03-08 05:27:18] [INFO ] [Nat]Absence check using 36 positive and 25 generalized place invariants in 85 ms returned sat
[2023-03-08 05:27:19] [INFO ] After 1138ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :47
[2023-03-08 05:27:19] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-08 05:27:20] [INFO ] After 1296ms SMT Verify possible using 21 Read/Feed constraints in natural domain returned unsat :0 sat :47
[2023-03-08 05:27:20] [INFO ] Deduced a trap composed of 11 places in 92 ms of which 0 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Deduced a trap composed of 16 places in 67 ms of which 0 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Deduced a trap composed of 11 places in 66 ms of which 0 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Deduced a trap composed of 8 places in 62 ms of which 16 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Deduced a trap composed of 10 places in 31 ms of which 1 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Trap strengthening (SAT) tested/added 6/5 trap constraints in 399 ms
[2023-03-08 05:27:21] [INFO ] Deduced a trap composed of 18 places in 63 ms of which 0 ms to minimize.
[2023-03-08 05:27:21] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 84 ms
[2023-03-08 05:27:22] [INFO ] Deduced a trap composed of 15 places in 58 ms of which 0 ms to minimize.
[2023-03-08 05:27:22] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 78 ms
[2023-03-08 05:27:22] [INFO ] Deduced a trap composed of 8 places in 37 ms of which 0 ms to minimize.
[2023-03-08 05:27:22] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 63 ms
[2023-03-08 05:27:23] [INFO ] After 3664ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :47
Attempting to minimize the solution found.
Minimization took 1513 ms.
[2023-03-08 05:27:24] [INFO ] After 6899ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :47
Parikh walk visited 1 properties in 2490 ms.
Support contains 64 out of 299 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 299/299 places, 261/261 transitions.
Applied a total of 0 rules in 8 ms. Remains 299 /299 variables (removed 0) and now considering 261/261 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 299/299 places, 261/261 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 299/299 places, 261/261 transitions.
Applied a total of 0 rules in 8 ms. Remains 299 /299 variables (removed 0) and now considering 261/261 (removed 0) transitions.
[2023-03-08 05:27:27] [INFO ] Invariant cache hit.
[2023-03-08 05:27:27] [INFO ] Implicit Places using invariants in 122 ms returned []
[2023-03-08 05:27:27] [INFO ] Invariant cache hit.
[2023-03-08 05:27:27] [INFO ] State equation strengthened by 21 read => feed constraints.
[2023-03-08 05:27:27] [INFO ] Implicit Places using invariants and state equation in 333 ms returned []
Implicit Place search using SMT with State Equation took 457 ms to find 0 implicit places.
[2023-03-08 05:27:27] [INFO ] Redundant transitions in 11 ms returned []
[2023-03-08 05:27:27] [INFO ] Invariant cache hit.
[2023-03-08 05:27:27] [INFO ] Dead Transitions using invariants and state equation in 138 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 626 ms. Remains : 299/299 places, 261/261 transitions.
Graph (complete) has 957 edges and 299 vertex of which 298 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.0 ms
Discarding 1 places :
Also discarding 0 output transitions
Applied a total of 1 rules in 9 ms. Remains 298 /299 variables (removed 1) and now considering 261/261 (removed 0) transitions.
Running SMT prover for 46 properties.
// Phase 1: matrix 261 rows 298 cols
[2023-03-08 05:27:27] [INFO ] Computed 60 place invariants in 12 ms
[2023-03-08 05:27:28] [INFO ] [Real]Absence check using 35 positive place invariants in 6 ms returned sat
[2023-03-08 05:27:28] [INFO ] [Real]Absence check using 35 positive and 25 generalized place invariants in 13 ms returned sat
[2023-03-08 05:27:28] [INFO ] After 273ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:46
[2023-03-08 05:27:28] [INFO ] [Nat]Absence check using 35 positive place invariants in 27 ms returned sat
[2023-03-08 05:27:28] [INFO ] [Nat]Absence check using 35 positive and 25 generalized place invariants in 107 ms returned sat
[2023-03-08 05:27:29] [INFO ] After 1135ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :46
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 12 places in 54 ms of which 1 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 74 ms
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 6 places in 68 ms of which 1 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 90 ms
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 21 places in 79 ms of which 1 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 98 ms
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 10 places in 37 ms of which 2 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 76 ms
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 5 places in 71 ms of which 0 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 15 places in 68 ms of which 2 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Deduced a trap composed of 18 places in 44 ms of which 0 ms to minimize.
[2023-03-08 05:27:30] [INFO ] Trap strengthening (SAT) tested/added 4/3 trap constraints in 237 ms
[2023-03-08 05:27:31] [INFO ] Deduced a trap composed of 17 places in 63 ms of which 0 ms to minimize.
[2023-03-08 05:27:31] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 86 ms
[2023-03-08 05:27:31] [INFO ] Deduced a trap composed of 20 places in 59 ms of which 1 ms to minimize.
[2023-03-08 05:27:31] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 84 ms
[2023-03-08 05:27:31] [INFO ] Deduced a trap composed of 16 places in 63 ms of which 0 ms to minimize.
[2023-03-08 05:27:32] [INFO ] Deduced a trap composed of 18 places in 61 ms of which 1 ms to minimize.
[2023-03-08 05:27:32] [INFO ] Deduced a trap composed of 13 places in 57 ms of which 0 ms to minimize.
[2023-03-08 05:27:32] [INFO ] Deduced a trap composed of 15 places in 53 ms of which 0 ms to minimize.
[2023-03-08 05:27:32] [INFO ] Trap strengthening (SAT) tested/added 5/4 trap constraints in 293 ms
[2023-03-08 05:27:32] [INFO ] After 3493ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :46
Attempting to minimize the solution found.
Minimization took 1213 ms.
[2023-03-08 05:27:33] [INFO ] After 5389ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :46
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 21 ms
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 21 ms
[2023-03-08 05:27:33] [INFO ] Input system was already deterministic with 371 transitions.
Computed a total of 223 stabilizing places and 215 stable transitions
Graph (complete) has 941 edges and 419 vertex of which 411 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.11 ms
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 403 transition count 355
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 403 transition count 355
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 38 place count 403 transition count 349
Discarding 6 places :
Symmetric choice reduction at 1 with 6 rule applications. Total rules 44 place count 397 transition count 343
Iterating global reduction 1 with 6 rules applied. Total rules applied 50 place count 397 transition count 343
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 54 place count 397 transition count 339
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 55 place count 396 transition count 338
Iterating global reduction 2 with 1 rules applied. Total rules applied 56 place count 396 transition count 338
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 57 place count 396 transition count 337
Applied a total of 57 rules in 22 ms. Remains 396 /419 variables (removed 23) and now considering 337/371 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 22 ms. Remains : 396/419 places, 337/371 transitions.
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 15 ms
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 17 ms
[2023-03-08 05:27:33] [INFO ] Input system was already deterministic with 337 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 403 transition count 355
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 403 transition count 355
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 37 place count 403 transition count 350
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 45 place count 395 transition count 342
Iterating global reduction 1 with 8 rules applied. Total rules applied 53 place count 395 transition count 342
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 58 place count 395 transition count 337
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 394 transition count 336
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 394 transition count 336
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 61 place count 394 transition count 335
Applied a total of 61 rules in 47 ms. Remains 394 /419 variables (removed 25) and now considering 335/371 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 394/419 places, 335/371 transitions.
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 17 ms
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 17 ms
[2023-03-08 05:27:33] [INFO ] Input system was already deterministic with 335 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 407 transition count 359
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 407 transition count 359
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 30 place count 407 transition count 353
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 35 place count 402 transition count 348
Iterating global reduction 1 with 5 rules applied. Total rules applied 40 place count 402 transition count 348
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 44 place count 402 transition count 344
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 45 place count 401 transition count 343
Iterating global reduction 2 with 1 rules applied. Total rules applied 46 place count 401 transition count 343
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 47 place count 401 transition count 342
Applied a total of 47 rules in 41 ms. Remains 401 /419 variables (removed 18) and now considering 342/371 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 401/419 places, 342/371 transitions.
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:27:33] [INFO ] Input system was already deterministic with 342 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 404 transition count 356
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 404 transition count 356
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 34 place count 404 transition count 352
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 42 place count 396 transition count 344
Iterating global reduction 1 with 8 rules applied. Total rules applied 50 place count 396 transition count 344
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 55 place count 396 transition count 339
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 56 place count 395 transition count 338
Iterating global reduction 2 with 1 rules applied. Total rules applied 57 place count 395 transition count 338
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 58 place count 395 transition count 337
Applied a total of 58 rules in 40 ms. Remains 395 /419 variables (removed 24) and now considering 337/371 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 40 ms. Remains : 395/419 places, 337/371 transitions.
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:27:33] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:27:33] [INFO ] Input system was already deterministic with 337 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Graph (complete) has 941 edges and 419 vertex of which 411 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.2 ms
Discarding 8 places :
Also discarding 5 output transitions
Drop transitions removed 5 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 17 place count 410 transition count 349
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 33 place count 394 transition count 349
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 9 Pre rules applied. Total rules applied 33 place count 394 transition count 340
Deduced a syphon composed of 9 places in 1 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 51 place count 385 transition count 340
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 65 place count 371 transition count 326
Iterating global reduction 2 with 14 rules applied. Total rules applied 79 place count 371 transition count 326
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 85 place count 371 transition count 320
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 85 place count 371 transition count 317
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 91 place count 368 transition count 317
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 97 place count 362 transition count 311
Iterating global reduction 3 with 6 rules applied. Total rules applied 103 place count 362 transition count 311
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 3 with 7 rules applied. Total rules applied 110 place count 362 transition count 304
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 113 place count 360 transition count 303
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 113 place count 360 transition count 302
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 115 place count 359 transition count 302
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 0 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 5 with 140 rules applied. Total rules applied 255 place count 289 transition count 232
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 257 place count 287 transition count 230
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 258 place count 286 transition count 230
Applied a total of 258 rules in 86 ms. Remains 286 /419 variables (removed 133) and now considering 230/371 (removed 141) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 86 ms. Remains : 286/419 places, 230/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 230 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 403 transition count 355
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 403 transition count 355
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 37 place count 403 transition count 350
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 45 place count 395 transition count 342
Iterating global reduction 1 with 8 rules applied. Total rules applied 53 place count 395 transition count 342
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 58 place count 395 transition count 337
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 394 transition count 336
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 394 transition count 336
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 61 place count 394 transition count 335
Applied a total of 61 rules in 35 ms. Remains 394 /419 variables (removed 25) and now considering 335/371 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 394/419 places, 335/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 335 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 402 transition count 354
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 402 transition count 354
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 40 place count 402 transition count 348
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 47 place count 395 transition count 341
Iterating global reduction 1 with 7 rules applied. Total rules applied 54 place count 395 transition count 341
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 58 place count 395 transition count 337
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 394 transition count 336
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 394 transition count 336
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 61 place count 394 transition count 335
Applied a total of 61 rules in 40 ms. Remains 394 /419 variables (removed 25) and now considering 335/371 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 41 ms. Remains : 394/419 places, 335/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 335 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 402 transition count 354
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 402 transition count 354
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 40 place count 402 transition count 348
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 48 place count 394 transition count 340
Iterating global reduction 1 with 8 rules applied. Total rules applied 56 place count 394 transition count 340
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 61 place count 394 transition count 335
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 62 place count 393 transition count 334
Iterating global reduction 2 with 1 rules applied. Total rules applied 63 place count 393 transition count 334
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 64 place count 393 transition count 333
Applied a total of 64 rules in 56 ms. Remains 393 /419 variables (removed 26) and now considering 333/371 (removed 38) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 393/419 places, 333/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 10 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 333 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Graph (complete) has 941 edges and 419 vertex of which 411 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 5 output transitions
Drop transitions removed 5 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 17 place count 410 transition count 349
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 33 place count 394 transition count 349
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 9 Pre rules applied. Total rules applied 33 place count 394 transition count 340
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 51 place count 385 transition count 340
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 64 place count 372 transition count 327
Iterating global reduction 2 with 13 rules applied. Total rules applied 77 place count 372 transition count 327
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 83 place count 372 transition count 321
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 83 place count 372 transition count 318
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 89 place count 369 transition count 318
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 94 place count 364 transition count 313
Iterating global reduction 3 with 5 rules applied. Total rules applied 99 place count 364 transition count 313
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 3 with 6 rules applied. Total rules applied 105 place count 364 transition count 307
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 108 place count 362 transition count 306
Performed 71 Post agglomeration using F-continuation condition.Transition count delta: 71
Deduced a syphon composed of 71 places in 0 ms
Reduce places removed 71 places and 0 transitions.
Iterating global reduction 5 with 142 rules applied. Total rules applied 250 place count 291 transition count 235
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 252 place count 289 transition count 233
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 253 place count 288 transition count 233
Applied a total of 253 rules in 49 ms. Remains 288 /419 variables (removed 131) and now considering 233/371 (removed 138) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 51 ms. Remains : 288/419 places, 233/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 233 transitions.
Finished random walk after 57 steps, including 1 resets, run visited all 1 properties in 1 ms. (steps per millisecond=57 )
FORMULA DES-PT-40b-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 405 transition count 357
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 405 transition count 357
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 33 place count 405 transition count 352
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 38 place count 400 transition count 347
Iterating global reduction 1 with 5 rules applied. Total rules applied 43 place count 400 transition count 347
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 47 place count 400 transition count 343
Applied a total of 47 rules in 17 ms. Remains 400 /419 variables (removed 19) and now considering 343/371 (removed 28) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 400/419 places, 343/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 10 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 343 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 402 transition count 354
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 402 transition count 354
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 40 place count 402 transition count 348
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 47 place count 395 transition count 341
Iterating global reduction 1 with 7 rules applied. Total rules applied 54 place count 395 transition count 341
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 58 place count 395 transition count 337
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 59 place count 394 transition count 336
Iterating global reduction 2 with 1 rules applied. Total rules applied 60 place count 394 transition count 336
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 61 place count 394 transition count 335
Applied a total of 61 rules in 16 ms. Remains 394 /419 variables (removed 25) and now considering 335/371 (removed 36) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 394/419 places, 335/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 335 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 404 transition count 356
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 404 transition count 356
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 35 place count 404 transition count 351
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 42 place count 397 transition count 344
Iterating global reduction 1 with 7 rules applied. Total rules applied 49 place count 397 transition count 344
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 53 place count 397 transition count 340
Applied a total of 53 rules in 13 ms. Remains 397 /419 variables (removed 22) and now considering 340/371 (removed 31) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 397/419 places, 340/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 10 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 340 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Graph (complete) has 941 edges and 419 vertex of which 411 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 5 output transitions
Drop transitions removed 5 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 15 transitions
Trivial Post-agglo rules discarded 15 transitions
Performed 15 trivial Post agglomeration. Transition count delta: 15
Iterating post reduction 0 with 15 rules applied. Total rules applied 16 place count 410 transition count 350
Reduce places removed 15 places and 0 transitions.
Iterating post reduction 1 with 15 rules applied. Total rules applied 31 place count 395 transition count 350
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 10 Pre rules applied. Total rules applied 31 place count 395 transition count 340
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 51 place count 385 transition count 340
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 65 place count 371 transition count 326
Iterating global reduction 2 with 14 rules applied. Total rules applied 79 place count 371 transition count 326
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 85 place count 371 transition count 320
Performed 3 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 3 Pre rules applied. Total rules applied 85 place count 371 transition count 317
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 91 place count 368 transition count 317
Discarding 6 places :
Symmetric choice reduction at 3 with 6 rule applications. Total rules 97 place count 362 transition count 311
Iterating global reduction 3 with 6 rules applied. Total rules applied 103 place count 362 transition count 311
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 3 with 7 rules applied. Total rules applied 110 place count 362 transition count 304
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 3 rules applied. Total rules applied 113 place count 360 transition count 303
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 113 place count 360 transition count 302
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 115 place count 359 transition count 302
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 0 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 5 with 140 rules applied. Total rules applied 255 place count 289 transition count 232
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 257 place count 287 transition count 230
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 258 place count 286 transition count 230
Applied a total of 258 rules in 49 ms. Remains 286 /419 variables (removed 133) and now considering 230/371 (removed 141) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 49 ms. Remains : 286/419 places, 230/371 transitions.
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 8 ms
[2023-03-08 05:27:34] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:27:34] [INFO ] Input system was already deterministic with 230 transitions.
Incomplete random walk after 10000 steps, including 315 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 65 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1804956 steps, run timeout after 3001 ms. (steps per millisecond=601 ) properties seen :{}
Probabilistic random walk after 1804956 steps, saw 257898 distinct states, run finished after 3002 ms. (steps per millisecond=601 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 230 rows 286 cols
[2023-03-08 05:27:37] [INFO ] Computed 58 place invariants in 16 ms
[2023-03-08 05:27:37] [INFO ] [Real]Absence check using 33 positive place invariants in 4 ms returned sat
[2023-03-08 05:27:37] [INFO ] [Real]Absence check using 33 positive and 25 generalized place invariants in 11 ms returned sat
[2023-03-08 05:27:37] [INFO ] After 82ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:27:37] [INFO ] [Nat]Absence check using 33 positive place invariants in 5 ms returned sat
[2023-03-08 05:27:37] [INFO ] [Nat]Absence check using 33 positive and 25 generalized place invariants in 65 ms returned sat
[2023-03-08 05:27:38] [INFO ] After 138ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:27:38] [INFO ] After 161ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-08 05:27:38] [INFO ] After 315ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 300 ms.
Support contains 2 out of 286 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 286/286 places, 230/230 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 286 transition count 226
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 6 place count 284 transition count 226
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 14 place count 280 transition count 222
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: -2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 18 place count 278 transition count 224
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 2 with 1 rules applied. Total rules applied 19 place count 278 transition count 223
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 20 place count 277 transition count 223
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 21 place count 277 transition count 223
Applied a total of 21 rules in 21 ms. Remains 277 /286 variables (removed 9) and now considering 223/230 (removed 7) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 21 ms. Remains : 277/286 places, 223/230 transitions.
Incomplete random walk after 1000000 steps, including 45270 resets, run finished after 2119 ms. (steps per millisecond=471 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 8847 resets, run finished after 925 ms. (steps per millisecond=1081 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 5260192 steps, run timeout after 9001 ms. (steps per millisecond=584 ) properties seen :{}
Probabilistic random walk after 5260192 steps, saw 765608 distinct states, run finished after 9001 ms. (steps per millisecond=584 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 223 rows 277 cols
[2023-03-08 05:27:50] [INFO ] Computed 60 place invariants in 11 ms
[2023-03-08 05:27:50] [INFO ] [Real]Absence check using 36 positive place invariants in 4 ms returned sat
[2023-03-08 05:27:50] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 12 ms returned sat
[2023-03-08 05:27:50] [INFO ] After 75ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:27:50] [INFO ] [Nat]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:27:50] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 33 ms returned sat
[2023-03-08 05:27:51] [INFO ] After 300ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:27:51] [INFO ] After 320ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 16 ms.
[2023-03-08 05:27:51] [INFO ] After 456ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 69 ms.
Support contains 2 out of 277 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 277/277 places, 223/223 transitions.
Applied a total of 0 rules in 4 ms. Remains 277 /277 variables (removed 0) and now considering 223/223 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 4 ms. Remains : 277/277 places, 223/223 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 277/277 places, 223/223 transitions.
Applied a total of 0 rules in 9 ms. Remains 277 /277 variables (removed 0) and now considering 223/223 (removed 0) transitions.
[2023-03-08 05:27:51] [INFO ] Invariant cache hit.
[2023-03-08 05:27:51] [INFO ] Implicit Places using invariants in 136 ms returned []
[2023-03-08 05:27:51] [INFO ] Invariant cache hit.
[2023-03-08 05:27:51] [INFO ] Implicit Places using invariants and state equation in 271 ms returned []
Implicit Place search using SMT with State Equation took 411 ms to find 0 implicit places.
[2023-03-08 05:27:51] [INFO ] Redundant transitions in 3 ms returned []
[2023-03-08 05:27:51] [INFO ] Invariant cache hit.
[2023-03-08 05:27:51] [INFO ] Dead Transitions using invariants and state equation in 117 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 547 ms. Remains : 277/277 places, 223/223 transitions.
Incomplete random walk after 100000 steps, including 4570 resets, run finished after 288 ms. (steps per millisecond=347 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-08 05:27:52] [INFO ] Invariant cache hit.
[2023-03-08 05:27:52] [INFO ] [Real]Absence check using 36 positive place invariants in 7 ms returned sat
[2023-03-08 05:27:52] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:27:52] [INFO ] After 68ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-08 05:27:52] [INFO ] Deduced a trap composed of 6 places in 34 ms of which 1 ms to minimize.
[2023-03-08 05:27:52] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 63 ms
[2023-03-08 05:27:52] [INFO ] After 142ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:27:52] [INFO ] After 212ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:27:52] [INFO ] [Nat]Absence check using 36 positive place invariants in 4 ms returned sat
[2023-03-08 05:27:52] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 57 ms returned sat
[2023-03-08 05:27:52] [INFO ] After 247ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:27:52] [INFO ] After 272ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-08 05:27:52] [INFO ] After 423ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 1000000 steps, including 45812 resets, run finished after 2096 ms. (steps per millisecond=477 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 1000001 steps, including 8794 resets, run finished after 919 ms. (steps per millisecond=1088 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 5367385 steps, run timeout after 9001 ms. (steps per millisecond=596 ) properties seen :{}
Probabilistic random walk after 5367385 steps, saw 781556 distinct states, run finished after 9002 ms. (steps per millisecond=596 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-08 05:28:04] [INFO ] Invariant cache hit.
[2023-03-08 05:28:04] [INFO ] [Real]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:04] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:28:04] [INFO ] After 72ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:04] [INFO ] [Nat]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:04] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 108 ms returned sat
[2023-03-08 05:28:05] [INFO ] After 105ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:05] [INFO ] After 168ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 13 ms.
[2023-03-08 05:28:05] [INFO ] After 357ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 72 ms.
Support contains 2 out of 277 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 277/277 places, 223/223 transitions.
Applied a total of 0 rules in 5 ms. Remains 277 /277 variables (removed 0) and now considering 223/223 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 5 ms. Remains : 277/277 places, 223/223 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 277/277 places, 223/223 transitions.
Applied a total of 0 rules in 4 ms. Remains 277 /277 variables (removed 0) and now considering 223/223 (removed 0) transitions.
[2023-03-08 05:28:05] [INFO ] Invariant cache hit.
[2023-03-08 05:28:05] [INFO ] Implicit Places using invariants in 166 ms returned []
[2023-03-08 05:28:05] [INFO ] Invariant cache hit.
[2023-03-08 05:28:05] [INFO ] Implicit Places using invariants and state equation in 298 ms returned []
Implicit Place search using SMT with State Equation took 495 ms to find 0 implicit places.
[2023-03-08 05:28:05] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-08 05:28:05] [INFO ] Invariant cache hit.
[2023-03-08 05:28:05] [INFO ] Dead Transitions using invariants and state equation in 116 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 625 ms. Remains : 277/277 places, 223/223 transitions.
Incomplete random walk after 100000 steps, including 4531 resets, run finished after 210 ms. (steps per millisecond=476 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-08 05:28:06] [INFO ] Invariant cache hit.
[2023-03-08 05:28:06] [INFO ] [Real]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:06] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:28:06] [INFO ] After 68ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-08 05:28:06] [INFO ] Deduced a trap composed of 6 places in 33 ms of which 0 ms to minimize.
[2023-03-08 05:28:06] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 53 ms
[2023-03-08 05:28:06] [INFO ] After 131ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:06] [INFO ] After 195ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:06] [INFO ] [Nat]Absence check using 36 positive place invariants in 4 ms returned sat
[2023-03-08 05:28:06] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 58 ms returned sat
[2023-03-08 05:28:06] [INFO ] After 242ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:06] [INFO ] After 263ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 5 ms.
[2023-03-08 05:28:06] [INFO ] After 422ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Incomplete random walk after 10000 steps, including 455 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 88 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1782018 steps, run timeout after 3001 ms. (steps per millisecond=593 ) properties seen :{}
Probabilistic random walk after 1782018 steps, saw 251104 distinct states, run finished after 3001 ms. (steps per millisecond=593 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-08 05:28:09] [INFO ] Invariant cache hit.
[2023-03-08 05:28:09] [INFO ] [Real]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:09] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:28:09] [INFO ] After 64ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:09] [INFO ] [Nat]Absence check using 36 positive place invariants in 4 ms returned sat
[2023-03-08 05:28:09] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 59 ms returned sat
[2023-03-08 05:28:10] [INFO ] After 255ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:10] [INFO ] After 274ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-03-08 05:28:10] [INFO ] After 457ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 277 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 277/277 places, 223/223 transitions.
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 276 transition count 222
Applied a total of 1 rules in 8 ms. Remains 276 /277 variables (removed 1) and now considering 222/223 (removed 1) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 8 ms. Remains : 276/277 places, 222/223 transitions.
Incomplete random walk after 10000 steps, including 472 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 89 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1809000 steps, run timeout after 3001 ms. (steps per millisecond=602 ) properties seen :{}
Probabilistic random walk after 1809000 steps, saw 255357 distinct states, run finished after 3001 ms. (steps per millisecond=602 ) properties seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 222 rows 276 cols
[2023-03-08 05:28:13] [INFO ] Computed 60 place invariants in 4 ms
[2023-03-08 05:28:13] [INFO ] [Real]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:13] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:28:13] [INFO ] After 72ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:13] [INFO ] [Nat]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:13] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 44 ms returned sat
[2023-03-08 05:28:13] [INFO ] After 242ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:13] [INFO ] After 259ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 13 ms.
[2023-03-08 05:28:13] [INFO ] After 414ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 1 out of 276 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 276/276 places, 222/222 transitions.
Applied a total of 0 rules in 6 ms. Remains 276 /276 variables (removed 0) and now considering 222/222 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 6 ms. Remains : 276/276 places, 222/222 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 276/276 places, 222/222 transitions.
Applied a total of 0 rules in 5 ms. Remains 276 /276 variables (removed 0) and now considering 222/222 (removed 0) transitions.
[2023-03-08 05:28:13] [INFO ] Invariant cache hit.
[2023-03-08 05:28:13] [INFO ] Implicit Places using invariants in 140 ms returned []
[2023-03-08 05:28:13] [INFO ] Invariant cache hit.
[2023-03-08 05:28:14] [INFO ] Implicit Places using invariants and state equation in 270 ms returned []
Implicit Place search using SMT with State Equation took 433 ms to find 0 implicit places.
[2023-03-08 05:28:14] [INFO ] Redundant transitions in 1 ms returned []
[2023-03-08 05:28:14] [INFO ] Invariant cache hit.
[2023-03-08 05:28:14] [INFO ] Dead Transitions using invariants and state equation in 118 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 575 ms. Remains : 276/276 places, 222/222 transitions.
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 276 transition count 222
Applied a total of 1 rules in 9 ms. Remains 276 /276 variables (removed 0) and now considering 222/222 (removed 0) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 222 rows 276 cols
[2023-03-08 05:28:14] [INFO ] Computed 60 place invariants in 2 ms
[2023-03-08 05:28:14] [INFO ] [Real]Absence check using 36 positive place invariants in 4 ms returned sat
[2023-03-08 05:28:14] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 11 ms returned sat
[2023-03-08 05:28:14] [INFO ] After 69ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:14] [INFO ] [Nat]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:14] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 42 ms returned sat
[2023-03-08 05:28:14] [INFO ] After 226ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:14] [INFO ] After 241ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-08 05:28:14] [INFO ] After 403ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished random walk after 2 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=2 )
Partial Free-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 277 transition count 223
Applied a total of 1 rules in 9 ms. Remains 277 /277 variables (removed 0) and now considering 223/223 (removed 0) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 223 rows 277 cols
[2023-03-08 05:28:14] [INFO ] Computed 60 place invariants in 2 ms
[2023-03-08 05:28:14] [INFO ] [Real]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:14] [INFO ] [Real]Absence check using 36 positive and 24 generalized place invariants in 13 ms returned sat
[2023-03-08 05:28:14] [INFO ] After 81ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 05:28:14] [INFO ] [Nat]Absence check using 36 positive place invariants in 5 ms returned sat
[2023-03-08 05:28:14] [INFO ] [Nat]Absence check using 36 positive and 24 generalized place invariants in 36 ms returned sat
[2023-03-08 05:28:15] [INFO ] After 261ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 05:28:15] [INFO ] Deduced a trap composed of 46 places in 39 ms of which 0 ms to minimize.
[2023-03-08 05:28:15] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 57 ms
[2023-03-08 05:28:15] [INFO ] After 331ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 26 ms.
[2023-03-08 05:28:15] [INFO ] After 484ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Starting structural reductions in SI_CTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Graph (complete) has 941 edges and 419 vertex of which 411 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 5 output transitions
Drop transitions removed 5 transitions
Reduce places removed 1 places and 1 transitions.
Drop transitions removed 16 transitions
Trivial Post-agglo rules discarded 16 transitions
Performed 16 trivial Post agglomeration. Transition count delta: 16
Iterating post reduction 0 with 16 rules applied. Total rules applied 17 place count 410 transition count 349
Reduce places removed 16 places and 0 transitions.
Iterating post reduction 1 with 16 rules applied. Total rules applied 33 place count 394 transition count 349
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 33 place count 394 transition count 341
Deduced a syphon composed of 8 places in 1 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 49 place count 386 transition count 341
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 61 place count 374 transition count 329
Iterating global reduction 2 with 12 rules applied. Total rules applied 73 place count 374 transition count 329
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 79 place count 374 transition count 323
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 79 place count 374 transition count 322
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 81 place count 373 transition count 322
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 86 place count 368 transition count 317
Iterating global reduction 3 with 5 rules applied. Total rules applied 91 place count 368 transition count 317
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 5 rules applied. Total rules applied 96 place count 368 transition count 312
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 97 place count 367 transition count 312
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 97 place count 367 transition count 311
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 99 place count 366 transition count 311
Performed 70 Post agglomeration using F-continuation condition.Transition count delta: 70
Deduced a syphon composed of 70 places in 0 ms
Reduce places removed 70 places and 0 transitions.
Iterating global reduction 5 with 140 rules applied. Total rules applied 239 place count 296 transition count 241
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 5 with 1 rules applied. Total rules applied 240 place count 296 transition count 240
Reduce places removed 2 places and 2 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 242 place count 294 transition count 238
Applied a total of 242 rules in 49 ms. Remains 294 /419 variables (removed 125) and now considering 238/371 (removed 133) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 49 ms. Remains : 294/419 places, 238/371 transitions.
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 10 ms
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 8 ms
[2023-03-08 05:28:15] [INFO ] Input system was already deterministic with 238 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 403 transition count 355
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 403 transition count 355
Ensure Unique test removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 0 with 6 rules applied. Total rules applied 38 place count 403 transition count 349
Discarding 7 places :
Symmetric choice reduction at 1 with 7 rule applications. Total rules 45 place count 396 transition count 342
Iterating global reduction 1 with 7 rules applied. Total rules applied 52 place count 396 transition count 342
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 1 with 4 rules applied. Total rules applied 56 place count 396 transition count 338
Applied a total of 56 rules in 12 ms. Remains 396 /419 variables (removed 23) and now considering 338/371 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 396/419 places, 338/371 transitions.
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 10 ms
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:28:15] [INFO ] Input system was already deterministic with 338 transitions.
Starting structural reductions in LTL mode, iteration 0 : 419/419 places, 371/371 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 406 transition count 358
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 406 transition count 358
Ensure Unique test removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 29 place count 406 transition count 355
Discarding 8 places :
Symmetric choice reduction at 1 with 8 rule applications. Total rules 37 place count 398 transition count 347
Iterating global reduction 1 with 8 rules applied. Total rules applied 45 place count 398 transition count 347
Ensure Unique test removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 1 with 5 rules applied. Total rules applied 50 place count 398 transition count 342
Applied a total of 50 rules in 12 ms. Remains 398 /419 variables (removed 21) and now considering 342/371 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 398/419 places, 342/371 transitions.
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 9 ms
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 11 ms
[2023-03-08 05:28:15] [INFO ] Input system was already deterministic with 342 transitions.
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 12 ms
[2023-03-08 05:28:15] [INFO ] Flatten gal took : 26 ms
[2023-03-08 05:28:15] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 13 ms.
[2023-03-08 05:28:15] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 419 places, 371 transitions and 1256 arcs took 2 ms.
Total runtime 110669 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DES-PT-40b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA DES-PT-40b-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678254033408
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 23 (type EXCL) for 22 DES-PT-40b-CTLFireability-02
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 70 (type FNDP) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 70 (type FNDP) for DES-PT-40b-CTLFireability-04
lola: result : true
lola: fired transitions : 49
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 71 (type EQUN) for DES-PT-40b-CTLFireability-04 (obsolete)
lola: CANCELED task # 73 (type SRCH) for DES-PT-40b-CTLFireability-04 (obsolete)
lola: FINISHED task # 71 (type EQUN) for DES-PT-40b-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 73 (type SRCH) for DES-PT-40b-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type FNDP) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:756
lola: rewrite Frontend/Parser/formula_rewrite.k:691
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 76 (type FNDP) for DES-PT-40b-CTLFireability-01
lola: result : true
lola: fired transitions : 12
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: CANCELED task # 77 (type EQUN) for DES-PT-40b-CTLFireability-01 (obsolete)
lola: CANCELED task # 79 (type SRCH) for DES-PT-40b-CTLFireability-01 (obsolete)
lola: FINISHED task # 79 (type SRCH) for DES-PT-40b-CTLFireability-01
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/375/CTLFireability-77.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 75 (type FNDP) for 57 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 57 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SRCH) for 57 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 84 (type SRCH) for DES-PT-40b-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/375/CTLFireability-82.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 77 (type EQUN) for DES-PT-40b-CTLFireability-01
lola: result : true
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/189 4/32 DES-PT-40b-CTLFireability-02 562059 m, 112411 m/sec, 1982360 t fired, .
75 EF FNDP 4/3598 0/5 DES-PT-40b-CTLFireability-12 6421688 t fired, 257359 attempts, .
82 EF STEQ 4/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 6 secs. Pages in use: 4
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/189 7/32 DES-PT-40b-CTLFireability-02 1092591 m, 106106 m/sec, 4062736 t fired, .
75 EF FNDP 9/3598 0/5 DES-PT-40b-CTLFireability-12 13568807 t fired, 547796 attempts, .
82 EF STEQ 9/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 11 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/189 9/32 DES-PT-40b-CTLFireability-02 1584627 m, 98407 m/sec, 6120248 t fired, .
75 EF FNDP 14/3598 0/5 DES-PT-40b-CTLFireability-12 20773554 t fired, 840597 attempts, .
82 EF STEQ 14/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 16 secs. Pages in use: 9
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/189 13/32 DES-PT-40b-CTLFireability-02 2129732 m, 109021 m/sec, 8213112 t fired, .
75 EF FNDP 19/3598 0/5 DES-PT-40b-CTLFireability-12 27952642 t fired, 1132014 attempts, .
82 EF STEQ 19/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 21 secs. Pages in use: 13
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/189 16/32 DES-PT-40b-CTLFireability-02 2664891 m, 107031 m/sec, 10309146 t fired, .
75 EF FNDP 24/3598 0/5 DES-PT-40b-CTLFireability-12 35153165 t fired, 1424284 attempts, .
82 EF STEQ 24/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 26 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/189 18/32 DES-PT-40b-CTLFireability-02 3152150 m, 97451 m/sec, 12356007 t fired, .
75 EF FNDP 29/3598 0/5 DES-PT-40b-CTLFireability-12 42291901 t fired, 1715058 attempts, .
82 EF STEQ 29/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 31 secs. Pages in use: 18
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/189 21/32 DES-PT-40b-CTLFireability-02 3701387 m, 109847 m/sec, 14452701 t fired, .
75 EF FNDP 34/3598 0/5 DES-PT-40b-CTLFireability-12 49526101 t fired, 2008519 attempts, .
82 EF STEQ 34/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 36 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/189 24/32 DES-PT-40b-CTLFireability-02 4233772 m, 106477 m/sec, 16547247 t fired, .
75 EF FNDP 39/3598 0/5 DES-PT-40b-CTLFireability-12 56776653 t fired, 2303202 attempts, .
82 EF STEQ 39/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 41 secs. Pages in use: 24
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/189 27/32 DES-PT-40b-CTLFireability-02 4722786 m, 97802 m/sec, 18612505 t fired, .
75 EF FNDP 44/3598 0/5 DES-PT-40b-CTLFireability-12 64027907 t fired, 2598323 attempts, .
82 EF STEQ 44/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 46 secs. Pages in use: 27
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/189 30/32 DES-PT-40b-CTLFireability-02 5168711 m, 89185 m/sec, 20686297 t fired, .
75 EF FNDP 49/3598 0/5 DES-PT-40b-CTLFireability-12 71272222 t fired, 2892883 attempts, .
82 EF STEQ 49/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 51 secs. Pages in use: 30
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/189 32/32 DES-PT-40b-CTLFireability-02 5590193 m, 84296 m/sec, 22741555 t fired, .
75 EF FNDP 54/3598 0/5 DES-PT-40b-CTLFireability-12 78519414 t fired, 3188091 attempts, .
82 EF STEQ 54/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 23 (type EXCL) for DES-PT-40b-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 4 0 0 8 0 0 1
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 59/3598 0/5 DES-PT-40b-CTLFireability-12 86002863 t fired, 3493449 attempts, .
82 EF STEQ 59/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 85 (type EXCL) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 196 sec
lola: memory limit: 32 pages
lola: FINISHED task # 85 (type EXCL) for DES-PT-40b-CTLFireability-01
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 80 (type EXCL) for 50 DES-PT-40b-CTLFireability-11
lola: time limit : 235 sec
lola: memory limit: 32 pages
lola: FINISHED task # 80 (type EXCL) for DES-PT-40b-CTLFireability-11
lola: result : true
lola: markings : 93
lola: fired transitions : 92
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 66 DES-PT-40b-CTLFireability-15
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for DES-PT-40b-CTLFireability-15
lola: result : true
lola: markings : 420883
lola: fired transitions : 1722640
lola: time used : 4.000000
lola: memory pages used : 3
lola: LAUNCH task # 64 (type EXCL) for 63 DES-PT-40b-CTLFireability-14
lola: time limit : 271 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 1/271 1/32 DES-PT-40b-CTLFireability-14 35987 m, 7197 m/sec, 315156 t fired, .
75 EF FNDP 64/3598 0/5 DES-PT-40b-CTLFireability-12 93253757 t fired, 3788097 attempts, .
82 EF STEQ 64/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 6/271 1/32 DES-PT-40b-CTLFireability-14 200605 m, 32923 m/sec, 2083444 t fired, .
75 EF FNDP 69/3598 0/5 DES-PT-40b-CTLFireability-12 100501584 t fired, 4083287 attempts, .
82 EF STEQ 69/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 11/271 2/32 DES-PT-40b-CTLFireability-14 360447 m, 31968 m/sec, 3847201 t fired, .
75 EF FNDP 74/3598 0/5 DES-PT-40b-CTLFireability-12 107749667 t fired, 4378173 attempts, .
82 EF STEQ 74/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 16/271 3/32 DES-PT-40b-CTLFireability-14 518504 m, 31611 m/sec, 5608130 t fired, .
75 EF FNDP 79/3598 0/5 DES-PT-40b-CTLFireability-12 114987977 t fired, 4672534 attempts, .
82 EF STEQ 79/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 21/271 4/32 DES-PT-40b-CTLFireability-14 669873 m, 30273 m/sec, 7357163 t fired, .
75 EF FNDP 84/3598 0/5 DES-PT-40b-CTLFireability-12 122242657 t fired, 4967931 attempts, .
82 EF STEQ 84/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 26/271 5/32 DES-PT-40b-CTLFireability-14 817050 m, 29435 m/sec, 9116729 t fired, .
75 EF FNDP 89/3598 0/5 DES-PT-40b-CTLFireability-12 129494882 t fired, 5263057 attempts, .
82 EF STEQ 89/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 31/271 5/32 DES-PT-40b-CTLFireability-14 950332 m, 26656 m/sec, 10863372 t fired, .
75 EF FNDP 94/3598 0/5 DES-PT-40b-CTLFireability-12 136791189 t fired, 5560033 attempts, .
82 EF STEQ 94/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 36/271 6/32 DES-PT-40b-CTLFireability-14 1082592 m, 26452 m/sec, 12594031 t fired, .
75 EF FNDP 99/3598 0/5 DES-PT-40b-CTLFireability-12 144010684 t fired, 5854128 attempts, .
82 EF STEQ 99/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 41/271 6/32 DES-PT-40b-CTLFireability-14 1213897 m, 26261 m/sec, 14313928 t fired, .
75 EF FNDP 104/3598 0/5 DES-PT-40b-CTLFireability-12 151155643 t fired, 6145211 attempts, .
82 EF STEQ 104/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 46/271 7/32 DES-PT-40b-CTLFireability-14 1340887 m, 25398 m/sec, 16020674 t fired, .
75 EF FNDP 109/3598 0/5 DES-PT-40b-CTLFireability-12 158282143 t fired, 6436012 attempts, .
82 EF STEQ 109/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 51/271 8/32 DES-PT-40b-CTLFireability-14 1480566 m, 27935 m/sec, 17745938 t fired, .
75 EF FNDP 114/3598 0/5 DES-PT-40b-CTLFireability-12 165439969 t fired, 6727801 attempts, .
82 EF STEQ 114/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 56/271 8/32 DES-PT-40b-CTLFireability-14 1611536 m, 26194 m/sec, 19459546 t fired, .
75 EF FNDP 119/3598 0/5 DES-PT-40b-CTLFireability-12 172630128 t fired, 7020913 attempts, .
82 EF STEQ 119/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 61/271 9/32 DES-PT-40b-CTLFireability-14 1742292 m, 26151 m/sec, 21172573 t fired, .
75 EF FNDP 124/3598 0/5 DES-PT-40b-CTLFireability-12 179822688 t fired, 7313855 attempts, .
82 EF STEQ 124/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 66/271 10/32 DES-PT-40b-CTLFireability-14 1873493 m, 26240 m/sec, 22889005 t fired, .
75 EF FNDP 129/3598 0/5 DES-PT-40b-CTLFireability-12 187008161 t fired, 7605919 attempts, .
82 EF STEQ 129/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 71/271 10/32 DES-PT-40b-CTLFireability-14 2001632 m, 25627 m/sec, 24587889 t fired, .
75 EF FNDP 134/3598 0/5 DES-PT-40b-CTLFireability-12 194133940 t fired, 7895801 attempts, .
82 EF STEQ 134/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 76/271 11/32 DES-PT-40b-CTLFireability-14 2144484 m, 28570 m/sec, 26296277 t fired, .
75 EF FNDP 139/3598 0/5 DES-PT-40b-CTLFireability-12 201300451 t fired, 8186780 attempts, .
82 EF STEQ 139/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 81/271 12/32 DES-PT-40b-CTLFireability-14 2290596 m, 29222 m/sec, 27993724 t fired, .
75 EF FNDP 144/3598 0/5 DES-PT-40b-CTLFireability-12 208457826 t fired, 8478171 attempts, .
82 EF STEQ 144/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 86/271 13/32 DES-PT-40b-CTLFireability-14 2446515 m, 31183 m/sec, 29685302 t fired, .
75 EF FNDP 149/3598 0/5 DES-PT-40b-CTLFireability-12 215567115 t fired, 8767176 attempts, .
82 EF STEQ 149/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 91/271 13/32 DES-PT-40b-CTLFireability-14 2590064 m, 28709 m/sec, 31370588 t fired, .
75 EF FNDP 154/3598 0/5 DES-PT-40b-CTLFireability-12 222694941 t fired, 9056808 attempts, .
82 EF STEQ 154/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 96/271 14/32 DES-PT-40b-CTLFireability-14 2703236 m, 22634 m/sec, 33026005 t fired, .
75 EF FNDP 159/3598 0/5 DES-PT-40b-CTLFireability-12 229814818 t fired, 9347309 attempts, .
82 EF STEQ 159/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 101/271 14/32 DES-PT-40b-CTLFireability-14 2798625 m, 19077 m/sec, 34681953 t fired, .
75 EF FNDP 164/3598 0/5 DES-PT-40b-CTLFireability-12 236991702 t fired, 9639716 attempts, .
82 EF STEQ 164/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 106/271 15/32 DES-PT-40b-CTLFireability-14 2891901 m, 18655 m/sec, 36325289 t fired, .
75 EF FNDP 169/3598 0/5 DES-PT-40b-CTLFireability-12 244153708 t fired, 9931671 attempts, .
82 EF STEQ 169/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 111/271 16/32 DES-PT-40b-CTLFireability-14 3053865 m, 32392 m/sec, 38030683 t fired, .
75 EF FNDP 174/3598 0/5 DES-PT-40b-CTLFireability-12 251284931 t fired, 10221715 attempts, .
82 EF STEQ 174/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 116/271 16/32 DES-PT-40b-CTLFireability-14 3203810 m, 29989 m/sec, 39726954 t fired, .
75 EF FNDP 179/3598 0/5 DES-PT-40b-CTLFireability-12 258425930 t fired, 10512934 attempts, .
82 EF STEQ 179/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 121/271 17/32 DES-PT-40b-CTLFireability-14 3338141 m, 26866 m/sec, 41413215 t fired, .
75 EF FNDP 184/3598 0/5 DES-PT-40b-CTLFireability-12 265572038 t fired, 10803426 attempts, .
82 EF STEQ 184/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 126/271 18/32 DES-PT-40b-CTLFireability-14 3476654 m, 27702 m/sec, 43107173 t fired, .
75 EF FNDP 189/3598 0/5 DES-PT-40b-CTLFireability-12 272760505 t fired, 11096503 attempts, .
82 EF STEQ 189/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 131/271 18/32 DES-PT-40b-CTLFireability-14 3618781 m, 28425 m/sec, 44796722 t fired, .
75 EF FNDP 194/3598 0/5 DES-PT-40b-CTLFireability-12 279963940 t fired, 11389876 attempts, .
82 EF STEQ 194/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 136/271 19/32 DES-PT-40b-CTLFireability-14 3763804 m, 29004 m/sec, 46470535 t fired, .
75 EF FNDP 199/3598 0/5 DES-PT-40b-CTLFireability-12 287167712 t fired, 11683450 attempts, .
82 EF STEQ 199/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 141/271 20/32 DES-PT-40b-CTLFireability-14 3917849 m, 30809 m/sec, 48143311 t fired, .
75 EF FNDP 204/3598 0/5 DES-PT-40b-CTLFireability-12 294368600 t fired, 11977011 attempts, .
82 EF STEQ 204/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 146/271 20/32 DES-PT-40b-CTLFireability-14 4026996 m, 21829 m/sec, 49781799 t fired, .
75 EF FNDP 209/3598 0/5 DES-PT-40b-CTLFireability-12 301544807 t fired, 12269075 attempts, .
82 EF STEQ 209/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 151/271 21/32 DES-PT-40b-CTLFireability-14 4118700 m, 18340 m/sec, 51404267 t fired, .
75 EF FNDP 214/3598 0/5 DES-PT-40b-CTLFireability-12 308693044 t fired, 12560745 attempts, .
82 EF STEQ 214/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 156/271 22/32 DES-PT-40b-CTLFireability-14 4239602 m, 24180 m/sec, 53090232 t fired, .
75 EF FNDP 219/3598 0/5 DES-PT-40b-CTLFireability-12 315868492 t fired, 12853260 attempts, .
82 EF STEQ 219/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 161/271 22/32 DES-PT-40b-CTLFireability-14 4356739 m, 23427 m/sec, 54770529 t fired, .
75 EF FNDP 224/3598 0/5 DES-PT-40b-CTLFireability-12 323033963 t fired, 13145327 attempts, .
82 EF STEQ 224/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 166/271 23/32 DES-PT-40b-CTLFireability-14 4462008 m, 21053 m/sec, 56436176 t fired, .
75 EF FNDP 229/3598 0/5 DES-PT-40b-CTLFireability-12 330194714 t fired, 13437583 attempts, .
82 EF STEQ 229/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 171/271 23/32 DES-PT-40b-CTLFireability-14 4564613 m, 20521 m/sec, 58100625 t fired, .
75 EF FNDP 234/3598 0/5 DES-PT-40b-CTLFireability-12 337366724 t fired, 13730005 attempts, .
82 EF STEQ 234/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 176/271 24/32 DES-PT-40b-CTLFireability-14 4669252 m, 20927 m/sec, 59759777 t fired, .
75 EF FNDP 239/3598 0/5 DES-PT-40b-CTLFireability-12 344539483 t fired, 14022812 attempts, .
82 EF STEQ 239/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 181/271 24/32 DES-PT-40b-CTLFireability-14 4773242 m, 20798 m/sec, 61426093 t fired, .
75 EF FNDP 244/3598 0/5 DES-PT-40b-CTLFireability-12 351709341 t fired, 14315100 attempts, .
82 EF STEQ 244/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 186/271 25/32 DES-PT-40b-CTLFireability-14 4882858 m, 21923 m/sec, 63067052 t fired, .
75 EF FNDP 249/3598 0/5 DES-PT-40b-CTLFireability-12 358878538 t fired, 14607531 attempts, .
82 EF STEQ 249/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 191/271 25/32 DES-PT-40b-CTLFireability-14 4987065 m, 20841 m/sec, 64711384 t fired, .
75 EF FNDP 254/3598 0/5 DES-PT-40b-CTLFireability-12 366090129 t fired, 14901107 attempts, .
82 EF STEQ 254/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 256 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 196/271 26/32 DES-PT-40b-CTLFireability-14 5100623 m, 22711 m/sec, 66364687 t fired, .
75 EF FNDP 259/3598 0/5 DES-PT-40b-CTLFireability-12 373312058 t fired, 15195785 attempts, .
82 EF STEQ 259/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 261 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 201/271 26/32 DES-PT-40b-CTLFireability-14 5198737 m, 19622 m/sec, 67997031 t fired, .
75 EF FNDP 264/3598 0/5 DES-PT-40b-CTLFireability-12 380499864 t fired, 15488426 attempts, .
82 EF STEQ 264/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 266 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 206/271 27/32 DES-PT-40b-CTLFireability-14 5271954 m, 14643 m/sec, 69500862 t fired, .
75 EF FNDP 269/3598 0/5 DES-PT-40b-CTLFireability-12 387629900 t fired, 15778677 attempts, .
82 EF STEQ 269/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 271 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 211/271 27/32 DES-PT-40b-CTLFireability-14 5343938 m, 14396 m/sec, 71063283 t fired, .
75 EF FNDP 274/3598 0/5 DES-PT-40b-CTLFireability-12 394422573 t fired, 16055614 attempts, .
82 EF STEQ 274/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 276 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 216/271 28/32 DES-PT-40b-CTLFireability-14 5507266 m, 32665 m/sec, 72803211 t fired, .
75 EF FNDP 279/3598 0/5 DES-PT-40b-CTLFireability-12 401621976 t fired, 16350015 attempts, .
82 EF STEQ 279/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 281 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 221/271 29/32 DES-PT-40b-CTLFireability-14 5662858 m, 31118 m/sec, 74535284 t fired, .
75 EF FNDP 284/3598 0/5 DES-PT-40b-CTLFireability-12 408802451 t fired, 16642009 attempts, .
82 EF STEQ 284/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 286 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 226/271 29/32 DES-PT-40b-CTLFireability-14 5819125 m, 31253 m/sec, 76274581 t fired, .
75 EF FNDP 289/3598 0/5 DES-PT-40b-CTLFireability-12 415447628 t fired, 16913549 attempts, .
82 EF STEQ 289/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 291 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 231/271 30/32 DES-PT-40b-CTLFireability-14 5972687 m, 30712 m/sec, 77994495 t fired, .
75 EF FNDP 294/3598 0/5 DES-PT-40b-CTLFireability-12 422577859 t fired, 17203202 attempts, .
82 EF STEQ 294/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 296 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 236/271 31/32 DES-PT-40b-CTLFireability-14 6120882 m, 29639 m/sec, 79710534 t fired, .
75 EF FNDP 299/3598 0/5 DES-PT-40b-CTLFireability-12 429744032 t fired, 17495511 attempts, .
82 EF STEQ 299/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 301 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 241/271 31/32 DES-PT-40b-CTLFireability-14 6250150 m, 25853 m/sec, 81414085 t fired, .
75 EF FNDP 304/3598 0/5 DES-PT-40b-CTLFireability-12 436928367 t fired, 17788595 attempts, .
82 EF STEQ 304/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 306 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 CTL EXCL 246/271 32/32 DES-PT-40b-CTLFireability-14 6379258 m, 25821 m/sec, 83108507 t fired, .
75 EF FNDP 309/3598 0/5 DES-PT-40b-CTLFireability-12 444026267 t fired, 18078351 attempts, .
82 EF STEQ 309/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 311 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 64 (type EXCL) for DES-PT-40b-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 314/3598 0/5 DES-PT-40b-CTLFireability-12 451206315 t fired, 18370419 attempts, .
82 EF STEQ 314/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 55 (type EXCL) for 50 DES-PT-40b-CTLFireability-11
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for DES-PT-40b-CTLFireability-11
lola: result : false
lola: markings : 85
lola: fired transitions : 84
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 DES-PT-40b-CTLFireability-10
lola: time limit : 298 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/298 4/32 DES-PT-40b-CTLFireability-10 622940 m, 124588 m/sec, 2090436 t fired, .
75 EF FNDP 319/3598 0/5 DES-PT-40b-CTLFireability-12 458327467 t fired, 18660473 attempts, .
82 EF STEQ 319/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 321 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/298 8/32 DES-PT-40b-CTLFireability-10 1252719 m, 125955 m/sec, 4213657 t fired, .
75 EF FNDP 324/3598 0/5 DES-PT-40b-CTLFireability-12 465559784 t fired, 18954781 attempts, .
82 EF STEQ 324/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 326 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 15/298 12/32 DES-PT-40b-CTLFireability-10 1884023 m, 126260 m/sec, 6311995 t fired, .
75 EF FNDP 329/3598 0/5 DES-PT-40b-CTLFireability-12 472731000 t fired, 19246133 attempts, .
82 EF STEQ 329/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 331 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 20/298 14/32 DES-PT-40b-CTLFireability-10 2347304 m, 92656 m/sec, 8409194 t fired, .
75 EF FNDP 334/3598 0/5 DES-PT-40b-CTLFireability-12 479916125 t fired, 19538772 attempts, .
82 EF STEQ 334/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 336 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 25/298 16/32 DES-PT-40b-CTLFireability-10 2719606 m, 74460 m/sec, 10489247 t fired, .
75 EF FNDP 339/3598 0/5 DES-PT-40b-CTLFireability-12 487070202 t fired, 19830484 attempts, .
82 EF STEQ 339/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 341 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 30/298 18/32 DES-PT-40b-CTLFireability-10 3077068 m, 71492 m/sec, 12532430 t fired, .
75 EF FNDP 344/3598 0/5 DES-PT-40b-CTLFireability-12 494206193 t fired, 20121282 attempts, .
82 EF STEQ 344/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 346 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 35/298 20/32 DES-PT-40b-CTLFireability-10 3409291 m, 66444 m/sec, 14600729 t fired, .
75 EF FNDP 349/3598 0/5 DES-PT-40b-CTLFireability-12 501374237 t fired, 20413999 attempts, .
82 EF STEQ 349/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 351 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 40/298 22/32 DES-PT-40b-CTLFireability-10 3721409 m, 62423 m/sec, 16644200 t fired, .
75 EF FNDP 354/3598 0/5 DES-PT-40b-CTLFireability-12 508552620 t fired, 20705638 attempts, .
82 EF STEQ 354/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 356 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 45/298 23/32 DES-PT-40b-CTLFireability-10 4033729 m, 62464 m/sec, 18709057 t fired, .
75 EF FNDP 359/3598 0/5 DES-PT-40b-CTLFireability-12 515706425 t fired, 20996997 attempts, .
82 EF STEQ 359/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 361 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 50/298 25/32 DES-PT-40b-CTLFireability-10 4327420 m, 58738 m/sec, 20762294 t fired, .
75 EF FNDP 364/3598 0/5 DES-PT-40b-CTLFireability-12 522899196 t fired, 21289684 attempts, .
82 EF STEQ 364/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 366 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 55/298 26/32 DES-PT-40b-CTLFireability-10 4666521 m, 67820 m/sec, 22817882 t fired, .
75 EF FNDP 369/3598 0/5 DES-PT-40b-CTLFireability-12 530078881 t fired, 21582309 attempts, .
82 EF STEQ 369/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 371 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 60/298 28/32 DES-PT-40b-CTLFireability-10 4967188 m, 60133 m/sec, 24841974 t fired, .
75 EF FNDP 374/3598 0/5 DES-PT-40b-CTLFireability-12 537242285 t fired, 21873801 attempts, .
82 EF STEQ 374/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 376 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 65/298 30/32 DES-PT-40b-CTLFireability-10 5284640 m, 63490 m/sec, 26932044 t fired, .
75 EF FNDP 379/3598 0/5 DES-PT-40b-CTLFireability-12 544536903 t fired, 22171755 attempts, .
82 EF STEQ 379/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 381 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 70/298 31/32 DES-PT-40b-CTLFireability-10 5594093 m, 61890 m/sec, 29060412 t fired, .
75 EF FNDP 384/3598 0/5 DES-PT-40b-CTLFireability-12 551941253 t fired, 22473439 attempts, .
82 EF STEQ 384/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 386 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 48 (type EXCL) for DES-PT-40b-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 389/3598 0/5 DES-PT-40b-CTLFireability-12 559368096 t fired, 22775674 attempts, .
82 EF STEQ 389/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 391 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 45 (type EXCL) for 44 DES-PT-40b-CTLFireability-09
lola: time limit : 320 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for DES-PT-40b-CTLFireability-09
lola: result : false
lola: markings : 85
lola: fired transitions : 89
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 37 DES-PT-40b-CTLFireability-07
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/356 4/32 DES-PT-40b-CTLFireability-07 668034 m, 133606 m/sec, 2167633 t fired, .
75 EF FNDP 394/3598 0/5 DES-PT-40b-CTLFireability-12 566760232 t fired, 23076987 attempts, .
82 EF STEQ 394/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 396 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/356 7/32 DES-PT-40b-CTLFireability-07 1219506 m, 110294 m/sec, 4296185 t fired, .
75 EF FNDP 399/3598 0/5 DES-PT-40b-CTLFireability-12 574150686 t fired, 23378124 attempts, .
82 EF STEQ 399/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 401 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/356 10/32 DES-PT-40b-CTLFireability-07 1720923 m, 100283 m/sec, 6369038 t fired, .
75 EF FNDP 404/3598 0/5 DES-PT-40b-CTLFireability-12 581545508 t fired, 23678321 attempts, .
82 EF STEQ 404/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 406 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/356 14/32 DES-PT-40b-CTLFireability-07 2258389 m, 107493 m/sec, 8448579 t fired, .
75 EF FNDP 409/3598 0/5 DES-PT-40b-CTLFireability-12 588939866 t fired, 23980002 attempts, .
82 EF STEQ 409/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 411 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/356 17/32 DES-PT-40b-CTLFireability-07 2827618 m, 113845 m/sec, 10551362 t fired, .
75 EF FNDP 414/3598 0/5 DES-PT-40b-CTLFireability-12 596345883 t fired, 24282251 attempts, .
82 EF STEQ 414/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 416 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/356 20/32 DES-PT-40b-CTLFireability-07 3413437 m, 117163 m/sec, 12683960 t fired, .
75 EF FNDP 419/3598 0/5 DES-PT-40b-CTLFireability-12 603749980 t fired, 24583908 attempts, .
82 EF STEQ 419/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 421 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/356 23/32 DES-PT-40b-CTLFireability-07 3922899 m, 101892 m/sec, 14763097 t fired, .
75 EF FNDP 424/3598 0/5 DES-PT-40b-CTLFireability-12 611111537 t fired, 24883545 attempts, .
82 EF STEQ 424/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 426 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 40/356 26/32 DES-PT-40b-CTLFireability-07 4442115 m, 103843 m/sec, 16838649 t fired, .
75 EF FNDP 429/3598 0/5 DES-PT-40b-CTLFireability-12 618433009 t fired, 25182086 attempts, .
82 EF STEQ 429/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 431 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 45/356 29/32 DES-PT-40b-CTLFireability-07 5000256 m, 111628 m/sec, 18893840 t fired, .
75 EF FNDP 434/3598 0/5 DES-PT-40b-CTLFireability-12 625784385 t fired, 25481818 attempts, .
82 EF STEQ 434/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 436 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 40 (type EXCL) for DES-PT-40b-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 439/3598 0/5 DES-PT-40b-CTLFireability-12 633131436 t fired, 25781853 attempts, .
82 EF STEQ 439/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 441 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 35 (type EXCL) for 34 DES-PT-40b-CTLFireability-06
lola: time limit : 394 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/394 2/32 DES-PT-40b-CTLFireability-06 293582 m, 58716 m/sec, 2047294 t fired, .
75 EF FNDP 444/3598 0/5 DES-PT-40b-CTLFireability-12 640523073 t fired, 26083869 attempts, .
82 EF STEQ 444/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 446 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/394 3/32 DES-PT-40b-CTLFireability-06 577365 m, 56756 m/sec, 4092760 t fired, .
75 EF FNDP 449/3598 0/5 DES-PT-40b-CTLFireability-12 647852767 t fired, 26382188 attempts, .
82 EF STEQ 449/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 451 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 15/394 5/32 DES-PT-40b-CTLFireability-06 840800 m, 52687 m/sec, 6133567 t fired, .
75 EF FNDP 454/3598 0/5 DES-PT-40b-CTLFireability-12 655188334 t fired, 26681505 attempts, .
82 EF STEQ 454/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 456 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 20/394 6/32 DES-PT-40b-CTLFireability-06 1089838 m, 49807 m/sec, 8187446 t fired, .
75 EF FNDP 459/3598 0/5 DES-PT-40b-CTLFireability-12 662563718 t fired, 26982776 attempts, .
82 EF STEQ 459/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 461 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 25/394 7/32 DES-PT-40b-CTLFireability-06 1335542 m, 49140 m/sec, 10234417 t fired, .
75 EF FNDP 464/3598 0/5 DES-PT-40b-CTLFireability-12 669941581 t fired, 27282735 attempts, .
82 EF STEQ 464/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 30/394 8/32 DES-PT-40b-CTLFireability-06 1588358 m, 50563 m/sec, 12280347 t fired, .
75 EF FNDP 469/3598 0/5 DES-PT-40b-CTLFireability-12 677322603 t fired, 27583063 attempts, .
82 EF STEQ 469/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 471 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 35/394 10/32 DES-PT-40b-CTLFireability-06 1836872 m, 49702 m/sec, 14327419 t fired, .
75 EF FNDP 474/3598 0/5 DES-PT-40b-CTLFireability-12 684724381 t fired, 27884336 attempts, .
82 EF STEQ 474/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 476 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 40/394 11/32 DES-PT-40b-CTLFireability-06 2074637 m, 47553 m/sec, 16344502 t fired, .
75 EF FNDP 479/3598 0/5 DES-PT-40b-CTLFireability-12 692050409 t fired, 28183090 attempts, .
82 EF STEQ 479/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 481 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 45/394 12/32 DES-PT-40b-CTLFireability-06 2336485 m, 52369 m/sec, 18260825 t fired, .
75 EF FNDP 484/3598 0/5 DES-PT-40b-CTLFireability-12 699244975 t fired, 28476062 attempts, .
82 EF STEQ 484/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 486 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 50/394 13/32 DES-PT-40b-CTLFireability-06 2595974 m, 51897 m/sec, 20157514 t fired, .
75 EF FNDP 489/3598 0/5 DES-PT-40b-CTLFireability-12 706364730 t fired, 28764785 attempts, .
82 EF STEQ 489/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 491 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 55/394 14/32 DES-PT-40b-CTLFireability-06 2804113 m, 41627 m/sec, 22155729 t fired, .
75 EF FNDP 494/3598 0/5 DES-PT-40b-CTLFireability-12 713641163 t fired, 29060886 attempts, .
82 EF STEQ 494/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 496 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 60/394 16/32 DES-PT-40b-CTLFireability-06 3042367 m, 47650 m/sec, 24141538 t fired, .
75 EF FNDP 499/3598 0/5 DES-PT-40b-CTLFireability-12 720947520 t fired, 29358441 attempts, .
82 EF STEQ 499/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 501 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 65/394 17/32 DES-PT-40b-CTLFireability-06 3309545 m, 53435 m/sec, 26158795 t fired, .
75 EF FNDP 504/3598 0/5 DES-PT-40b-CTLFireability-12 728308732 t fired, 29658083 attempts, .
82 EF STEQ 504/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 506 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 71/394 18/32 DES-PT-40b-CTLFireability-06 3559661 m, 50023 m/sec, 28156908 t fired, .
75 EF FNDP 510/3598 0/5 DES-PT-40b-CTLFireability-12 735682932 t fired, 29958241 attempts, .
82 EF STEQ 510/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 512 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 76/394 19/32 DES-PT-40b-CTLFireability-06 3825954 m, 53258 m/sec, 30089276 t fired, .
75 EF FNDP 515/3598 0/5 DES-PT-40b-CTLFireability-12 742978238 t fired, 30255373 attempts, .
82 EF STEQ 515/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 517 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 81/394 21/32 DES-PT-40b-CTLFireability-06 4049994 m, 44808 m/sec, 32005640 t fired, .
75 EF FNDP 520/3598 0/5 DES-PT-40b-CTLFireability-12 750103463 t fired, 30545803 attempts, .
82 EF STEQ 520/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 522 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 86/394 22/32 DES-PT-40b-CTLFireability-06 4259322 m, 41865 m/sec, 33961854 t fired, .
75 EF FNDP 525/3598 0/5 DES-PT-40b-CTLFireability-12 757234377 t fired, 30836607 attempts, .
82 EF STEQ 525/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 527 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 91/394 23/32 DES-PT-40b-CTLFireability-06 4474441 m, 43023 m/sec, 35949633 t fired, .
75 EF FNDP 530/3598 0/5 DES-PT-40b-CTLFireability-12 764411464 t fired, 31128629 attempts, .
82 EF STEQ 530/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 532 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 96/394 24/32 DES-PT-40b-CTLFireability-06 4679406 m, 40993 m/sec, 37933539 t fired, .
75 EF FNDP 535/3598 0/5 DES-PT-40b-CTLFireability-12 771574153 t fired, 31420395 attempts, .
82 EF STEQ 535/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 537 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 101/394 25/32 DES-PT-40b-CTLFireability-06 4892054 m, 42529 m/sec, 39910785 t fired, .
75 EF FNDP 540/3598 0/5 DES-PT-40b-CTLFireability-12 778765898 t fired, 31713395 attempts, .
82 EF STEQ 540/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 542 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 106/394 26/32 DES-PT-40b-CTLFireability-06 5103047 m, 42198 m/sec, 41837554 t fired, .
75 EF FNDP 545/3598 0/5 DES-PT-40b-CTLFireability-12 785920624 t fired, 32006027 attempts, .
82 EF STEQ 545/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 547 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 111/394 27/32 DES-PT-40b-CTLFireability-06 5278280 m, 35046 m/sec, 43787068 t fired, .
75 EF FNDP 550/3598 0/5 DES-PT-40b-CTLFireability-12 793156240 t fired, 32300047 attempts, .
82 EF STEQ 550/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 552 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 116/394 28/32 DES-PT-40b-CTLFireability-06 5507959 m, 45935 m/sec, 45774879 t fired, .
75 EF FNDP 555/3598 0/5 DES-PT-40b-CTLFireability-12 800363616 t fired, 32594079 attempts, .
82 EF STEQ 555/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 557 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 121/394 29/32 DES-PT-40b-CTLFireability-06 5784380 m, 55284 m/sec, 47780802 t fired, .
75 EF FNDP 560/3598 0/5 DES-PT-40b-CTLFireability-12 807581027 t fired, 32888389 attempts, .
82 EF STEQ 560/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 562 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 126/394 30/32 DES-PT-40b-CTLFireability-06 6054271 m, 53978 m/sec, 49779281 t fired, .
75 EF FNDP 565/3598 0/5 DES-PT-40b-CTLFireability-12 814799603 t fired, 33182439 attempts, .
82 EF STEQ 565/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 567 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 131/394 32/32 DES-PT-40b-CTLFireability-06 6304179 m, 49981 m/sec, 51782947 t fired, .
75 EF FNDP 570/3598 0/5 DES-PT-40b-CTLFireability-12 822017300 t fired, 33476423 attempts, .
82 EF STEQ 570/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 572 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 35 (type EXCL) for DES-PT-40b-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 575/3598 0/5 DES-PT-40b-CTLFireability-12 829235859 t fired, 33770252 attempts, .
82 EF STEQ 575/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 577 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 32 (type EXCL) for 31 DES-PT-40b-CTLFireability-05
lola: time limit : 431 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/431 5/32 DES-PT-40b-CTLFireability-05 670534 m, 134106 m/sec, 2115641 t fired, .
75 EF FNDP 580/3598 0/5 DES-PT-40b-CTLFireability-12 836446955 t fired, 34064879 attempts, .
82 EF STEQ 580/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 582 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/431 8/32 DES-PT-40b-CTLFireability-05 1247128 m, 115318 m/sec, 4211732 t fired, .
75 EF FNDP 585/3598 0/5 DES-PT-40b-CTLFireability-12 843658766 t fired, 34358519 attempts, .
82 EF STEQ 585/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 587 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: FINISHED task # 32 (type EXCL) for DES-PT-40b-CTLFireability-05
lola: result : true
lola: markings : 1690263
lola: fired transitions : 6169804
lola: time used : 14.000000
lola: memory pages used : 10
lola: LAUNCH task # 26 (type EXCL) for 25 DES-PT-40b-CTLFireability-03
lola: time limit : 501 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 1/501 1/32 DES-PT-40b-CTLFireability-03 37930 m, 7586 m/sec, 110375 t fired, .
75 EF FNDP 590/3598 0/5 DES-PT-40b-CTLFireability-12 850865658 t fired, 34652664 attempts, .
82 EF STEQ 590/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 592 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: FINISHED task # 26 (type EXCL) for DES-PT-40b-CTLFireability-03
lola: result : true
lola: markings : 84000
lola: fired transitions : 275407
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DES-PT-40b-CTLFireability-00
lola: time limit : 601 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/601 4/32 DES-PT-40b-CTLFireability-00 580336 m, 116067 m/sec, 1958093 t fired, .
75 EF FNDP 595/3598 0/5 DES-PT-40b-CTLFireability-12 858076871 t fired, 34947000 attempts, .
82 EF STEQ 595/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 597 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/601 8/32 DES-PT-40b-CTLFireability-00 1211711 m, 126275 m/sec, 4081595 t fired, .
75 EF FNDP 600/3598 0/5 DES-PT-40b-CTLFireability-12 865278824 t fired, 35240285 attempts, .
82 EF STEQ 600/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 602 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/601 12/32 DES-PT-40b-CTLFireability-00 1846117 m, 126881 m/sec, 6200503 t fired, .
75 EF FNDP 605/3598 0/5 DES-PT-40b-CTLFireability-12 872487277 t fired, 35533654 attempts, .
82 EF STEQ 605/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 607 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/601 14/32 DES-PT-40b-CTLFireability-00 2318558 m, 94488 m/sec, 8326545 t fired, .
75 EF FNDP 610/3598 0/5 DES-PT-40b-CTLFireability-12 879694833 t fired, 35826984 attempts, .
82 EF STEQ 610/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 612 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/601 16/32 DES-PT-40b-CTLFireability-00 2672247 m, 70737 m/sec, 10441884 t fired, .
75 EF FNDP 615/3598 0/5 DES-PT-40b-CTLFireability-12 886902397 t fired, 36120517 attempts, .
82 EF STEQ 615/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 617 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/601 18/32 DES-PT-40b-CTLFireability-00 3004603 m, 66471 m/sec, 12541730 t fired, .
75 EF FNDP 620/3598 0/5 DES-PT-40b-CTLFireability-12 894103993 t fired, 36413848 attempts, .
82 EF STEQ 620/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 622 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/601 20/32 DES-PT-40b-CTLFireability-00 3337878 m, 66655 m/sec, 14646991 t fired, .
75 EF FNDP 625/3598 0/5 DES-PT-40b-CTLFireability-12 901316182 t fired, 36708971 attempts, .
82 EF STEQ 625/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 627 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/601 21/32 DES-PT-40b-CTLFireability-00 3648206 m, 62065 m/sec, 16743104 t fired, .
75 EF FNDP 630/3598 0/5 DES-PT-40b-CTLFireability-12 908521440 t fired, 37002250 attempts, .
82 EF STEQ 630/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 632 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/601 23/32 DES-PT-40b-CTLFireability-00 3990551 m, 68469 m/sec, 18848409 t fired, .
75 EF FNDP 635/3598 0/5 DES-PT-40b-CTLFireability-12 915731489 t fired, 37295826 attempts, .
82 EF STEQ 635/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 637 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/601 25/32 DES-PT-40b-CTLFireability-00 4309689 m, 63827 m/sec, 20940752 t fired, .
75 EF FNDP 640/3598 0/5 DES-PT-40b-CTLFireability-12 922942597 t fired, 37589051 attempts, .
82 EF STEQ 640/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 642 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/601 26/32 DES-PT-40b-CTLFireability-00 4644754 m, 67013 m/sec, 23031899 t fired, .
75 EF FNDP 645/3598 0/5 DES-PT-40b-CTLFireability-12 930147038 t fired, 37882134 attempts, .
82 EF STEQ 645/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 647 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/601 28/32 DES-PT-40b-CTLFireability-00 4980275 m, 67104 m/sec, 25131830 t fired, .
75 EF FNDP 650/3598 0/5 DES-PT-40b-CTLFireability-12 937351978 t fired, 38175618 attempts, .
82 EF STEQ 650/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 652 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/601 30/32 DES-PT-40b-CTLFireability-00 5294301 m, 62805 m/sec, 27221213 t fired, .
75 EF FNDP 655/3598 0/5 DES-PT-40b-CTLFireability-12 944550774 t fired, 38469486 attempts, .
82 EF STEQ 655/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 657 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/601 31/32 DES-PT-40b-CTLFireability-00 5589566 m, 59053 m/sec, 29309105 t fired, .
75 EF FNDP 660/3598 0/5 DES-PT-40b-CTLFireability-12 951758034 t fired, 38763406 attempts, .
82 EF STEQ 660/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 662 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: CANCELED task # 1 (type EXCL) for DES-PT-40b-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-01: DISJ 0 1 0 0 9 0 0 3
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
75 EF FNDP 665/3598 0/5 DES-PT-40b-CTLFireability-12 958969079 t fired, 39057437 attempts, .
82 EF STEQ 665/3598 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 667 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 15
lola: LAUNCH task # 83 (type EXCL) for 57 DES-PT-40b-CTLFireability-12
lola: time limit : 733 sec
lola: memory limit: 32 pages
lola: FINISHED task # 83 (type EXCL) for DES-PT-40b-CTLFireability-12
lola: result : true
lola: markings : 13969
lola: fired transitions : 17425
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 75 (type FNDP) for DES-PT-40b-CTLFireability-12 (obsolete)
lola: CANCELED task # 82 (type EQUN) for DES-PT-40b-CTLFireability-12 (obsolete)
lola: LAUNCH task # 42 (type EXCL) for 37 DES-PT-40b-CTLFireability-07
lola: time limit : 977 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type FNDP) for DES-PT-40b-CTLFireability-12
lola: result : unknown
lola: fired transitions : 959044545
lola: tried executions : 39060454
lola: time used : 665.000000
lola: memory pages used : 0
lola: FINISHED task # 82 (type EQUN) for DES-PT-40b-CTLFireability-12
lola: result : unknown
lola: FINISHED task # 42 (type EXCL) for DES-PT-40b-CTLFireability-07
lola: result : true
lola: markings : 23
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 6 (type EXCL) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 1466 sec
lola: memory limit: 32 pages
lola: FINISHED task # 6 (type EXCL) for DES-PT-40b-CTLFireability-01
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 DES-PT-40b-CTLFireability-13
lola: time limit : 2933 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 5/2933 5/32 DES-PT-40b-CTLFireability-13 779453 m, 155890 m/sec, 2941033 t fired, .
Time elapsed: 672 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 10/2933 8/32 DES-PT-40b-CTLFireability-13 1416928 m, 127495 m/sec, 5814128 t fired, .
Time elapsed: 677 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 15/2933 11/32 DES-PT-40b-CTLFireability-13 1876495 m, 91913 m/sec, 8725571 t fired, .
Time elapsed: 682 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 20/2933 13/32 DES-PT-40b-CTLFireability-13 2274655 m, 79632 m/sec, 11600601 t fired, .
Time elapsed: 687 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 25/2933 15/32 DES-PT-40b-CTLFireability-13 2718063 m, 88681 m/sec, 14446694 t fired, .
Time elapsed: 692 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 30/2933 17/32 DES-PT-40b-CTLFireability-13 3089854 m, 74358 m/sec, 17209217 t fired, .
Time elapsed: 697 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 35/2933 19/32 DES-PT-40b-CTLFireability-13 3469830 m, 75995 m/sec, 19944252 t fired, .
Time elapsed: 702 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 40/2933 21/32 DES-PT-40b-CTLFireability-13 3799508 m, 65935 m/sec, 22653508 t fired, .
Time elapsed: 707 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 45/2933 23/32 DES-PT-40b-CTLFireability-13 4219253 m, 83949 m/sec, 25373164 t fired, .
Time elapsed: 712 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 50/2933 25/32 DES-PT-40b-CTLFireability-13 4575864 m, 71322 m/sec, 28109962 t fired, .
Time elapsed: 717 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 55/2933 27/32 DES-PT-40b-CTLFireability-13 4951321 m, 75091 m/sec, 30835066 t fired, .
Time elapsed: 722 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 60/2933 29/32 DES-PT-40b-CTLFireability-13 5283103 m, 66356 m/sec, 33520600 t fired, .
Time elapsed: 727 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 CTL EXCL 65/2933 31/32 DES-PT-40b-CTLFireability-13 5700190 m, 83417 m/sec, 36231062 t fired, .
Time elapsed: 732 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 61 (type EXCL) for DES-PT-40b-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
DES-PT-40b-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 737 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: Portfolio finished: no open tasks 15
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-00: CTL unknown AGGR
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-02: CTL unknown AGGR
DES-PT-40b-CTLFireability-03: CTL true CTL model checker
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-05: CTL true CTL model checker
DES-PT-40b-CTLFireability-06: CTL unknown AGGR
DES-PT-40b-CTLFireability-07: CONJ unknown CONJ
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-10: CTL unknown AGGR
DES-PT-40b-CTLFireability-11: DISJ false DISJ
DES-PT-40b-CTLFireability-12: EF true state space
DES-PT-40b-CTLFireability-13: CTL unknown AGGR
DES-PT-40b-CTLFireability-14: CTL unknown AGGR
DES-PT-40b-CTLFireability-15: CTL true CTL model checker
Time elapsed: 737 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-40b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DES-PT-40b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478300466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-40b.tgz
mv DES-PT-40b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;