About the Execution of LoLa+red for DES-PT-05a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
2758.632 | 259198.00 | 257969.00 | 1230.50 | TFFFT?FFFTT?F??T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r103-tall-167814478300394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is DES-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r103-tall-167814478300394
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 7.7K Feb 26 15:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K Feb 26 15:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 26 15:45 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 15:45 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 15:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 15:48 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 113K Feb 26 15:48 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 15:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 15:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 37K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-05a-CTLFireability-00
FORMULA_NAME DES-PT-05a-CTLFireability-01
FORMULA_NAME DES-PT-05a-CTLFireability-02
FORMULA_NAME DES-PT-05a-CTLFireability-03
FORMULA_NAME DES-PT-05a-CTLFireability-04
FORMULA_NAME DES-PT-05a-CTLFireability-05
FORMULA_NAME DES-PT-05a-CTLFireability-06
FORMULA_NAME DES-PT-05a-CTLFireability-07
FORMULA_NAME DES-PT-05a-CTLFireability-08
FORMULA_NAME DES-PT-05a-CTLFireability-09
FORMULA_NAME DES-PT-05a-CTLFireability-10
FORMULA_NAME DES-PT-05a-CTLFireability-11
FORMULA_NAME DES-PT-05a-CTLFireability-12
FORMULA_NAME DES-PT-05a-CTLFireability-13
FORMULA_NAME DES-PT-05a-CTLFireability-14
FORMULA_NAME DES-PT-05a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678250255769
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-05a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 04:37:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 04:37:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 04:37:37] [INFO ] Load time of PNML (sax parser for PT used): 38 ms
[2023-03-08 04:37:37] [INFO ] Transformed 135 places.
[2023-03-08 04:37:37] [INFO ] Transformed 92 transitions.
[2023-03-08 04:37:37] [INFO ] Found NUPN structural information;
[2023-03-08 04:37:37] [INFO ] Parsed PT model containing 135 places and 92 transitions and 457 arcs in 95 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Ensure Unique test removed 14 transitions
Reduce redundant transitions removed 14 transitions.
Support contains 101 out of 135 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 135/135 places, 78/78 transitions.
Applied a total of 0 rules in 11 ms. Remains 135 /135 variables (removed 0) and now considering 78/78 (removed 0) transitions.
// Phase 1: matrix 78 rows 135 cols
[2023-03-08 04:37:37] [INFO ] Computed 59 place invariants in 15 ms
[2023-03-08 04:37:37] [INFO ] Implicit Places using invariants in 249 ms returned [32]
Discarding 1 places :
Implicit Place search using SMT only with invariants took 271 ms to find 1 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 134/135 places, 78/78 transitions.
Applied a total of 0 rules in 3 ms. Remains 134 /134 variables (removed 0) and now considering 78/78 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 285 ms. Remains : 134/135 places, 78/78 transitions.
Support contains 101 out of 134 places after structural reductions.
[2023-03-08 04:37:37] [INFO ] Flatten gal took : 28 ms
[2023-03-08 04:37:37] [INFO ] Flatten gal took : 14 ms
[2023-03-08 04:37:37] [INFO ] Input system was already deterministic with 78 transitions.
Incomplete random walk after 10000 steps, including 225 resets, run finished after 421 ms. (steps per millisecond=23 ) properties (out of 62) seen :57
Incomplete Best-First random walk after 10001 steps, including 45 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 51 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 49 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 56 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 37 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 5) seen :1
Running SMT prover for 4 properties.
// Phase 1: matrix 78 rows 134 cols
[2023-03-08 04:37:38] [INFO ] Computed 58 place invariants in 4 ms
[2023-03-08 04:37:38] [INFO ] [Real]Absence check using 33 positive place invariants in 5 ms returned sat
[2023-03-08 04:37:38] [INFO ] [Real]Absence check using 33 positive and 25 generalized place invariants in 6 ms returned sat
[2023-03-08 04:37:38] [INFO ] After 94ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:2
[2023-03-08 04:37:38] [INFO ] [Nat]Absence check using 33 positive place invariants in 6 ms returned sat
[2023-03-08 04:37:38] [INFO ] [Nat]Absence check using 33 positive and 25 generalized place invariants in 8 ms returned sat
[2023-03-08 04:37:38] [INFO ] After 67ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :2
[2023-03-08 04:37:38] [INFO ] After 108ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :2
Attempting to minimize the solution found.
Minimization took 38 ms.
[2023-03-08 04:37:38] [INFO ] After 233ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :2
Fused 4 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 14 ms.
Support contains 5 out of 134 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 134/134 places, 78/78 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 134 transition count 76
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 3 place count 133 transition count 75
Iterating global reduction 1 with 1 rules applied. Total rules applied 4 place count 133 transition count 75
Partial Free-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 1 with 6 rules applied. Total rules applied 10 place count 133 transition count 75
Applied a total of 10 rules in 29 ms. Remains 133 /134 variables (removed 1) and now considering 75/78 (removed 3) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 29 ms. Remains : 133/134 places, 75/78 transitions.
Incomplete random walk after 10000 steps, including 131 resets, run finished after 109 ms. (steps per millisecond=91 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 14 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 24 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 1308791 steps, run timeout after 3001 ms. (steps per millisecond=436 ) properties seen :{}
Probabilistic random walk after 1308791 steps, saw 182256 distinct states, run finished after 3001 ms. (steps per millisecond=436 ) properties seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 75 rows 133 cols
[2023-03-08 04:37:42] [INFO ] Computed 60 place invariants in 4 ms
[2023-03-08 04:37:42] [INFO ] [Real]Absence check using 35 positive place invariants in 5 ms returned sat
[2023-03-08 04:37:42] [INFO ] [Real]Absence check using 35 positive and 25 generalized place invariants in 5 ms returned sat
[2023-03-08 04:37:42] [INFO ] After 52ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 04:37:42] [INFO ] [Nat]Absence check using 35 positive place invariants in 9 ms returned sat
[2023-03-08 04:37:42] [INFO ] [Nat]Absence check using 35 positive and 25 generalized place invariants in 5 ms returned sat
[2023-03-08 04:37:42] [INFO ] After 78ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-08 04:37:42] [INFO ] State equation strengthened by 3 read => feed constraints.
[2023-03-08 04:37:42] [INFO ] After 19ms SMT Verify possible using 3 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-08 04:37:42] [INFO ] After 48ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 20 ms.
[2023-03-08 04:37:42] [INFO ] After 219ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Finished Parikh walk after 418 steps, including 2 resets, run visited all 2 properties in 4 ms. (steps per millisecond=104 )
Parikh walk visited 2 properties in 8 ms.
Successfully simplified 2 atomic propositions for a total of 16 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA DES-PT-05a-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA DES-PT-05a-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 9 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 78 transitions.
Computed a total of 37 stabilizing places and 32 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 7 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Applied a total of 0 rules in 5 ms. Remains 134 /134 variables (removed 0) and now considering 78/78 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 134/134 places, 78/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 78 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 10 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 5 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 4 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 3 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 8 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 7 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Applied a total of 0 rules in 2 ms. Remains 134 /134 variables (removed 0) and now considering 78/78 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 134/134 places, 78/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 78 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 3 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 3 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 3 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 133 transition count 77
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 133 transition count 77
Applied a total of 2 rules in 3 ms. Remains 133 /134 variables (removed 1) and now considering 77/78 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 133/134 places, 77/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 77 transitions.
Starting structural reductions in LTL mode, iteration 0 : 134/134 places, 78/78 transitions.
Applied a total of 0 rules in 1 ms. Remains 134 /134 variables (removed 0) and now considering 78/78 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 134/134 places, 78/78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 4 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Input system was already deterministic with 78 transitions.
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:37:42] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 04:37:42] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 134 places, 78 transitions and 390 arcs took 0 ms.
Total runtime 5794 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT DES-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/367
CTLFireability
FORMULA DES-PT-05a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-05a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678250514967
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/367/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/367/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/367/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 1 (type EXCL) for 0 DES-PT-05a-CTLFireability-00
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 1 (type EXCL) for DES-PT-05a-CTLFireability-00
lola: result : true
lola: markings : 46
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 13 (type EXCL) for 12 DES-PT-05a-CTLFireability-05
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/257 4/32 DES-PT-05a-CTLFireability-05 875747 m, 175149 m/sec, 5928175 t fired, .
Time elapsed: 6 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/257 8/32 DES-PT-05a-CTLFireability-05 1656716 m, 156193 m/sec, 11679900 t fired, .
Time elapsed: 11 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/257 12/32 DES-PT-05a-CTLFireability-05 2541005 m, 176857 m/sec, 17722898 t fired, .
Time elapsed: 16 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/257 15/32 DES-PT-05a-CTLFireability-05 3308607 m, 153520 m/sec, 23658413 t fired, .
Time elapsed: 21 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/257 18/32 DES-PT-05a-CTLFireability-05 4024591 m, 143196 m/sec, 29595872 t fired, .
Time elapsed: 26 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/257 21/32 DES-PT-05a-CTLFireability-05 4782206 m, 151523 m/sec, 35571287 t fired, .
Time elapsed: 31 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/257 24/32 DES-PT-05a-CTLFireability-05 5575391 m, 158637 m/sec, 41387511 t fired, .
Time elapsed: 36 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/257 28/32 DES-PT-05a-CTLFireability-05 6382483 m, 161418 m/sec, 47410201 t fired, .
Time elapsed: 41 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/257 31/32 DES-PT-05a-CTLFireability-05 7204145 m, 164332 m/sec, 53244172 t fired, .
Time elapsed: 46 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 13 (type EXCL) for DES-PT-05a-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 44 (type EXCL) for 43 DES-PT-05a-CTLFireability-15
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for DES-PT-05a-CTLFireability-15
lola: result : true
lola: markings : 46
lola: fired transitions : 180
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 DES-PT-05a-CTLFireability-14
lola: time limit : 295 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/295 4/32 DES-PT-05a-CTLFireability-14 875888 m, 175177 m/sec, 5929151 t fired, .
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/295 8/32 DES-PT-05a-CTLFireability-14 1653532 m, 155528 m/sec, 11657081 t fired, .
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/295 12/32 DES-PT-05a-CTLFireability-14 2533027 m, 175899 m/sec, 17656425 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/295 15/32 DES-PT-05a-CTLFireability-14 3290125 m, 151419 m/sec, 23508379 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/295 18/32 DES-PT-05a-CTLFireability-14 3989119 m, 139798 m/sec, 29280864 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/295 21/32 DES-PT-05a-CTLFireability-14 4710538 m, 144283 m/sec, 35108015 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 35/295 24/32 DES-PT-05a-CTLFireability-14 5507629 m, 159418 m/sec, 40853462 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 40/295 28/32 DES-PT-05a-CTLFireability-14 6309110 m, 160296 m/sec, 46825647 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 45/295 31/32 DES-PT-05a-CTLFireability-14 7097481 m, 157674 m/sec, 52545750 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 41 (type EXCL) for DES-PT-05a-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 2 0 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 38 (type EXCL) for 33 DES-PT-05a-CTLFireability-13
lola: time limit : 318 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/318 2/32 DES-PT-05a-CTLFireability-13 453008 m, 90601 m/sec, 6342839 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/318 4/32 DES-PT-05a-CTLFireability-13 845174 m, 78433 m/sec, 12390385 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/318 6/32 DES-PT-05a-CTLFireability-13 1203696 m, 71704 m/sec, 18292159 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/318 7/32 DES-PT-05a-CTLFireability-13 1591202 m, 77501 m/sec, 24227877 t fired, .
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/318 9/32 DES-PT-05a-CTLFireability-13 2006866 m, 83132 m/sec, 30327881 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/318 11/32 DES-PT-05a-CTLFireability-13 2428158 m, 84258 m/sec, 36387641 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/318 13/32 DES-PT-05a-CTLFireability-13 2794228 m, 73214 m/sec, 42285308 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/318 14/32 DES-PT-05a-CTLFireability-13 3118604 m, 64875 m/sec, 47963049 t fired, .
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 45/318 15/32 DES-PT-05a-CTLFireability-13 3468961 m, 70071 m/sec, 53867035 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/318 17/32 DES-PT-05a-CTLFireability-13 3778543 m, 61916 m/sec, 59582333 t fired, .
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 55/318 18/32 DES-PT-05a-CTLFireability-13 4109656 m, 66222 m/sec, 65347492 t fired, .
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 60/318 20/32 DES-PT-05a-CTLFireability-13 4439408 m, 65950 m/sec, 71200762 t fired, .
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 65/318 21/32 DES-PT-05a-CTLFireability-13 4807637 m, 73645 m/sec, 77257545 t fired, .
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 70/318 23/32 DES-PT-05a-CTLFireability-13 5188196 m, 76111 m/sec, 82953014 t fired, .
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 75/318 24/32 DES-PT-05a-CTLFireability-13 5520411 m, 66443 m/sec, 88666353 t fired, .
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 80/318 26/32 DES-PT-05a-CTLFireability-13 5864677 m, 68853 m/sec, 94581231 t fired, .
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 85/318 27/32 DES-PT-05a-CTLFireability-13 6264809 m, 80026 m/sec, 100677482 t fired, .
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 90/318 29/32 DES-PT-05a-CTLFireability-13 6674763 m, 81990 m/sec, 107042396 t fired, .
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 1 0 2 0 0 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 95/318 31/32 DES-PT-05a-CTLFireability-13 7067296 m, 78506 m/sec, 113170930 t fired, .
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 38 (type EXCL) for DES-PT-05a-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 1 0 0 2 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 36 (type EXCL) for 33 DES-PT-05a-CTLFireability-13
lola: time limit : 339 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for DES-PT-05a-CTLFireability-13
lola: result : false
lola: markings : 45
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 DES-PT-05a-CTLFireability-12
lola: time limit : 377 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for DES-PT-05a-CTLFireability-12
lola: result : false
lola: markings : 81
lola: fired transitions : 178
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 DES-PT-05a-CTLFireability-11
lola: time limit : 424 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/424 4/32 DES-PT-05a-CTLFireability-11 903431 m, 180686 m/sec, 6130865 t fired, .
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/424 8/32 DES-PT-05a-CTLFireability-11 1708794 m, 161072 m/sec, 12074318 t fired, .
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/424 12/32 DES-PT-05a-CTLFireability-11 2615151 m, 181271 m/sec, 18298555 t fired, .
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/424 15/32 DES-PT-05a-CTLFireability-11 3402285 m, 157426 m/sec, 24384002 t fired, .
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/424 18/32 DES-PT-05a-CTLFireability-11 4137131 m, 146969 m/sec, 30450873 t fired, .
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/424 22/32 DES-PT-05a-CTLFireability-11 4954406 m, 163455 m/sec, 36674320 t fired, .
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/424 25/32 DES-PT-05a-CTLFireability-11 5740340 m, 157186 m/sec, 42698116 t fired, .
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/424 29/32 DES-PT-05a-CTLFireability-11 6593407 m, 170613 m/sec, 48960248 t fired, .
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/424 32/32 DES-PT-05a-CTLFireability-11 7430074 m, 167333 m/sec, 54833256 t fired, .
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 28 (type EXCL) for DES-PT-05a-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-08: AGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-09: EGEF 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-05a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
DES-PT-05a-CTLFireability-13: DISJ 0 0 0 0 3 0 1 0
DES-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 25 (type EXCL) for 24 DES-PT-05a-CTLFireability-10
lola: time limit : 478 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for DES-PT-05a-CTLFireability-10
lola: result : true
lola: markings : 77217
lola: fired transitions : 303522
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 DES-PT-05a-CTLFireability-06
lola: time limit : 558 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for DES-PT-05a-CTLFireability-06
lola: result : false
lola: markings : 8483
lola: fired transitions : 39719
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DES-PT-05a-CTLFireability-04
lola: time limit : 669 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for DES-PT-05a-CTLFireability-04
lola: result : true
lola: markings : 117261
lola: fired transitions : 333769
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 DES-PT-05a-CTLFireability-02
lola: time limit : 837 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for DES-PT-05a-CTLFireability-02
lola: result : false
lola: markings : 46
lola: fired transitions : 137
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 DES-PT-05a-CTLFireability-01
lola: time limit : 1116 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DES-PT-05a-CTLFireability-01
lola: result : false
lola: markings : 87
lola: fired transitions : 101
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 DES-PT-05a-CTLFireability-09
lola: time limit : 1674 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for DES-PT-05a-CTLFireability-09
lola: result : true
lola: markings : 46
lola: fired transitions : 93
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 DES-PT-05a-CTLFireability-08
lola: time limit : 3349 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for DES-PT-05a-CTLFireability-08
lola: result : false
lola: markings : 37
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-05a-CTLFireability-00: CTL true CTL model checker
DES-PT-05a-CTLFireability-01: CTL false CTL model checker
DES-PT-05a-CTLFireability-02: CTL false CTL model checker
DES-PT-05a-CTLFireability-04: CTL true CTL model checker
DES-PT-05a-CTLFireability-05: CTL unknown AGGR
DES-PT-05a-CTLFireability-06: CTL false CTL model checker
DES-PT-05a-CTLFireability-08: AGEF false tscc_search
DES-PT-05a-CTLFireability-09: EGEF true CTL model checker
DES-PT-05a-CTLFireability-10: CTL true CTL model checker
DES-PT-05a-CTLFireability-11: CTL unknown AGGR
DES-PT-05a-CTLFireability-12: CTL false CTL model checker
DES-PT-05a-CTLFireability-13: DISJ unknown DISJ
DES-PT-05a-CTLFireability-14: CTL unknown AGGR
DES-PT-05a-CTLFireability-15: CTL true CTL model checker
Time elapsed: 251 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is DES-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r103-tall-167814478300394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-05a.tgz
mv DES-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;