Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477400860.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCshifumi-PT-6a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477400860
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 7.4M
-rw-r--r-- 1 mcc users 8.8K Feb 27 04:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 101K Feb 27 04:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 27 00:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K Feb 27 00:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 27 09:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 147K Feb 27 09:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 27 06:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 27 06:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.9M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-00
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-01
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-02
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-03
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-04
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-05
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-06
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-07
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-08
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-09
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-10
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-11
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-12
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-13
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-14
FORMULA_NAME DLCshifumi-PT-6a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678338413159

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCshifumi-PT-6a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCshifumi-PT-6a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA DLCshifumi-PT-6a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCshifumi-PT-6a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678338918321

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 84 (type SKEL/SRCH) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/SRCH) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 87 (type SKEL/FNDP) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type SKEL/EQUN) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 89 (type SKEL/SRCH) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 90 (type SKEL/SRCH) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 89 (type SKEL/SRCH) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 87 (type FNDP) for DLCshifumi-PT-6a-LTLFireability-00 (obsolete)
lola: CANCELED task # 88 (type EQUN) for DLCshifumi-PT-6a-LTLFireability-00 (obsolete)
lola: CANCELED task # 90 (type SRCH) for DLCshifumi-PT-6a-LTLFireability-00 (obsolete)
lola: FINISHED task # 90 (type SKEL/SRCH) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 87 (type SKEL/FNDP) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-88.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 88 (type SKEL/EQUN) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 5 0 0 0
DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-06: CONJ 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-12: CONJ 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 0 0 0 0
DLCshifumi-PT-6a-LTLFireability-15: AG 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 37 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 7 (type CNST) for 0 DLCshifumi-PT-6a-LTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 7 (type CNST) for DLCshifumi-PT-6a-LTLFireability-00
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 37 (type CNST) for 34 DLCshifumi-PT-6a-LTLFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 37 (type CNST) for DLCshifumi-PT-6a-LTLFireability-06
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-6a-LTLFireability-06: CONJ false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 6 0 0 0
DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
DLCshifumi-PT-6a-LTLFireability-12: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-15: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 42 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-6a-LTLFireability-06: CONJ false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-6a-LTLFireability-00: CONJ 0 0 0 0 6 0 0 0
DLCshifumi-PT-6a-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
DLCshifumi-PT-6a-LTLFireability-12: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-14: CONJ 0 0 0 0 2 0 0 0
DLCshifumi-PT-6a-LTLFireability-15: AG 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 47 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-6a-LTLFireability-06: CONJ false preprocessing

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DLCshifumi-PT-6a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-6a-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
DLCshifumi-PT-6a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 LTL EXCL 19/519 1/32 DLCshifumi-PT-6a-LTLFireability-10 54089 m, 3224 m/sec, 3435014 t fired, .

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ltlfireabilityconf --formula=$DIR/LTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-6a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-6a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477400860"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-6a.tgz
mv DLCshifumi-PT-6a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;