About the Execution of LoLA for DLCshifumi-PT-4b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16222.260 | 428633.00 | 713705.00 | 10066.40 | ????TT????T???F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477400834.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCshifumi-PT-4b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477400834
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.5M
-rw-r--r-- 1 mcc users 6.8K Feb 26 07:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 26 07:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K Feb 26 07:33 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K Feb 26 07:33 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:54 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:54 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:54 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:54 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.6K Feb 26 07:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 97K Feb 26 07:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 07:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 07:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:54 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:54 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 5.1M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-00
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-01
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-02
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-03
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-04
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-05
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-06
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-07
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-08
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-09
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-10
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-11
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-12
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-13
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-14
FORMULA_NAME DLCshifumi-PT-4b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678334779825
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCshifumi-PT-4b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCshifumi-PT-4b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCshifumi-PT-4b-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-4b-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-4b-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCshifumi-PT-4b-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678335208458
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 99 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 104 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 4.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 109 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 114 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 119 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 124 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 129 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 4.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 134 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 139 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 144 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 13.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 149 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 154 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 159 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 7.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 164 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-04: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-05: EF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 169 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type EXCL) for 15 DLCshifumi-PT-4b-CTLFireability-05
lola: time limit : 190 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 48 (type FNDP) for 15 DLCshifumi-PT-4b-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 15 DLCshifumi-PT-4b-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SRCH) for 15 DLCshifumi-PT-4b-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 54 (type SRCH) for DLCshifumi-PT-4b-CTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type FNDP) for 42 DLCshifumi-PT-4b-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type EXCL) for DLCshifumi-PT-4b-CTLFireability-05
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for DLCshifumi-PT-4b-CTLFireability-05 (obsolete)
lola: CANCELED task # 51 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-05 (obsolete)
lola: LAUNCH task # 56 (type EXCL) for 12 DLCshifumi-PT-4b-CTLFireability-04
lola: time limit : 190 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type FNDP) for 12 DLCshifumi-PT-4b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 12 DLCshifumi-PT-4b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type EXCL) for DLCshifumi-PT-4b-CTLFireability-04
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 52 (type FNDP) for DLCshifumi-PT-4b-CTLFireability-04 (obsolete)
lola: CANCELED task # 55 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-04 (obsolete)
lola: LAUNCH task # 59 (type EXCL) for 42 DLCshifumi-PT-4b-CTLFireability-14
lola: time limit : 201 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 58 (type EQUN) for 42 DLCshifumi-PT-4b-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SRCH) for 42 DLCshifumi-PT-4b-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 60 (type SRCH) for DLCshifumi-PT-4b-CTLFireability-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 51 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-05
lola: result : unknown
lola: FINISHED task # 48 (type FNDP) for DLCshifumi-PT-4b-CTLFireability-05
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 50 (type FNDP) for DLCshifumi-PT-4b-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 58 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-14 (obsolete)
lola: CANCELED task # 59 (type EXCL) for DLCshifumi-PT-4b-CTLFireability-14 (obsolete)
lola: FINISHED task # 52 (type FNDP) for DLCshifumi-PT-4b-CTLFireability-04
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-55.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 55 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-04
lola: result : true
sara: try reading problem file /home/mcc/execution/CTLFireability-58.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 58 (type EQUN) for DLCshifumi-PT-4b-CTLFireability-14
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 174 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 0 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 179 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 8.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 31 (type EXCL) for 30 DLCshifumi-PT-4b-CTLFireability-10
lola: time limit : 244 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 31 (type EXCL) for DLCshifumi-PT-4b-CTLFireability-10
lola: result : true
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 DLCshifumi-PT-4b-CTLFireability-15
lola: time limit : 263 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 3/263 1/32 DLCshifumi-PT-4b-CTLFireability-15 24641 m, 4928 m/sec, 184663 t fired, .
Time elapsed: 184 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 8/263 1/32 DLCshifumi-PT-4b-CTLFireability-15 68565 m, 8784 m/sec, 501935 t fired, .
Time elapsed: 189 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 0 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 13/263 2/32 DLCshifumi-PT-4b-CTLFireability-15 113915 m, 9070 m/sec, 841642 t fired, .
Time elapsed: 194 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: Created skeleton in 8.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 18/284 2/32 DLCshifumi-PT-4b-CTLFireability-15 149472 m, 7111 m/sec, 1107855 t fired, .
Time elapsed: 199 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 23/284 3/32 DLCshifumi-PT-4b-CTLFireability-15 182040 m, 6513 m/sec, 1355242 t fired, .
Time elapsed: 204 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 28/284 3/32 DLCshifumi-PT-4b-CTLFireability-15 234960 m, 10584 m/sec, 1754489 t fired, .
Time elapsed: 209 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 33/284 4/32 DLCshifumi-PT-4b-CTLFireability-15 282848 m, 9577 m/sec, 2123336 t fired, .
Time elapsed: 214 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 38/284 4/32 DLCshifumi-PT-4b-CTLFireability-15 327374 m, 8905 m/sec, 2465934 t fired, .
Time elapsed: 219 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 43/284 4/32 DLCshifumi-PT-4b-CTLFireability-15 373453 m, 9215 m/sec, 2823825 t fired, .
Time elapsed: 224 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 48/284 5/32 DLCshifumi-PT-4b-CTLFireability-15 420410 m, 9391 m/sec, 3178944 t fired, .
Time elapsed: 229 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 53/284 5/32 DLCshifumi-PT-4b-CTLFireability-15 469417 m, 9801 m/sec, 3563930 t fired, .
Time elapsed: 234 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 58/284 6/32 DLCshifumi-PT-4b-CTLFireability-15 516899 m, 9496 m/sec, 3932402 t fired, .
Time elapsed: 239 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 63/284 7/32 DLCshifumi-PT-4b-CTLFireability-15 589054 m, 14431 m/sec, 4493843 t fired, .
Time elapsed: 244 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 68/284 7/32 DLCshifumi-PT-4b-CTLFireability-15 678664 m, 17922 m/sec, 5149209 t fired, .
Time elapsed: 249 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 73/284 8/32 DLCshifumi-PT-4b-CTLFireability-15 778842 m, 20035 m/sec, 5894787 t fired, .
Time elapsed: 254 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 78/284 9/32 DLCshifumi-PT-4b-CTLFireability-15 884453 m, 21122 m/sec, 6705846 t fired, .
Time elapsed: 259 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 83/284 9/32 DLCshifumi-PT-4b-CTLFireability-15 984438 m, 19997 m/sec, 7464710 t fired, .
Time elapsed: 264 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 88/284 10/32 DLCshifumi-PT-4b-CTLFireability-15 1088736 m, 20859 m/sec, 8243271 t fired, .
Time elapsed: 269 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 93/284 11/32 DLCshifumi-PT-4b-CTLFireability-15 1194824 m, 21217 m/sec, 9064389 t fired, .
Time elapsed: 274 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 98/284 11/32 DLCshifumi-PT-4b-CTLFireability-15 1299092 m, 20853 m/sec, 9873464 t fired, .
Time elapsed: 279 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 103/284 12/32 DLCshifumi-PT-4b-CTLFireability-15 1404164 m, 21014 m/sec, 10693878 t fired, .
Time elapsed: 284 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 108/284 13/32 DLCshifumi-PT-4b-CTLFireability-15 1509583 m, 21083 m/sec, 11507809 t fired, .
Time elapsed: 289 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 113/284 14/32 DLCshifumi-PT-4b-CTLFireability-15 1611290 m, 20341 m/sec, 12311955 t fired, .
Time elapsed: 294 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 118/284 15/32 DLCshifumi-PT-4b-CTLFireability-15 1715753 m, 20892 m/sec, 13115199 t fired, .
Time elapsed: 299 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 123/284 15/32 DLCshifumi-PT-4b-CTLFireability-15 1814095 m, 19668 m/sec, 13874936 t fired, .
Time elapsed: 304 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 128/284 16/32 DLCshifumi-PT-4b-CTLFireability-15 1911136 m, 19408 m/sec, 14626980 t fired, .
Time elapsed: 309 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 133/284 17/32 DLCshifumi-PT-4b-CTLFireability-15 2013336 m, 20440 m/sec, 15427481 t fired, .
Time elapsed: 314 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 138/284 17/32 DLCshifumi-PT-4b-CTLFireability-15 2110834 m, 19499 m/sec, 16183622 t fired, .
Time elapsed: 319 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 143/284 18/32 DLCshifumi-PT-4b-CTLFireability-15 2212984 m, 20430 m/sec, 16987139 t fired, .
Time elapsed: 324 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 148/284 19/32 DLCshifumi-PT-4b-CTLFireability-15 2315997 m, 20602 m/sec, 17791072 t fired, .
Time elapsed: 329 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 153/284 19/32 DLCshifumi-PT-4b-CTLFireability-15 2416129 m, 20026 m/sec, 18585142 t fired, .
Time elapsed: 334 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 158/284 20/32 DLCshifumi-PT-4b-CTLFireability-15 2493835 m, 15541 m/sec, 19183813 t fired, .
Time elapsed: 339 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 163/284 21/32 DLCshifumi-PT-4b-CTLFireability-15 2601578 m, 21548 m/sec, 19983262 t fired, .
Time elapsed: 344 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 168/284 22/32 DLCshifumi-PT-4b-CTLFireability-15 2706373 m, 20959 m/sec, 20763112 t fired, .
Time elapsed: 349 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 173/284 23/32 DLCshifumi-PT-4b-CTLFireability-15 2813681 m, 21461 m/sec, 21563405 t fired, .
Time elapsed: 354 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 178/284 24/32 DLCshifumi-PT-4b-CTLFireability-15 2913404 m, 19944 m/sec, 22338913 t fired, .
Time elapsed: 359 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 183/284 24/32 DLCshifumi-PT-4b-CTLFireability-15 3009213 m, 19161 m/sec, 23097459 t fired, .
Time elapsed: 364 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 188/284 25/32 DLCshifumi-PT-4b-CTLFireability-15 3084564 m, 15070 m/sec, 23693319 t fired, .
Time elapsed: 369 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 193/284 25/32 DLCshifumi-PT-4b-CTLFireability-15 3160408 m, 15168 m/sec, 24293286 t fired, .
Time elapsed: 374 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 210/284 26/32 DLCshifumi-PT-4b-CTLFireability-15 3214232 m, 10764 m/sec, 24717974 t fired, .
Time elapsed: 392 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 229/284 26/32 DLCshifumi-PT-4b-CTLFireability-15 3214305 m, 14 m/sec, 24718586 t fired, .
Time elapsed: 410 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCshifumi-PT-4b-CTLFireability-04: EF true state space
DLCshifumi-PT-4b-CTLFireability-05: EF true state space
DLCshifumi-PT-4b-CTLFireability-10: CTL true CTL model checker
DLCshifumi-PT-4b-CTLFireability-14: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCshifumi-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-03: SP ECTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-12: EGEF 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCshifumi-PT-4b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 247/284 26/32 DLCshifumi-PT-4b-CTLFireability-15 3214582 m, 55 m/sec, 24720657 t fired, .
Time elapsed: 428 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCshifumi-PT-4b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCshifumi-PT-4b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477400834"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCshifumi-PT-4b.tgz
mv DLCshifumi-PT-4b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;