MCC'2023- Execution of r102-tall-167814477300786

About the Execution of LoLA for DLCround-PT-13b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	434099.00	0.00	0.00	????T?F????T???T	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.
Waiting for the VM to be
..................................
============
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-13b,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r102-tall-16
==================================

--------------------
preparation of the directory
/home/mcc/execution
total 2.5M
-rw-r--r-- 1 mcc users 6.3K
-rw-r--r-- 1 mcc users 63K
-rw-r--r-- 1 mcc users 5.6K
-rw-r--r-- 1 mcc users 50K
-rw-r--r-- 1 mcc users 4.2K
-rw-r--r-- 1 mcc users 6.4K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users 24K
-rw-r--r-- 1 mcc users 2.2K
-rw-r--r-- 1 mcc users 16K
-rw-r--r-- 1 mcc users 12K
-rw-r--r-- 1 mcc users 128K
-rw-r--r-- 1 mcc users 6.4K
-rw-r--r-- 1 mcc users 49K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users
-rw-r--r-- 1 mcc users 2.1M Mar

--------------------
content from stdout:

=== Data for post analysis

The expected result is a
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi
FORMULA_NAME DLCround-PT-13b-CTLFi

=== Now, execution of the

BK_START 1678329150943

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-13b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-13b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/
current directory: /home/mcc/execu
CTLFireability

FORMULA DLCround-PT-13b-CTLFireability-04

FORMULA DLCround-PT-13b-CTLFireability-06

FORMULA DLCround-PT-13b-CTLFireability-15

FORMULA DLCround-PT-13b-CTLFireability-11

BK_STOP 1678329585042

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file
lola: reading net from
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/
lola: Reading formula.
lola: Using XML format
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Rule S: 0 transitions
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 26 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
FINISHED FORMULA: CATEGORY

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 31 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: Created skeleton
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 62
lola: time limit : 162 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 60
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 61
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: LAUNCH task # 63
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 63
lola: result
lola: time used :
lola: memory pages used :
lola: FINISHED task # 62
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: CANCELED task # 60
lola: CANCELED task # 61
lola: FINISHED task # 60
lola: result
lola: fired transitions :
lola: tried executions :
lola: time used :
lola: memory pages used :
lola: FINISHED task # 61
lola: result
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 36 secs.
# running tasks: 0 of 4 Visible:
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: LAUNCH task # 23
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: FINISHED task # 23
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 35
lola: time limit : 187 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 3/187

Time elapsed: 41 secs.
# running tasks: 1 of 4 Visible:
lola: Created skeleton
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 8/197

Time elapsed: 46 secs.
# running tasks: 1 of 4 Visible:
lola: Created skeleton
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
lola: rewrite Frontend/Parser/fo
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 13/209

Time elapsed: 51 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 18/209

Time elapsed: 56 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 23/209

Time elapsed: 61 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 28/209

Time elapsed: 66 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 33/209

Time elapsed: 71 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 38/209

Time elapsed: 76 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 43/209

Time elapsed: 81 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 48/209

Time elapsed: 86 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 53/209

Time elapsed: 91 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 58/209

Time elapsed: 96 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 63/209

Time elapsed: 101 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 68/209

Time elapsed: 106 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 73/209

Time elapsed: 111 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 78/209

Time elapsed: 116 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 83/209

Time elapsed: 121 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 88/209

Time elapsed: 126 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 93/209

Time elapsed: 131 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 98/209

Time elapsed: 136 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 103/209

Time elapsed: 141 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 111/209

Time elapsed: 149 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 116/209

Time elapsed: 154 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 121/209

Time elapsed: 159 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 126/209

Time elapsed: 164 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT
35 CTL EXCL 131/209

Time elapsed: 169 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 35
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:
DLCround-PT-13b-CTLFireability-15:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 174 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 58
lola: time limit : 214 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 55
lola: time limit : 228 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 5/228

Time elapsed: 179 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 10/228

Time elapsed: 184 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 15/228

Time elapsed: 189 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 20/228

Time elapsed: 194 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 25/228

Time elapsed: 199 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 30/228

Time elapsed: 204 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 35/228

Time elapsed: 209 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 40/228

Time elapsed: 214 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 45/228

Time elapsed: 219 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 50/228

Time elapsed: 224 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 55/228

Time elapsed: 229 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 60/228

Time elapsed: 234 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 65/228

Time elapsed: 239 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 70/228

Time elapsed: 244 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 75/228

Time elapsed: 249 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 80/228

Time elapsed: 254 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 85/228

Time elapsed: 259 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 90/228

Time elapsed: 264 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 95/228

Time elapsed: 269 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 100/228

Time elapsed: 274 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 105/228

Time elapsed: 279 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 110/228

Time elapsed: 284 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 115/228

Time elapsed: 289 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 120/228

Time elapsed: 294 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 125/228

Time elapsed: 299 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
55 CTL EXCL 130/228

Time elapsed: 304 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 55
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 309 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 49
lola: time limit : 235 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 5/235

Time elapsed: 314 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 10/235

Time elapsed: 319 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 15/235

Time elapsed: 324 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 20/235

Time elapsed: 329 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 25/235

Time elapsed: 334 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 30/235

Time elapsed: 339 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 35/235

Time elapsed: 344 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 40/235

Time elapsed: 349 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 45/235

Time elapsed: 354 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 50/235

Time elapsed: 359 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 55/235

Time elapsed: 364 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 60/235

Time elapsed: 369 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 65/235

Time elapsed: 374 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 71/235

Time elapsed: 380 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 76/235

Time elapsed: 385 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 81/235

Time elapsed: 390 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 86/235

Time elapsed: 395 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
49 CTL EXCL 91/235

Time elapsed: 400 secs.
# running tasks: 1 of 4 Visible:
lola: CANCELED task # 49
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT

Time elapsed: 405 secs.
# running tasks: 1 of 4 Visible:
lola: LAUNCH task # 46
lola: time limit : 245 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46
lola: result
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 29
lola: time limit : 319 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
29 CTL EXCL 5/319

Time elapsed: 410 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
29 CTL EXCL 10/319

Time elapsed: 415 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
29 CTL EXCL 15/319

Time elapsed: 420 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
29 CTL EXCL 20/319

Time elapsed: 425 secs.
# running tasks: 1 of 4 Visible:
FINISHED FORMULA: CATEGORY
DLCround-PT-13b-CTLFireability-04:
DLCround-PT-13b-CTLFireability-06:
DLCround-PT-13b-CTLFireability-11:
DLCround-PT-13b-CTLFireability-15:

PENDING FORMULAS: CATEGORY
DLCround-PT-13b-CTLFireability-00:
DLCround-PT-13b-CTLFireability-01:
DLCround-PT-13b-CTLFireability-02:
DLCround-PT-13b-CTLFireability-03:
DLCround-PT-13b-CTLFireability-05:
DLCround-PT-13b-CTLFireability-07:
DLCround-PT-13b-CTLFireability-08:
DLCround-PT-13b-CTLFireability-09:
DLCround-PT-13b-CTLFireability-10:
DLCround-PT-13b-CTLFireability-12:
DLCround-PT-13b-CTLFireability-13:
DLCround-PT-13b-CTLFireability-14:

TASK CATEGORY TYPE TIME/TLIMIT
29 CTL EXCL 25/319

Time elapsed: 430 secs.
# running tasks: 1 of 4 Visible:
/home/mcc/BenchKit/bin//../lola/bi
r102-tall-167814477300786.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ready (probing ssh) .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... ========================================================= examination is CTLFireability seconds 16384 MBytes 7814477300786 =================================== to be used: Feb 25 18:45 CTLCardinality.txt Feb 25 18:45 CTLCardinality.xml Feb 25 18:45 CTLFireability.txt Feb 25 18:45 CTLFireability.xml Jan 29 11:40 GenericPropertiesDefinition.xml Jan 29 11:40 GenericPropertiesVerdict.xml Feb 25 15:53 LTLCardinality.txt Feb 25 15:53 LTLCardinality.xml Feb 25 15:53 LTLFireability.txt Feb 25 15:53 LTLFireability.xml Feb 25 18:46 ReachabilityCardinality.txt Feb 25 18:46 ReachabilityCardinality.xml Feb 25 18:46 ReachabilityFireability.txt Feb 25 18:46 ReachabilityFireability.xml Feb 25 15:53 UpperBounds.txt Feb 25 15:53 UpperBounds.xml 6 Mar 5 18:22 equiv_col 4 Mar 5 18:22 instance 6 Mar 5 18:22 iscolored 5 18:22 model.pnml generated by BenchKit (invocation template) vector of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N / bin//../lola/bin/ tion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT (--pnmlnet) /home/mcc/execution/model.pnml place/transition net execution/model.pnml (--xmlformula) /home/mcc/execution/CTLFireability.xml rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:445 rmula_rewrite.k:547 rmula_rewrite.k:451 rmula_rewrite.k:250 rmula_rewrite.k:314 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:544 rmula_rewrite.k:317 rmula_rewrite.k:296 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:296 rmula_rewrite.k:250 rmula_rewrite.k:547 rmula_rewrite.k:400 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:388 rmula_rewrite.k:250 rmula_rewrite.k:547 rmula_rewrite.k:253 rmula_rewrite.k:547 rmula_rewrite.k:547 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:325 rmula_rewrite.k:328 rmula_rewrite.k:296 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:550 rmula_rewrite.k:550 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:314 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:322 rmula_rewrite.k:331 rmula_rewrite.k:299 rmula_rewrite.k:322 rmula_rewrite.k:334 rmula_rewrite.k:322 rmula_rewrite.k:328 rmula_rewrite.k:299 rmula_rewrite.k:472 rmula_rewrite.k:325 rmula_rewrite.k:337 rmula_rewrite.k:317 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:296 rmula_rewrite.k:317 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:96 rmula_rewrite.k:138 rmula_rewrite.k:199 rmula_rewrite.k:147 rmula_rewrite.k:325 rmula_rewrite.k:331 rmula_rewrite.k:322 rmula_rewrite.k:337 rmula_rewrite.k:296 rmula_rewrite.k:296 rmula_rewrite.k:475 in 1.000000 secs. in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 1.000000 secs. removed,0 places removed VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 1.000000 secs. in 0.000000 secs. in 1.000000 secs. in 0.000000 secs. in 2.000000 secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 2 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 0 16 in 2.000000 secs. in 2.000000 secs. in 1.000000 secs. rmula_rewrite.k:711 rmula_rewrite.k:711 rmula_rewrite.k:711 (type EXCL) for 16 DLCround-PT-13b-CTLFireability-04 (type FNDP) for 16 DLCround-PT-13b-CTLFireability-04 sec (type EQUN) for 16 DLCround-PT-13b-CTLFireability-04 sec (type SRCH) for 16 DLCround-PT-13b-CTLFireability-04 sec rmula_rewrite.k:711 (type SRCH) for DLCround-PT-13b-CTLFireability-04 : unknown 0.000000 1 (type EXCL) for DLCround-PT-13b-CTLFireability-04 : true 3 2 0.000000 1 (type FNDP) for DLCround-PT-13b-CTLFireability-04 (obsolete) (type EQUN) for DLCround-PT-13b-CTLFireability-04 (obsolete) (type FNDP) for DLCround-PT-13b-CTLFireability-04 : true 1 1 0.000000 0 (type EQUN) for DLCround-PT-13b-CTLFireability-04 : unknown VALUE PRODUCED BY EF true state space IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 2 16 in 2.000000 secs. rmula_rewrite.k:813 rmula_rewrite.k:813 rmula_rewrite.k:811 rmula_rewrite.k:810 rmula_rewrite.k:806 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:809 rmula_rewrite.k:806 (type EXCL) for 22 DLCround-PT-13b-CTLFireability-06 rmula_rewrite.k:811 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:813 (type EXCL) for DLCround-PT-13b-CTLFireability-06 : false 16 16 0.000000 1 (type EXCL) for 34 DLCround-PT-13b-CTLFireability-10 rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:806 rmula_rewrite.k:814 rmula_rewrite.k:808 rmula_rewrite.k:814 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 1 0 0 0 0 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-13b-CTLFireability-10 20766 m, 4153 m/sec, 67415 t fired, . Pages in use: 2 16 in 6.000000 secs. VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 DISJ 0 1 0 0 2 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 1 0 0 0 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 0 0 0 3 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCround-PT-13b-CTLFireability-10 83730 m, 12592 m/sec, 295600 t fired, . Pages in use: 2 16 in 2.000000 secs. rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:809 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:809 rmula_rewrite.k:806 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:811 rmula_rewrite.k:807 rmula_rewrite.k:714 rmula_rewrite.k:812 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:812 rmula_rewrite.k:806 rmula_rewrite.k:714 rmula_rewrite.k:814 rmula_rewrite.k:809 rmula_rewrite.k:809 rmula_rewrite.k:815 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:810 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:809 rmula_rewrite.k:815 rmula_rewrite.k:808 rmula_rewrite.k:813 rmula_rewrite.k:806 rmula_rewrite.k:813 rmula_rewrite.k:807 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:807 rmula_rewrite.k:814 rmula_rewrite.k:813 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:809 rmula_rewrite.k:813 rmula_rewrite.k:810 rmula_rewrite.k:815 rmula_rewrite.k:810 rmula_rewrite.k:813 rmula_rewrite.k:814 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:807 rmula_rewrite.k:808 rmula_rewrite.k:812 rmula_rewrite.k:814 rmula_rewrite.k:806 rmula_rewrite.k:807 rmula_rewrite.k:811 rmula_rewrite.k:806 rmula_rewrite.k:808 rmula_rewrite.k:806 rmula_rewrite.k:812 rmula_rewrite.k:811 rmula_rewrite.k:808 rmula_rewrite.k:809 rmula_rewrite.k:812 rmula_rewrite.k:808 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-13b-CTLFireability-10 253710 m, 33996 m/sec, 931492 t fired, . Pages in use: 2 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-13b-CTLFireability-10 519155 m, 53089 m/sec, 1986233 t fired, . Pages in use: 4 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-13b-CTLFireability-10 776889 m, 51546 m/sec, 3073949 t fired, . Pages in use: 5 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-13b-CTLFireability-10 1094672 m, 63556 m/sec, 4262301 t fired, . Pages in use: 7 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-13b-CTLFireability-10 1403669 m, 61799 m/sec, 5456933 t fired, . Pages in use: 9 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCround-PT-13b-CTLFireability-10 1707026 m, 60671 m/sec, 6643514 t fired, . Pages in use: 11 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCround-PT-13b-CTLFireability-10 1985881 m, 55771 m/sec, 7863299 t fired, . Pages in use: 12 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCround-PT-13b-CTLFireability-10 2266980 m, 56219 m/sec, 9060724 t fired, . Pages in use: 14 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCround-PT-13b-CTLFireability-10 2541264 m, 54856 m/sec, 10253684 t fired, . Pages in use: 15 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 DLCround-PT-13b-CTLFireability-10 2807084 m, 53164 m/sec, 11458478 t fired, . Pages in use: 17 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCround-PT-13b-CTLFireability-10 3084014 m, 55386 m/sec, 12652601 t fired, . Pages in use: 18 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCround-PT-13b-CTLFireability-10 3343319 m, 51861 m/sec, 13859838 t fired, . Pages in use: 20 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 DLCround-PT-13b-CTLFireability-10 3600894 m, 51515 m/sec, 15064980 t fired, . Pages in use: 21 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 DLCround-PT-13b-CTLFireability-10 3856992 m, 51219 m/sec, 16269974 t fired, . Pages in use: 22 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCround-PT-13b-CTLFireability-10 4104650 m, 49531 m/sec, 17469627 t fired, . Pages in use: 24 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 DLCround-PT-13b-CTLFireability-10 4347326 m, 48535 m/sec, 18682441 t fired, . Pages in use: 25 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCround-PT-13b-CTLFireability-10 4604248 m, 51384 m/sec, 19884638 t fired, . Pages in use: 26 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 DLCround-PT-13b-CTLFireability-10 4800528 m, 39256 m/sec, 20859975 t fired, . Pages in use: 27 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCround-PT-13b-CTLFireability-10 4925069 m, 24908 m/sec, 21462957 t fired, . Pages in use: 28 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 DLCround-PT-13b-CTLFireability-10 5124802 m, 39946 m/sec, 22427659 t fired, . Pages in use: 29 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 DLCround-PT-13b-CTLFireability-10 5292471 m, 33533 m/sec, 23200411 t fired, . Pages in use: 30 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCround-PT-13b-CTLFireability-10 5407605 m, 23026 m/sec, 23742611 t fired, . Pages in use: 31 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCround-PT-13b-CTLFireability-10 5533987 m, 25276 m/sec, 24293905 t fired, . Pages in use: 31 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 DLCround-PT-13b-CTLFireability-10 5683857 m, 29974 m/sec, 24976201 t fired, . Pages in use: 32 16 (type EXCL) for DLCround-PT-13b-CTLFireability-10 (memory limit exceeded) VALUE PRODUCED BY EF true state space CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 16 (type EXCL) for 57 DLCround-PT-13b-CTLFireability-15 (type EXCL) for DLCround-PT-13b-CTLFireability-15 : true 1503 1504 0.000000 1 (type EXCL) for 54 DLCround-PT-13b-CTLFireability-14 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-13b-CTLFireability-14 140862 m, 28172 m/sec, 318702 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-13b-CTLFireability-14 296563 m, 31140 m/sec, 672833 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCround-PT-13b-CTLFireability-14 451378 m, 30963 m/sec, 1024636 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-13b-CTLFireability-14 601277 m, 29979 m/sec, 1367861 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCround-PT-13b-CTLFireability-14 751530 m, 30050 m/sec, 1709752 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-13b-CTLFireability-14 900896 m, 29873 m/sec, 2051662 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCround-PT-13b-CTLFireability-14 1050768 m, 29974 m/sec, 2393715 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCround-PT-13b-CTLFireability-14 1204169 m, 30680 m/sec, 2745220 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCround-PT-13b-CTLFireability-14 1364912 m, 32148 m/sec, 3111494 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCround-PT-13b-CTLFireability-14 1524998 m, 32017 m/sec, 3475131 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 DLCround-PT-13b-CTLFireability-14 1681581 m, 31316 m/sec, 3829796 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 DLCround-PT-13b-CTLFireability-14 1839018 m, 31487 m/sec, 4188160 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCround-PT-13b-CTLFireability-14 1998469 m, 31890 m/sec, 4553350 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCround-PT-13b-CTLFireability-14 2154242 m, 31154 m/sec, 4911194 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 DLCround-PT-13b-CTLFireability-14 2305786 m, 30308 m/sec, 5259711 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 DLCround-PT-13b-CTLFireability-14 2453270 m, 29496 m/sec, 5596119 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 DLCround-PT-13b-CTLFireability-14 2600773 m, 29500 m/sec, 5931999 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCround-PT-13b-CTLFireability-14 2755838 m, 31013 m/sec, 6285084 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 DLCround-PT-13b-CTLFireability-14 2913858 m, 31604 m/sec, 6644041 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCround-PT-13b-CTLFireability-14 3069484 m, 31125 m/sec, 7001409 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 DLCround-PT-13b-CTLFireability-14 3224089 m, 30921 m/sec, 7356300 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCround-PT-13b-CTLFireability-14 3377807 m, 30743 m/sec, 7708404 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 DLCround-PT-13b-CTLFireability-14 3531210 m, 30680 m/sec, 8059960 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 DLCround-PT-13b-CTLFireability-14 3684926 m, 30743 m/sec, 8413764 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCround-PT-13b-CTLFireability-14 3839373 m, 30889 m/sec, 8768298 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 DLCround-PT-13b-CTLFireability-14 3993883 m, 30902 m/sec, 9123683 t fired, . Pages in use: 32 16 (type EXCL) for DLCround-PT-13b-CTLFireability-14 (memory limit exceeded) VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 16 (type EXCL) for 48 DLCround-PT-13b-CTLFireability-12 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCround-PT-13b-CTLFireability-12 166251 m, 33250 m/sec, 360218 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCround-PT-13b-CTLFireability-12 346671 m, 36084 m/sec, 753243 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-13b-CTLFireability-12 522546 m, 35175 m/sec, 1138437 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCround-PT-13b-CTLFireability-12 698764 m, 35243 m/sec, 1523096 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-13b-CTLFireability-12 862725 m, 32792 m/sec, 1881966 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCround-PT-13b-CTLFireability-12 1040965 m, 35648 m/sec, 2272597 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCround-PT-13b-CTLFireability-12 1217438 m, 35294 m/sec, 2662632 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCround-PT-13b-CTLFireability-12 1392754 m, 35063 m/sec, 3050756 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 DLCround-PT-13b-CTLFireability-12 1568693 m, 35187 m/sec, 3438124 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCround-PT-13b-CTLFireability-12 1747860 m, 35833 m/sec, 3832828 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCround-PT-13b-CTLFireability-12 1925803 m, 35588 m/sec, 4224928 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 DLCround-PT-13b-CTLFireability-12 2102148 m, 35269 m/sec, 4617000 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 DLCround-PT-13b-CTLFireability-12 2277800 m, 35130 m/sec, 5006167 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCround-PT-13b-CTLFireability-12 2460375 m, 36515 m/sec, 5417005 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCround-PT-13b-CTLFireability-12 2635779 m, 35080 m/sec, 5803717 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCround-PT-13b-CTLFireability-12 2811052 m, 35054 m/sec, 6189970 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 DLCround-PT-13b-CTLFireability-12 2985716 m, 34932 m/sec, 6570138 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCround-PT-13b-CTLFireability-12 3158483 m, 34553 m/sec, 6952657 t fired, . Pages in use: 32 16 (type EXCL) for DLCround-PT-13b-CTLFireability-12 (memory limit exceeded) VALUE PRODUCED BY EF true state space CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 3 0 0 3 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 16 (type EXCL) for 37 DLCround-PT-13b-CTLFireability-11 (type EXCL) for DLCround-PT-13b-CTLFireability-11 : true 197 196 0.000000 1 (type EXCL) for 28 DLCround-PT-13b-CTLFireability-08 VALUE PRODUCED BY EF true state space CTL false CTL model checker DISJ true state space /EXEF CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCround-PT-13b-CTLFireability-08 264081 m, 52816 m/sec, 310696 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker DISJ true state space /EXEF CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCround-PT-13b-CTLFireability-08 544085 m, 56000 m/sec, 642666 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker DISJ true state space /EXEF CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCround-PT-13b-CTLFireability-08 825436 m, 56270 m/sec, 976127 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker DISJ true state space /EXEF CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCround-PT-13b-CTLFireability-08 1071955 m, 49303 m/sec, 1270174 t fired, . Pages in use: 32 16 VALUE PRODUCED BY EF true state space CTL false CTL model checker DISJ true state space /EXEF CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCround-PT-13b-CTLFireability-08 1341179 m, 53844 m/sec, 1597145 t fired, . Pages in use: 32 16 n//../BenchKit_head.sh: line 63: 377 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-13b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-13b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477300786"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-13b.tgz
mv DLCround-PT-13b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;