About the Execution of LoLA for DLCround-PT-08a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4012.380 | 115473.00 | 116779.00 | 197.80 | FFFFFFFFFFF?FTTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477200700.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-08a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477200700
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 948K
-rw-r--r-- 1 mcc users 6.4K Feb 25 19:02 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 19:02 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 18:44 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 25 18:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:53 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:53 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:53 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Feb 25 15:53 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 19:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Feb 25 19:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 19:27 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 69K Feb 25 19:27 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:53 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:53 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 479K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-08a-LTLFireability-00
FORMULA_NAME DLCround-PT-08a-LTLFireability-01
FORMULA_NAME DLCround-PT-08a-LTLFireability-02
FORMULA_NAME DLCround-PT-08a-LTLFireability-03
FORMULA_NAME DLCround-PT-08a-LTLFireability-04
FORMULA_NAME DLCround-PT-08a-LTLFireability-05
FORMULA_NAME DLCround-PT-08a-LTLFireability-06
FORMULA_NAME DLCround-PT-08a-LTLFireability-07
FORMULA_NAME DLCround-PT-08a-LTLFireability-08
FORMULA_NAME DLCround-PT-08a-LTLFireability-09
FORMULA_NAME DLCround-PT-08a-LTLFireability-10
FORMULA_NAME DLCround-PT-08a-LTLFireability-11
FORMULA_NAME DLCround-PT-08a-LTLFireability-12
FORMULA_NAME DLCround-PT-08a-LTLFireability-13
FORMULA_NAME DLCround-PT-08a-LTLFireability-14
FORMULA_NAME DLCround-PT-08a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678317912751
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-08a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-08a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA DLCround-PT-08a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-08a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678318028224
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:496
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SKEL/FNDP) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SKEL/EQUN) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/SRCH) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 60 (type SKEL/SRCH) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 58 (type SKEL/FNDP) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: CANCELED task # 61 (type SRCH) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: FINISHED task # 61 (type SKEL/SRCH) for DLCround-PT-08a-LTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/LTLFireability-59.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 64 (type SKEL/FNDP) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SKEL/EQUN) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type SKEL/SRCH) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/SRCH) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 67 (type SKEL/SRCH) for DLCround-PT-08a-LTLFireability-01
lola: result : unknown
lola: time used : 1.000000
lola: memory pages used : 1
lola: FINISHED task # 64 (type SKEL/FNDP) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 65 (type EQUN) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: CANCELED task # 66 (type SRCH) for DLCround-PT-08a-LTLFireability-01 (obsolete)
sara: try reading problem file /home/mcc/execution/LTLFireability-65.sara.
lola: FINISHED task # 66 (type SKEL/SRCH) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 1.000000
lola: memory pages used : 1
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 59 (type SKEL/EQUN) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: FINISHED task # 65 (type SKEL/EQUN) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 28 DLCround-PT-08a-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: FINISHED task # 68 (type SKEL/SRCH) for DLCround-PT-08a-LTLFireability-08
lola: result : false
lola: markings : 15
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 72 (type EXCL) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 70 (type FNDP) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 71 (type EQUN) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 3 DLCround-PT-08a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type EXCL) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 70 (type FNDP) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: CANCELED task # 71 (type EQUN) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: CANCELED task # 73 (type SRCH) for DLCround-PT-08a-LTLFireability-01 (obsolete)
lola: FINISHED task # 70 (type FNDP) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/LTLFireability-71.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 71 (type EQUN) for DLCround-PT-08a-LTLFireability-01
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 17 (type EXCL) for 16 DLCround-PT-08a-LTLFireability-04
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for DLCround-PT-08a-LTLFireability-04
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 42 (type EXCL) for 41 DLCround-PT-08a-LTLFireability-11
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 76 (type FNDP) for 13 DLCround-PT-08a-LTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 13 DLCround-PT-08a-LTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 13 DLCround-PT-08a-LTLFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 79 (type SRCH) for DLCround-PT-08a-LTLFireability-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 76 (type FNDP) for DLCround-PT-08a-LTLFireability-03
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for DLCround-PT-08a-LTLFireability-03 (obsolete)
lola: FINISHED task # 77 (type EQUN) for DLCround-PT-08a-LTLFireability-03
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 4/257 2/32 DLCround-PT-08a-LTLFireability-11 221034 m, 44206 m/sec, 7975782 t fired, .
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 9/257 3/32 DLCround-PT-08a-LTLFireability-11 451029 m, 45999 m/sec, 16334599 t fired, .
Time elapsed: 10 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 14/257 5/32 DLCround-PT-08a-LTLFireability-11 677031 m, 45200 m/sec, 24496220 t fired, .
Time elapsed: 15 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 19/257 6/32 DLCround-PT-08a-LTLFireability-11 897581 m, 44110 m/sec, 32557144 t fired, .
Time elapsed: 20 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 24/257 8/32 DLCround-PT-08a-LTLFireability-11 1118621 m, 44208 m/sec, 40867847 t fired, .
Time elapsed: 25 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 29/257 9/32 DLCround-PT-08a-LTLFireability-11 1338091 m, 43894 m/sec, 49174609 t fired, .
Time elapsed: 30 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 34/257 11/32 DLCround-PT-08a-LTLFireability-11 1553400 m, 43061 m/sec, 57387318 t fired, .
Time elapsed: 35 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 39/257 12/32 DLCround-PT-08a-LTLFireability-11 1765880 m, 42496 m/sec, 65477594 t fired, .
Time elapsed: 40 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 44/257 13/32 DLCround-PT-08a-LTLFireability-11 1971937 m, 41211 m/sec, 73415774 t fired, .
Time elapsed: 45 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 49/257 15/32 DLCround-PT-08a-LTLFireability-11 2184079 m, 42428 m/sec, 81557289 t fired, .
Time elapsed: 50 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 54/257 16/32 DLCround-PT-08a-LTLFireability-11 2403133 m, 43810 m/sec, 89738193 t fired, .
Time elapsed: 55 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 59/257 17/32 DLCround-PT-08a-LTLFireability-11 2615512 m, 42475 m/sec, 97712683 t fired, .
Time elapsed: 60 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 64/257 19/32 DLCround-PT-08a-LTLFireability-11 2824081 m, 41713 m/sec, 105553303 t fired, .
Time elapsed: 65 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 69/257 20/32 DLCround-PT-08a-LTLFireability-11 3027271 m, 40638 m/sec, 113421928 t fired, .
Time elapsed: 70 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 74/257 22/32 DLCround-PT-08a-LTLFireability-11 3239779 m, 42501 m/sec, 121449842 t fired, .
Time elapsed: 75 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 79/257 23/32 DLCround-PT-08a-LTLFireability-11 3462967 m, 44637 m/sec, 129970361 t fired, .
Time elapsed: 80 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 84/257 24/32 DLCround-PT-08a-LTLFireability-11 3683346 m, 44075 m/sec, 138358199 t fired, .
Time elapsed: 85 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 90/257 26/32 DLCround-PT-08a-LTLFireability-11 3896311 m, 42593 m/sec, 146536319 t fired, .
Time elapsed: 91 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 95/257 27/32 DLCround-PT-08a-LTLFireability-11 4106394 m, 42016 m/sec, 154676944 t fired, .
Time elapsed: 96 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 100/257 29/32 DLCround-PT-08a-LTLFireability-11 4319458 m, 42612 m/sec, 162873844 t fired, .
Time elapsed: 101 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 105/257 30/32 DLCround-PT-08a-LTLFireability-11 4540063 m, 44121 m/sec, 171069851 t fired, .
Time elapsed: 106 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 LTL EXCL 110/257 31/32 DLCround-PT-08a-LTLFireability-11 4757742 m, 43535 m/sec, 179323071 t fired, .
Time elapsed: 111 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for DLCround-PT-08a-LTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-08a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-06: AU 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-08: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-08a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
DLCround-PT-08a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-14: F 0 1 0 0 1 0 0 0
DLCround-PT-08a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 48 (type EXCL) for 47 DLCround-PT-08a-LTLFireability-13
lola: time limit : 268 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for DLCround-PT-08a-LTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 28 DLCround-PT-08a-LTLFireability-08
lola: time limit : 290 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for DLCround-PT-08a-LTLFireability-08
lola: result : false
lola: markings : 17
lola: fired transitions : 80
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-08a-LTLFireability-05
lola: time limit : 348 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for DLCround-PT-08a-LTLFireability-05
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 DLCround-PT-08a-LTLFireability-02
lola: time limit : 387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for DLCround-PT-08a-LTLFireability-02
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-08a-LTLFireability-00
lola: time limit : 435 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-08a-LTLFireability-00
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 74 (type EXCL) for 50 DLCround-PT-08a-LTLFireability-14
lola: time limit : 497 sec
lola: memory limit: 32 pages
lola: FINISHED task # 74 (type EXCL) for DLCround-PT-08a-LTLFireability-14
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 80 (type EXCL) for 22 DLCround-PT-08a-LTLFireability-06
lola: time limit : 580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 80 (type EXCL) for DLCround-PT-08a-LTLFireability-06
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-08a-LTLFireability-07
lola: time limit : 696 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for DLCround-PT-08a-LTLFireability-07
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 DLCround-PT-08a-LTLFireability-09
lola: time limit : 871 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for DLCround-PT-08a-LTLFireability-09
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 DLCround-PT-08a-LTLFireability-12
lola: time limit : 1161 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for DLCround-PT-08a-LTLFireability-12
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 DLCround-PT-08a-LTLFireability-15
lola: time limit : 1742 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for DLCround-PT-08a-LTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 DLCround-PT-08a-LTLFireability-10
lola: time limit : 3484 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DLCround-PT-08a-LTLFireability-10
lola: result : false
lola: markings : 14
lola: fired transitions : 174
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-08a-LTLFireability-00: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-01: CONJ false state space
DLCround-PT-08a-LTLFireability-02: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-03: AG false findpath
DLCround-PT-08a-LTLFireability-04: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-05: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-06: AU false state space /ER
DLCround-PT-08a-LTLFireability-07: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-08: CONJ false LTL model checker
DLCround-PT-08a-LTLFireability-09: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-10: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-11: LTL unknown AGGR
DLCround-PT-08a-LTLFireability-12: LTL false LTL model checker
DLCround-PT-08a-LTLFireability-13: LTL true LTL model checker
DLCround-PT-08a-LTLFireability-14: F true state space / EG
DLCround-PT-08a-LTLFireability-15: LTL false LTL model checker
Time elapsed: 116 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-08a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-08a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477200700"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-08a.tgz
mv DLCround-PT-08a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;