About the Execution of LoLA for DLCround-PT-06a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3369.367 | 98731.00 | 97049.00 | 480.90 | FFFT?TFFFFFFFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477200668.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-06a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477200668
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 796K
-rw-r--r-- 1 mcc users 6.8K Feb 25 18:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 18:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 18:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 18:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 19:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 127K Feb 25 19:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 25 18:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 73K Feb 25 18:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 325K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-06a-LTLFireability-00
FORMULA_NAME DLCround-PT-06a-LTLFireability-01
FORMULA_NAME DLCround-PT-06a-LTLFireability-02
FORMULA_NAME DLCround-PT-06a-LTLFireability-03
FORMULA_NAME DLCround-PT-06a-LTLFireability-04
FORMULA_NAME DLCround-PT-06a-LTLFireability-05
FORMULA_NAME DLCround-PT-06a-LTLFireability-06
FORMULA_NAME DLCround-PT-06a-LTLFireability-07
FORMULA_NAME DLCround-PT-06a-LTLFireability-08
FORMULA_NAME DLCround-PT-06a-LTLFireability-09
FORMULA_NAME DLCround-PT-06a-LTLFireability-10
FORMULA_NAME DLCround-PT-06a-LTLFireability-11
FORMULA_NAME DLCround-PT-06a-LTLFireability-12
FORMULA_NAME DLCround-PT-06a-LTLFireability-13
FORMULA_NAME DLCround-PT-06a-LTLFireability-14
FORMULA_NAME DLCround-PT-06a-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678314992847
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-06a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-06a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability
FORMULA DLCround-PT-06a-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-06a-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678315091578
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:424
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 72 (type SKEL/SRCH) for 6 DLCround-PT-06a-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 73 (type SKEL/SRCH) for 3 DLCround-PT-06a-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type SKEL/SRCH) for DLCround-PT-06a-LTLFireability-01
lola: result : false
lola: markings : 15
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: FINISHED task # 72 (type SKEL/SRCH) for DLCround-PT-06a-LTLFireability-02
lola: result : false
lola: markings : 3189
lola: fired transitions : 33961
lola: time used : 1.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 17 (type EXCL) for 16 DLCround-PT-06a-LTLFireability-04
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 74 (type SKEL/SRCH) for 65 DLCround-PT-06a-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 74 (type SKEL/SRCH) for DLCround-PT-06a-LTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-13: CONJ 0 3 0 0 3 0 0 0
DLCround-PT-06a-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 4/163 3/32 DLCround-PT-06a-LTLFireability-04 358876 m, 71775 m/sec, 8964743 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-13: CONJ 0 3 0 0 3 0 0 0
DLCround-PT-06a-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 9/163 5/32 DLCround-PT-06a-LTLFireability-04 702049 m, 68634 m/sec, 18322753 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-13: CONJ 0 3 0 0 3 0 0 0
DLCround-PT-06a-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 14/163 7/32 DLCround-PT-06a-LTLFireability-04 1026514 m, 64893 m/sec, 27284568 t fired, .
Time elapsed: 15 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-13: CONJ 0 3 0 0 3 0 0 0
DLCround-PT-06a-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 19/163 9/32 DLCround-PT-06a-LTLFireability-04 1335752 m, 61847 m/sec, 36061186 t fired, .
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DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
DLCround-PT-06a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-13: CONJ 0 3 0 0 3 0 0 0
DLCround-PT-06a-LTLFireability-14: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-06a-LTLFireability-15: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 LTL EXCL 24/163 11/32 DLCround-PT-06a-LTLFireability-04 1664582 m, 65766 m/sec, 44846791 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 2 0 0 2 0 0 0
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DLCround-PT-06a-LTLFireability-05: LTL true LTL model checker
DLCround-PT-06a-LTLFireability-06: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-07: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-14: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 0 1 0 3 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 LTL EXCL 10/391 4/32 DLCround-PT-06a-LTLFireability-02 603895 m, 56792 m/sec, 19700022 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-06a-LTLFireability-05: LTL true LTL model checker
DLCround-PT-06a-LTLFireability-06: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-07: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-14: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-15: CONJ false LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-06a-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-02: CONJ 0 0 1 0 3 0 0 0
DLCround-PT-06a-LTLFireability-03: F 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
DLCround-PT-06a-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
DLCround-PT-06a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
9 LTL EXCL 15/391 6/32 DLCround-PT-06a-LTLFireability-02 877680 m, 54757 m/sec, 29401230 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 9 (type EXCL) for DLCround-PT-06a-LTLFireability-02
lola: result : false
lola: markings : 1050660
lola: fired transitions : 36078266
lola: time used : 18.000000
lola: memory pages used : 7
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-06a-LTLFireability-01
lola: time limit : 437 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DLCround-PT-06a-LTLFireability-01
lola: result : false
lola: markings : 12
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-06a-LTLFireability-00
lola: time limit : 500 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-06a-LTLFireability-00
lola: result : false
lola: markings : 17
lola: fired transitions : 75
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 75 (type EXCL) for 13 DLCround-PT-06a-LTLFireability-03
lola: time limit : 583 sec
lola: memory limit: 32 pages
lola: FINISHED task # 75 (type EXCL) for DLCround-PT-06a-LTLFireability-03
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 DLCround-PT-06a-LTLFireability-11
lola: time limit : 700 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for DLCround-PT-06a-LTLFireability-11
lola: result : false
lola: markings : 5
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 DLCround-PT-06a-LTLFireability-10
lola: time limit : 875 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DLCround-PT-06a-LTLFireability-10
lola: result : false
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 DLCround-PT-06a-LTLFireability-09
lola: time limit : 1167 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for DLCround-PT-06a-LTLFireability-09
lola: result : false
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 DLCround-PT-06a-LTLFireability-08
lola: time limit : 1750 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for DLCround-PT-06a-LTLFireability-08
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 DLCround-PT-06a-LTLFireability-12
lola: time limit : 3501 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for DLCround-PT-06a-LTLFireability-12
lola: result : false
lola: markings : 3
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-06a-LTLFireability-00: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-01: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-02: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-03: F true state space / EG
DLCround-PT-06a-LTLFireability-04: LTL unknown AGGR
DLCround-PT-06a-LTLFireability-05: LTL true LTL model checker
DLCround-PT-06a-LTLFireability-06: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-07: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-08: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-09: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-10: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-11: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-12: LTL false LTL model checker
DLCround-PT-06a-LTLFireability-13: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-14: CONJ false LTL model checker
DLCround-PT-06a-LTLFireability-15: CONJ false LTL model checker
Time elapsed: 99 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-06a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-06a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477200668"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-06a.tgz
mv DLCround-PT-06a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;