About the Execution of LoLA for DLCround-PT-05b
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 7271.500 | 383950.00 | 360696.00 | 1033.20 | TF??F?T?T?F??T?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477200658.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-05b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477200658
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 7.6K Feb 25 18:23 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 18:23 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 18:23 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 18:23 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 18:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 109K Feb 25 18:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 25 18:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 25 18:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 674K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05b-CTLFireability-00
FORMULA_NAME DLCround-PT-05b-CTLFireability-01
FORMULA_NAME DLCround-PT-05b-CTLFireability-02
FORMULA_NAME DLCround-PT-05b-CTLFireability-03
FORMULA_NAME DLCround-PT-05b-CTLFireability-04
FORMULA_NAME DLCround-PT-05b-CTLFireability-05
FORMULA_NAME DLCround-PT-05b-CTLFireability-06
FORMULA_NAME DLCround-PT-05b-CTLFireability-07
FORMULA_NAME DLCround-PT-05b-CTLFireability-08
FORMULA_NAME DLCround-PT-05b-CTLFireability-09
FORMULA_NAME DLCround-PT-05b-CTLFireability-10
FORMULA_NAME DLCround-PT-05b-CTLFireability-11
FORMULA_NAME DLCround-PT-05b-CTLFireability-12
FORMULA_NAME DLCround-PT-05b-CTLFireability-13
FORMULA_NAME DLCround-PT-05b-CTLFireability-14
FORMULA_NAME DLCround-PT-05b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678313611866
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-05b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-05b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCround-PT-05b-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05b-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678313995816
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 60 (type EXCL) for 12 DLCround-PT-05b-CTLFireability-04
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for DLCround-PT-05b-CTLFireability-04
lola: result : true
lola: markings : 82
lola: fired transitions : 82
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 1 (type EXCL) for 0 DLCround-PT-05b-CTLFireability-00
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCround-PT-05b-CTLFireability-00
lola: result : true
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 23 (type EXCL) for 22 DLCround-PT-05b-CTLFireability-06
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 23 (type EXCL) for DLCround-PT-05b-CTLFireability-06
lola: result : true
lola: markings : 78
lola: fired transitions : 78
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-05b-CTLFireability-03
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/239 2/32 DLCround-PT-05b-CTLFireability-03 411563 m, 82312 m/sec, 1463648 t fired, .
Time elapsed: 9 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 9/239 6/32 DLCround-PT-05b-CTLFireability-03 1334558 m, 184599 m/sec, 4866954 t fired, .
Time elapsed: 14 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 14/239 10/32 DLCround-PT-05b-CTLFireability-03 2196588 m, 172406 m/sec, 8122673 t fired, .
Time elapsed: 19 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 19/239 14/32 DLCround-PT-05b-CTLFireability-03 3099414 m, 180565 m/sec, 11388476 t fired, .
Time elapsed: 24 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 24/239 17/32 DLCround-PT-05b-CTLFireability-03 3942086 m, 168534 m/sec, 14536029 t fired, .
Time elapsed: 29 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 29/239 21/32 DLCround-PT-05b-CTLFireability-03 4759798 m, 163542 m/sec, 17642086 t fired, .
Time elapsed: 34 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 34/239 24/32 DLCround-PT-05b-CTLFireability-03 5558704 m, 159781 m/sec, 20714975 t fired, .
Time elapsed: 39 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 39/239 28/32 DLCround-PT-05b-CTLFireability-03 6340548 m, 156368 m/sec, 23752165 t fired, .
Time elapsed: 44 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 44/239 31/32 DLCround-PT-05b-CTLFireability-03 7111474 m, 154185 m/sec, 26766254 t fired, .
Time elapsed: 49 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for DLCround-PT-05b-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 54 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 55 (type EXCL) for 54 DLCround-PT-05b-CTLFireability-14
lola: time limit : 253 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 5/253 6/32 DLCround-PT-05b-CTLFireability-14 691079 m, 138215 m/sec, 801532 t fired, .
Time elapsed: 59 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 10/253 10/32 DLCround-PT-05b-CTLFireability-14 1359234 m, 133631 m/sec, 1581299 t fired, .
Time elapsed: 64 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 15/253 15/32 DLCround-PT-05b-CTLFireability-14 2035575 m, 135268 m/sec, 2365799 t fired, .
Time elapsed: 69 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 20/253 19/32 DLCround-PT-05b-CTLFireability-14 2684753 m, 129835 m/sec, 3120747 t fired, .
Time elapsed: 74 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 25/253 24/32 DLCround-PT-05b-CTLFireability-14 3328751 m, 128799 m/sec, 3869388 t fired, .
Time elapsed: 79 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 30/253 28/32 DLCround-PT-05b-CTLFireability-14 3961629 m, 126575 m/sec, 4610919 t fired, .
Time elapsed: 84 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 35/253 32/32 DLCround-PT-05b-CTLFireability-14 4621017 m, 131877 m/sec, 5378453 t fired, .
Time elapsed: 89 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 55 (type EXCL) for DLCround-PT-05b-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 94 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 51 DLCround-PT-05b-CTLFireability-13
lola: time limit : 269 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for DLCround-PT-05b-CTLFireability-13
lola: result : true
lola: markings : 72
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 DLCround-PT-05b-CTLFireability-12
lola: time limit : 292 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/292 6/32 DLCround-PT-05b-CTLFireability-12 697038 m, 139407 m/sec, 806244 t fired, .
Time elapsed: 99 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 10/292 10/32 DLCround-PT-05b-CTLFireability-12 1362208 m, 133034 m/sec, 1577664 t fired, .
Time elapsed: 104 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 15/292 15/32 DLCround-PT-05b-CTLFireability-12 2010587 m, 129675 m/sec, 2331316 t fired, .
Time elapsed: 109 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 20/292 19/32 DLCround-PT-05b-CTLFireability-12 2651044 m, 128091 m/sec, 3076612 t fired, .
Time elapsed: 114 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 25/292 23/32 DLCround-PT-05b-CTLFireability-12 3267902 m, 123371 m/sec, 3798922 t fired, .
Time elapsed: 119 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 30/292 27/32 DLCround-PT-05b-CTLFireability-12 3892860 m, 124991 m/sec, 4526124 t fired, .
Time elapsed: 124 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 35/292 31/32 DLCround-PT-05b-CTLFireability-12 4531099 m, 127647 m/sec, 5273910 t fired, .
Time elapsed: 129 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 49 (type EXCL) for DLCround-PT-05b-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 134 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 41 DLCround-PT-05b-CTLFireability-11
lola: time limit : 315 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 5/315 6/32 DLCround-PT-05b-CTLFireability-11 725575 m, 145115 m/sec, 839169 t fired, .
Time elapsed: 139 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 10/315 10/32 DLCround-PT-05b-CTLFireability-11 1396473 m, 134179 m/sec, 1624339 t fired, .
Time elapsed: 144 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 15/315 15/32 DLCround-PT-05b-CTLFireability-11 2087869 m, 138279 m/sec, 2427895 t fired, .
Time elapsed: 149 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 20/315 19/32 DLCround-PT-05b-CTLFireability-11 2767270 m, 135880 m/sec, 3217446 t fired, .
Time elapsed: 154 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 25/315 24/32 DLCround-PT-05b-CTLFireability-11 3456735 m, 137893 m/sec, 4018180 t fired, .
Time elapsed: 159 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 30/315 30/32 DLCround-PT-05b-CTLFireability-11 4163259 m, 141304 m/sec, 4837530 t fired, .
Time elapsed: 164 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 46 (type EXCL) for DLCround-PT-05b-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 169 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 44 (type EXCL) for 41 DLCround-PT-05b-CTLFireability-11
lola: time limit : 343 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/343 5/32 DLCround-PT-05b-CTLFireability-11 504116 m, 100823 m/sec, 630634 t fired, .
Time elapsed: 174 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/343 9/32 DLCround-PT-05b-CTLFireability-11 992003 m, 97577 m/sec, 1216766 t fired, .
Time elapsed: 179 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/343 14/32 DLCround-PT-05b-CTLFireability-11 1480562 m, 97711 m/sec, 1793597 t fired, .
Time elapsed: 184 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/343 18/32 DLCround-PT-05b-CTLFireability-11 1990708 m, 102029 m/sec, 2381671 t fired, .
Time elapsed: 189 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/343 22/32 DLCround-PT-05b-CTLFireability-11 2485386 m, 98935 m/sec, 2974793 t fired, .
Time elapsed: 194 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/343 26/32 DLCround-PT-05b-CTLFireability-11 2978387 m, 98600 m/sec, 3565837 t fired, .
Time elapsed: 199 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 35/343 29/32 DLCround-PT-05b-CTLFireability-11 3463909 m, 97104 m/sec, 4156734 t fired, .
Time elapsed: 204 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 44 (type EXCL) for DLCround-PT-05b-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-10: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 209 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 34 DLCround-PT-05b-CTLFireability-10
lola: time limit : 376 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DLCround-PT-05b-CTLFireability-10
lola: result : false
lola: markings : 292
lola: fired transitions : 440
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 34 DLCround-PT-05b-CTLFireability-10
lola: time limit : 423 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for DLCround-PT-05b-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 DLCround-PT-05b-CTLFireability-09
lola: time limit : 484 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/484 4/32 DLCround-PT-05b-CTLFireability-09 358154 m, 71630 m/sec, 921543 t fired, .
Time elapsed: 214 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/484 7/32 DLCround-PT-05b-CTLFireability-09 691735 m, 66716 m/sec, 1976816 t fired, .
Time elapsed: 219 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/484 10/32 DLCround-PT-05b-CTLFireability-09 1023665 m, 66386 m/sec, 3030949 t fired, .
Time elapsed: 224 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/484 13/32 DLCround-PT-05b-CTLFireability-09 1338949 m, 63056 m/sec, 4069751 t fired, .
Time elapsed: 229 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/484 17/32 DLCround-PT-05b-CTLFireability-09 1701571 m, 72524 m/sec, 5107147 t fired, .
Time elapsed: 234 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/484 20/32 DLCround-PT-05b-CTLFireability-09 2126658 m, 85017 m/sec, 6028370 t fired, .
Time elapsed: 239 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/484 23/32 DLCround-PT-05b-CTLFireability-09 2537136 m, 82095 m/sec, 6916907 t fired, .
Time elapsed: 244 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 40/484 26/32 DLCround-PT-05b-CTLFireability-09 2949146 m, 82402 m/sec, 7806771 t fired, .
Time elapsed: 249 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 45/484 29/32 DLCround-PT-05b-CTLFireability-09 3352560 m, 80682 m/sec, 8680898 t fired, .
Time elapsed: 254 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 50/484 32/32 DLCround-PT-05b-CTLFireability-09 3743841 m, 78256 m/sec, 9533597 t fired, .
Time elapsed: 259 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for DLCround-PT-05b-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 264 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 DLCround-PT-05b-CTLFireability-07
lola: time limit : 556 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/556 6/32 DLCround-PT-05b-CTLFireability-07 699449 m, 139889 m/sec, 809037 t fired, .
Time elapsed: 269 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/556 10/32 DLCround-PT-05b-CTLFireability-07 1367652 m, 133640 m/sec, 1583867 t fired, .
Time elapsed: 274 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 15/556 15/32 DLCround-PT-05b-CTLFireability-07 2021185 m, 130706 m/sec, 2343635 t fired, .
Time elapsed: 279 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 20/556 19/32 DLCround-PT-05b-CTLFireability-07 2670212 m, 129805 m/sec, 3098914 t fired, .
Time elapsed: 284 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 25/556 23/32 DLCround-PT-05b-CTLFireability-07 3309623 m, 127882 m/sec, 3847452 t fired, .
Time elapsed: 289 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 30/556 28/32 DLCround-PT-05b-CTLFireability-07 3955643 m, 129204 m/sec, 4599590 t fired, .
Time elapsed: 294 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 35/556 32/32 DLCround-PT-05b-CTLFireability-07 4582573 m, 125386 m/sec, 5333741 t fired, .
Time elapsed: 299 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for DLCround-PT-05b-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 304 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-05b-CTLFireability-05
lola: time limit : 659 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/659 6/32 DLCround-PT-05b-CTLFireability-05 687255 m, 137451 m/sec, 798730 t fired, .
Time elapsed: 309 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/659 11/32 DLCround-PT-05b-CTLFireability-05 1362359 m, 135020 m/sec, 1585812 t fired, .
Time elapsed: 314 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 15/659 15/32 DLCround-PT-05b-CTLFireability-05 2019767 m, 131481 m/sec, 2354664 t fired, .
Time elapsed: 319 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 20/659 20/32 DLCround-PT-05b-CTLFireability-05 2709714 m, 137989 m/sec, 3156407 t fired, .
Time elapsed: 324 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 25/659 24/32 DLCround-PT-05b-CTLFireability-05 3368359 m, 131729 m/sec, 3930085 t fired, .
Time elapsed: 329 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 30/659 28/32 DLCround-PT-05b-CTLFireability-05 4017645 m, 129857 m/sec, 4693919 t fired, .
Time elapsed: 334 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 35/659 32/32 DLCround-PT-05b-CTLFireability-05 4680020 m, 132475 m/sec, 5470881 t fired, .
Time elapsed: 339 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for DLCround-PT-05b-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 344 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-05b-CTLFireability-02
lola: time limit : 814 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/814 6/32 DLCround-PT-05b-CTLFireability-02 722025 m, 144405 m/sec, 835149 t fired, .
Time elapsed: 349 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/814 11/32 DLCround-PT-05b-CTLFireability-02 1387659 m, 133126 m/sec, 1607586 t fired, .
Time elapsed: 354 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/814 15/32 DLCround-PT-05b-CTLFireability-02 2036868 m, 129841 m/sec, 2361822 t fired, .
Time elapsed: 359 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/814 19/32 DLCround-PT-05b-CTLFireability-02 2692260 m, 131078 m/sec, 3124816 t fired, .
Time elapsed: 364 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 25/814 24/32 DLCround-PT-05b-CTLFireability-02 3343686 m, 130285 m/sec, 3887357 t fired, .
Time elapsed: 369 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/814 28/32 DLCround-PT-05b-CTLFireability-02 4001679 m, 131598 m/sec, 4654100 t fired, .
Time elapsed: 374 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 35/814 32/32 DLCround-PT-05b-CTLFireability-02 4643923 m, 128448 m/sec, 5405358 t fired, .
Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for DLCround-PT-05b-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05b-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05b-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-11: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05b-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05b-CTLFireability-15: F 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 DLCround-PT-05b-CTLFireability-01
lola: time limit : 1072 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for DLCround-PT-05b-CTLFireability-01
lola: result : false
lola: markings : 15988
lola: fired transitions : 16354
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 57 DLCround-PT-05b-CTLFireability-15
lola: time limit : 1608 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for DLCround-PT-05b-CTLFireability-15
lola: result : true
lola: markings : 78
lola: fired transitions : 78
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 DLCround-PT-05b-CTLFireability-08
lola: time limit : 3216 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for DLCround-PT-05b-CTLFireability-08
lola: result : true
lola: markings : 3
lola: fired transitions : 29
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05b-CTLFireability-00: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-01: CTL false CTL model checker
DLCround-PT-05b-CTLFireability-02: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-03: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-04: CONJ false state space /EFEG
DLCround-PT-05b-CTLFireability-05: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-06: EG true state space / EG
DLCround-PT-05b-CTLFireability-07: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-08: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-09: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-10: DISJ false DISJ
DLCround-PT-05b-CTLFireability-11: CONJ unknown CONJ
DLCround-PT-05b-CTLFireability-12: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-13: CTL true CTL model checker
DLCround-PT-05b-CTLFireability-14: CTL unknown AGGR
DLCround-PT-05b-CTLFireability-15: F false state space / EG
Time elapsed: 384 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-05b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477200658"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05b.tgz
mv DLCround-PT-05b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;