About the Execution of LoLA for DLCround-PT-05a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16225.680 | 583213.00 | 586348.00 | 9978.20 | ?T???F???F?TTF?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477200650.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCround-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477200650
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 792K
-rw-r--r-- 1 mcc users 8.0K Feb 25 18:35 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 18:35 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 18:28 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 18:28 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 18:46 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 161K Feb 25 18:46 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 18:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 95K Feb 25 18:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 259K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCround-PT-05a-CTLFireability-00
FORMULA_NAME DLCround-PT-05a-CTLFireability-01
FORMULA_NAME DLCround-PT-05a-CTLFireability-02
FORMULA_NAME DLCround-PT-05a-CTLFireability-03
FORMULA_NAME DLCround-PT-05a-CTLFireability-04
FORMULA_NAME DLCround-PT-05a-CTLFireability-05
FORMULA_NAME DLCround-PT-05a-CTLFireability-06
FORMULA_NAME DLCround-PT-05a-CTLFireability-07
FORMULA_NAME DLCround-PT-05a-CTLFireability-08
FORMULA_NAME DLCround-PT-05a-CTLFireability-09
FORMULA_NAME DLCround-PT-05a-CTLFireability-10
FORMULA_NAME DLCround-PT-05a-CTLFireability-11
FORMULA_NAME DLCround-PT-05a-CTLFireability-12
FORMULA_NAME DLCround-PT-05a-CTLFireability-13
FORMULA_NAME DLCround-PT-05a-CTLFireability-14
FORMULA_NAME DLCround-PT-05a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678312874071
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCround-PT-05a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCround-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCround-PT-05a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCround-PT-05a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678313457284
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 77 (type SKEL/FNDP) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SKEL/EQUN) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SKEL/SRCH) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type SKEL/SRCH) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type SKEL/SRCH) for DLCround-PT-05a-CTLFireability-01
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 77 (type FNDP) for DLCround-PT-05a-CTLFireability-01 (obsolete)
lola: CANCELED task # 78 (type EQUN) for DLCround-PT-05a-CTLFireability-01 (obsolete)
lola: CANCELED task # 80 (type SRCH) for DLCround-PT-05a-CTLFireability-01 (obsolete)
lola: FINISHED task # 80 (type SKEL/SRCH) for DLCround-PT-05a-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 77 (type SKEL/FNDP) for DLCround-PT-05a-CTLFireability-01
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-78.sara.
sara: place or transition ordering is non-deterministic
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 78 (type SKEL/EQUN) for DLCround-PT-05a-CTLFireability-01
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 83 (type SKEL/FNDP) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/EQUN) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SKEL/SRCH) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SKEL/SRCH) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 83 (type SKEL/FNDP) for DLCround-PT-05a-CTLFireability-08
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 84 (type EQUN) for DLCround-PT-05a-CTLFireability-08 (obsolete)
lola: CANCELED task # 85 (type SRCH) for DLCround-PT-05a-CTLFireability-08 (obsolete)
lola: CANCELED task # 86 (type SRCH) for DLCround-PT-05a-CTLFireability-08 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-84.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 84 (type SKEL/EQUN) for DLCround-PT-05a-CTLFireability-08
lola: result : true
lola: FINISHED task # 86 (type SKEL/SRCH) for DLCround-PT-05a-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 44 (type EXCL) for 43 DLCround-PT-05a-CTLFireability-09
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 88 (type FNDP) for 59 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type EQUN) for 59 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 91 (type SRCH) for 59 DLCround-PT-05a-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 88 (type FNDP) for DLCround-PT-05a-CTLFireability-13
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 89 (type EQUN) for DLCround-PT-05a-CTLFireability-13 (obsolete)
lola: CANCELED task # 91 (type SRCH) for DLCround-PT-05a-CTLFireability-13 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/CTLFireability-89.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 89 (type EQUN) for DLCround-PT-05a-CTLFireability-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 99 (type FNDP) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type SRCH) for 3 DLCround-PT-05a-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 102 (type SRCH) for DLCround-PT-05a-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 99 (type FNDP) for DLCround-PT-05a-CTLFireability-01
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 100 (type EQUN) for DLCround-PT-05a-CTLFireability-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 100 (type EQUN) for DLCround-PT-05a-CTLFireability-01
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 103 (type FNDP) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 104 (type EQUN) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SRCH) for 32 DLCround-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 106 (type SRCH) for DLCround-PT-05a-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 103 (type FNDP) for DLCround-PT-05a-CTLFireability-08
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 104 (type EQUN) for DLCround-PT-05a-CTLFireability-08 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 104 (type EQUN) for DLCround-PT-05a-CTLFireability-08
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:737
lola: rewrite Frontend/Parser/formula_rewrite.k:693
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 44 (type EXCL) for DLCround-PT-05a-CTLFireability-09
lola: result : false
lola: markings : 92015
lola: fired transitions : 2341653
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 74 (type EXCL) for 73 DLCround-PT-05a-CTLFireability-15
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 74 (type EXCL) for DLCround-PT-05a-CTLFireability-15
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EXCL) for 70 DLCround-PT-05a-CTLFireability-14
lola: time limit : 211 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 2/211 1/32 DLCround-PT-05a-CTLFireability-14 94464 m, 18892 m/sec, 2747083 t fired, .
Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 7/211 2/32 DLCround-PT-05a-CTLFireability-14 432016 m, 67510 m/sec, 12500627 t fired, .
Time elapsed: 10 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 12/211 4/32 DLCround-PT-05a-CTLFireability-14 789439 m, 71484 m/sec, 21971912 t fired, .
Time elapsed: 15 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 17/211 5/32 DLCround-PT-05a-CTLFireability-14 1118724 m, 65857 m/sec, 31295471 t fired, .
Time elapsed: 20 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 22/211 6/32 DLCround-PT-05a-CTLFireability-14 1441607 m, 64576 m/sec, 40611640 t fired, .
Time elapsed: 25 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 27/211 8/32 DLCround-PT-05a-CTLFireability-14 1759689 m, 63616 m/sec, 50113713 t fired, .
Time elapsed: 30 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 32/211 9/32 DLCround-PT-05a-CTLFireability-14 2082323 m, 64526 m/sec, 59472971 t fired, .
Time elapsed: 35 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 37/211 10/32 DLCround-PT-05a-CTLFireability-14 2406783 m, 64892 m/sec, 68720582 t fired, .
Time elapsed: 40 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 42/211 12/32 DLCround-PT-05a-CTLFireability-14 2720310 m, 62705 m/sec, 77823972 t fired, .
Time elapsed: 45 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 47/211 13/32 DLCround-PT-05a-CTLFireability-14 3048196 m, 65577 m/sec, 86700404 t fired, .
Time elapsed: 50 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 52/211 14/32 DLCround-PT-05a-CTLFireability-14 3369860 m, 64332 m/sec, 95682835 t fired, .
Time elapsed: 55 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 57/211 16/32 DLCround-PT-05a-CTLFireability-14 3671813 m, 60390 m/sec, 104813647 t fired, .
Time elapsed: 60 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 62/211 17/32 DLCround-PT-05a-CTLFireability-14 3971414 m, 59920 m/sec, 113332768 t fired, .
Time elapsed: 65 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 67/211 18/32 DLCround-PT-05a-CTLFireability-14 4274314 m, 60580 m/sec, 122355114 t fired, .
Time elapsed: 70 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 72/211 20/32 DLCround-PT-05a-CTLFireability-14 4582158 m, 61568 m/sec, 131411180 t fired, .
Time elapsed: 75 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 77/211 21/32 DLCround-PT-05a-CTLFireability-14 4887869 m, 61142 m/sec, 140433196 t fired, .
Time elapsed: 80 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 82/211 22/32 DLCround-PT-05a-CTLFireability-14 5210233 m, 64472 m/sec, 149170650 t fired, .
Time elapsed: 85 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 87/211 24/32 DLCround-PT-05a-CTLFireability-14 5543681 m, 66689 m/sec, 158075700 t fired, .
Time elapsed: 90 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 92/211 25/32 DLCround-PT-05a-CTLFireability-14 5844045 m, 60072 m/sec, 166948672 t fired, .
Time elapsed: 95 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 97/211 26/32 DLCround-PT-05a-CTLFireability-14 6144987 m, 60188 m/sec, 175840735 t fired, .
Time elapsed: 100 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 102/211 27/32 DLCround-PT-05a-CTLFireability-14 6455694 m, 62141 m/sec, 184686599 t fired, .
Time elapsed: 105 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 107/211 29/32 DLCround-PT-05a-CTLFireability-14 6761327 m, 61126 m/sec, 193711251 t fired, .
Time elapsed: 110 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 112/211 30/32 DLCround-PT-05a-CTLFireability-14 7056812 m, 59097 m/sec, 202538046 t fired, .
Time elapsed: 115 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 117/211 31/32 DLCround-PT-05a-CTLFireability-14 7346440 m, 57925 m/sec, 211330110 t fired, .
Time elapsed: 120 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
71 CTL EXCL 122/211 32/32 DLCround-PT-05a-CTLFireability-14 7643778 m, 59467 m/sec, 220046391 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 71 (type EXCL) for DLCround-PT-05a-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-13: DISJ 0 1 0 0 4 0 0 7
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 68 (type EXCL) for 59 DLCround-PT-05a-CTLFireability-13
lola: time limit : 216 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for DLCround-PT-05a-CTLFireability-13
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 56 DLCround-PT-05a-CTLFireability-12
lola: time limit : 231 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for DLCround-PT-05a-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 49 DLCround-PT-05a-CTLFireability-11
lola: time limit : 247 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for DLCround-PT-05a-CTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 25 DLCround-PT-05a-CTLFireability-07
lola: time limit : 289 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 5/289 2/32 DLCround-PT-05a-CTLFireability-07 386664 m, 77332 m/sec, 9989228 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 10/289 4/32 DLCround-PT-05a-CTLFireability-07 859707 m, 94608 m/sec, 18676491 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 15/289 7/32 DLCround-PT-05a-CTLFireability-07 1511639 m, 130386 m/sec, 26522108 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 20/289 8/32 DLCround-PT-05a-CTLFireability-07 1904370 m, 78546 m/sec, 35186356 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 25/289 10/32 DLCround-PT-05a-CTLFireability-07 2367258 m, 92577 m/sec, 43368403 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 30/289 12/32 DLCround-PT-05a-CTLFireability-07 2772793 m, 81107 m/sec, 51758286 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 35/289 13/32 DLCround-PT-05a-CTLFireability-07 3115112 m, 68463 m/sec, 60529760 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 40/289 15/32 DLCround-PT-05a-CTLFireability-07 3533036 m, 83584 m/sec, 69132972 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 45/289 17/32 DLCround-PT-05a-CTLFireability-07 3955099 m, 84412 m/sec, 77750521 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 50/289 19/32 DLCround-PT-05a-CTLFireability-07 4399748 m, 88929 m/sec, 86003324 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 55/289 20/32 DLCround-PT-05a-CTLFireability-07 4817500 m, 83550 m/sec, 94353208 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 60/289 22/32 DLCround-PT-05a-CTLFireability-07 5215936 m, 79687 m/sec, 102723269 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 65/289 24/32 DLCround-PT-05a-CTLFireability-07 5728495 m, 102511 m/sec, 110477376 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 70/289 26/32 DLCround-PT-05a-CTLFireability-07 6171673 m, 88635 m/sec, 118875483 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 75/289 28/32 DLCround-PT-05a-CTLFireability-07 6619860 m, 89637 m/sec, 126924356 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 80/289 29/32 DLCround-PT-05a-CTLFireability-07 6992386 m, 74505 m/sec, 135435283 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
30 CTL EXCL 85/289 31/32 DLCround-PT-05a-CTLFireability-07 7305792 m, 62681 m/sec, 143977082 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 30 (type EXCL) for DLCround-PT-05a-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 25 DLCround-PT-05a-CTLFireability-07
lola: time limit : 307 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/307 2/32 DLCround-PT-05a-CTLFireability-07 434953 m, 86990 m/sec, 9289856 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/307 5/32 DLCround-PT-05a-CTLFireability-07 1015389 m, 116087 m/sec, 17646257 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/307 7/32 DLCround-PT-05a-CTLFireability-07 1626101 m, 122142 m/sec, 25691304 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/307 9/32 DLCround-PT-05a-CTLFireability-07 2051358 m, 85051 m/sec, 34272111 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/307 11/32 DLCround-PT-05a-CTLFireability-07 2582067 m, 106141 m/sec, 42211145 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/307 13/32 DLCround-PT-05a-CTLFireability-07 3066978 m, 96982 m/sec, 50387077 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/307 15/32 DLCround-PT-05a-CTLFireability-07 3440970 m, 74798 m/sec, 59112494 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/307 17/32 DLCround-PT-05a-CTLFireability-07 3916822 m, 95170 m/sec, 67546621 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/307 19/32 DLCround-PT-05a-CTLFireability-07 4346748 m, 85985 m/sec, 75956795 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/307 21/32 DLCround-PT-05a-CTLFireability-07 4844445 m, 99539 m/sec, 83966965 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/307 22/32 DLCround-PT-05a-CTLFireability-07 5287004 m, 88511 m/sec, 92129530 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/307 25/32 DLCround-PT-05a-CTLFireability-07 5845620 m, 111723 m/sec, 99845881 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/307 27/32 DLCround-PT-05a-CTLFireability-07 6331901 m, 97256 m/sec, 107842830 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/307 29/32 DLCround-PT-05a-CTLFireability-07 6821176 m, 97855 m/sec, 115780467 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/307 30/32 DLCround-PT-05a-CTLFireability-07 7234548 m, 82674 m/sec, 124105258 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 1 0 2 0 1 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 80/307 32/32 DLCround-PT-05a-CTLFireability-07 7619677 m, 77025 m/sec, 132375593 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for DLCround-PT-05a-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 DLCround-PT-05a-CTLFireability-06
lola: time limit : 329 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/329 2/32 DLCround-PT-05a-CTLFireability-06 335095 m, 67019 m/sec, 10006181 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/329 3/32 DLCround-PT-05a-CTLFireability-06 703718 m, 73724 m/sec, 19400087 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/329 5/32 DLCround-PT-05a-CTLFireability-06 1025508 m, 64358 m/sec, 28740027 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/329 6/32 DLCround-PT-05a-CTLFireability-06 1345511 m, 64000 m/sec, 37862111 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 25/329 7/32 DLCround-PT-05a-CTLFireability-06 1656893 m, 62276 m/sec, 47185332 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 30/329 9/32 DLCround-PT-05a-CTLFireability-06 1982618 m, 65145 m/sec, 56516773 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 35/329 10/32 DLCround-PT-05a-CTLFireability-06 2303194 m, 64115 m/sec, 65656479 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 40/329 11/32 DLCround-PT-05a-CTLFireability-06 2607490 m, 60859 m/sec, 74741770 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 45/329 13/32 DLCround-PT-05a-CTLFireability-06 2930949 m, 64691 m/sec, 83499925 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 50/329 14/32 DLCround-PT-05a-CTLFireability-06 3255234 m, 64857 m/sec, 92362606 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 55/329 15/32 DLCround-PT-05a-CTLFireability-06 3563283 m, 61609 m/sec, 101510209 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 60/329 17/32 DLCround-PT-05a-CTLFireability-06 3867146 m, 60772 m/sec, 110537298 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 65/329 18/32 DLCround-PT-05a-CTLFireability-06 4170026 m, 60576 m/sec, 119313374 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 70/329 19/32 DLCround-PT-05a-CTLFireability-06 4473817 m, 60758 m/sec, 128277976 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 75/329 20/32 DLCround-PT-05a-CTLFireability-06 4774729 m, 60182 m/sec, 137289356 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 80/329 22/32 DLCround-PT-05a-CTLFireability-06 5098586 m, 64771 m/sec, 146011386 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 85/329 23/32 DLCround-PT-05a-CTLFireability-06 5423527 m, 64988 m/sec, 154743987 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 90/329 24/32 DLCround-PT-05a-CTLFireability-06 5732794 m, 61853 m/sec, 163548486 t fired, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 95/329 25/32 DLCround-PT-05a-CTLFireability-06 6021783 m, 57797 m/sec, 172314465 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 100/329 27/32 DLCround-PT-05a-CTLFireability-06 6325389 m, 60721 m/sec, 181006290 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 105/329 28/32 DLCround-PT-05a-CTLFireability-06 6625887 m, 60099 m/sec, 189845301 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 110/329 29/32 DLCround-PT-05a-CTLFireability-06 6909947 m, 56812 m/sec, 198191593 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 115/329 30/32 DLCround-PT-05a-CTLFireability-06 7176809 m, 53372 m/sec, 206111001 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 120/329 31/32 DLCround-PT-05a-CTLFireability-06 7457506 m, 56139 m/sec, 214425515 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for DLCround-PT-05a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 DLCround-PT-05a-CTLFireability-05
lola: time limit : 352 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/352 2/32 DLCround-PT-05a-CTLFireability-05 420365 m, 84073 m/sec, 9554724 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 20 (type EXCL) for DLCround-PT-05a-CTLFireability-05
lola: result : false
lola: markings : 460160
lola: fired transitions : 10599638
lola: time used : 6.000000
lola: memory pages used : 2
lola: LAUNCH task # 10 (type EXCL) for 9 DLCround-PT-05a-CTLFireability-03
lola: time limit : 395 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 4/395 2/32 DLCround-PT-05a-CTLFireability-03 386436 m, 77287 m/sec, 9913634 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 9/395 3/32 DLCround-PT-05a-CTLFireability-03 723120 m, 67336 m/sec, 20379871 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 14/395 5/32 DLCround-PT-05a-CTLFireability-03 977762 m, 50928 m/sec, 30781038 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 19/395 6/32 DLCround-PT-05a-CTLFireability-03 1396685 m, 83784 m/sec, 40514549 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 24/395 8/32 DLCround-PT-05a-CTLFireability-03 1706352 m, 61933 m/sec, 50274297 t fired, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/395 9/32 DLCround-PT-05a-CTLFireability-03 2091385 m, 77006 m/sec, 61333963 t fired, .
Time elapsed: 466 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 36/395 10/32 DLCround-PT-05a-CTLFireability-03 2374642 m, 56651 m/sec, 71085197 t fired, .
Time elapsed: 472 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 41/395 12/32 DLCround-PT-05a-CTLFireability-03 2715209 m, 68113 m/sec, 80888553 t fired, .
Time elapsed: 477 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 46/395 13/32 DLCround-PT-05a-CTLFireability-03 3048485 m, 66655 m/sec, 90555019 t fired, .
Time elapsed: 482 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 51/395 14/32 DLCround-PT-05a-CTLFireability-03 3366671 m, 63637 m/sec, 100116880 t fired, .
Time elapsed: 487 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 56/395 16/32 DLCround-PT-05a-CTLFireability-03 3753915 m, 77448 m/sec, 109273821 t fired, .
Time elapsed: 492 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 61/395 18/32 DLCround-PT-05a-CTLFireability-03 4117530 m, 72723 m/sec, 118493879 t fired, .
Time elapsed: 497 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 66/395 19/32 DLCround-PT-05a-CTLFireability-03 4439805 m, 64455 m/sec, 128070932 t fired, .
Time elapsed: 502 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 71/395 20/32 DLCround-PT-05a-CTLFireability-03 4793318 m, 70702 m/sec, 138812923 t fired, .
Time elapsed: 507 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 76/395 22/32 DLCround-PT-05a-CTLFireability-03 5123690 m, 66074 m/sec, 148014505 t fired, .
Time elapsed: 512 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 81/395 23/32 DLCround-PT-05a-CTLFireability-03 5437037 m, 62669 m/sec, 157392749 t fired, .
Time elapsed: 517 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 86/395 24/32 DLCround-PT-05a-CTLFireability-03 5750066 m, 62605 m/sec, 166704651 t fired, .
Time elapsed: 522 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 92/395 26/32 DLCround-PT-05a-CTLFireability-03 6121009 m, 74188 m/sec, 175600372 t fired, .
Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 97/395 27/32 DLCround-PT-05a-CTLFireability-03 6454966 m, 66791 m/sec, 184661311 t fired, .
Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 102/395 29/32 DLCround-PT-05a-CTLFireability-03 6834604 m, 75927 m/sec, 193540189 t fired, .
Time elapsed: 538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 107/395 30/32 DLCround-PT-05a-CTLFireability-03 7138416 m, 60762 m/sec, 202625141 t fired, .
Time elapsed: 543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 113/395 31/32 DLCround-PT-05a-CTLFireability-03 7455176 m, 63352 m/sec, 211676696 t fired, .
Time elapsed: 549 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for DLCround-PT-05a-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 554 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 DLCround-PT-05a-CTLFireability-02
lola: time limit : 435 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/435 2/32 DLCround-PT-05a-CTLFireability-02 312760 m, 62552 m/sec, 9720891 t fired, .
Time elapsed: 559 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/435 3/32 DLCround-PT-05a-CTLFireability-02 659247 m, 69297 m/sec, 16758729 t fired, .
Time elapsed: 564 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 16/435 5/32 DLCround-PT-05a-CTLFireability-02 966981 m, 61546 m/sec, 24600662 t fired, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 21/435 6/32 DLCround-PT-05a-CTLFireability-02 1233079 m, 53219 m/sec, 32299339 t fired, .
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCround-PT-05a-CTLFireability-01: EF true findpath
DLCround-PT-05a-CTLFireability-05: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-09: CTL false CTL model checker
DLCround-PT-05a-CTLFireability-11: DISJ true CTL model checker
DLCround-PT-05a-CTLFireability-12: CTL true CTL model checker
DLCround-PT-05a-CTLFireability-13: DISJ false DISJ
DLCround-PT-05a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCround-PT-05a-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
DLCround-PT-05a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
DLCround-PT-05a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DLCround-PT-05a-CTLFireability-07: CONJ 0 0 0 0 2 0 2 0
DLCround-PT-05a-CTLFireability-08: DISJ 0 2 0 0 8 0 0 2
DLCround-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCround-PT-05a-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 26/435 7/32 DLCround-PT-05a-CTLFireability-02 1488712 m, 51126 m/sec, 39959196 t fired, .
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCround-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCround-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477200650"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCround-PT-05a.tgz
mv DLCround-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;