Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100604.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-8a, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100604
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.2M
-rw-r--r-- 1 mcc users 7.8K Feb 26 07:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 07:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 25 18:01 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 25 18:01 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 27 06:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 203K Feb 27 06:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 26 21:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 21:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 8.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-00
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-01
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-02
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-03
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-04
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-05
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-06
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-07
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-08
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-09
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-10
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-11
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-12
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-13
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-14
FORMULA_NAME DLCflexbar-PT-8a-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678306175204

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-8a
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-8a
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA DLCflexbar-PT-8a-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678306536562

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-01: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 21 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 6 (type CNST) for 3 DLCflexbar-PT-8a-LTLFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 6 (type CNST) for DLCflexbar-PT-8a-LTLFireability-01
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 76 (type SKEL/SRCH) for 33 DLCflexbar-PT-8a-LTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SKEL/SRCH) for DLCflexbar-PT-8a-LTLFireability-07
lola: result : false
lola: markings : 162
lola: fired transitions : 325
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-08: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 26 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 77 (type SKEL/SRCH) for 44 DLCflexbar-PT-8a-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type SKEL/SRCH) for DLCflexbar-PT-8a-LTLFireability-08
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 31 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 36 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 41 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 46 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 51 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 56 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 61 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 66 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 71 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 76 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 81 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 91 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 96 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 101 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-04: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 106 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:767
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:767
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:793
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:767
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:793
lola: LAUNCH task # 81 (type EXCL) for 16 DLCflexbar-PT-8a-LTLFireability-04
lola: time limit : 183 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 79 (type FNDP) for 16 DLCflexbar-PT-8a-LTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type EQUN) for 16 DLCflexbar-PT-8a-LTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SRCH) for 16 DLCflexbar-PT-8a-LTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:767
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 81 (type EXCL) for DLCflexbar-PT-8a-LTLFireability-04
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 79 (type FNDP) for DLCflexbar-PT-8a-LTLFireability-04 (obsolete)
lola: CANCELED task # 80 (type EQUN) for DLCflexbar-PT-8a-LTLFireability-04 (obsolete)
lola: CANCELED task # 82 (type SRCH) for DLCflexbar-PT-8a-LTLFireability-04 (obsolete)
lola: FINISHED task # 82 (type SRCH) for DLCflexbar-PT-8a-LTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 79 (type FNDP) for DLCflexbar-PT-8a-LTLFireability-04
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-80.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 80 (type EQUN) for DLCflexbar-PT-8a-LTLFireability-04
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 111 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 116 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 121 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 126 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 131 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 136 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 141 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 146 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 151 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 156 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 161 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 166 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 83 (type EXCL) for 51 DLCflexbar-PT-8a-LTLFireability-09
lola: time limit : 214 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-09: F 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
83 EG EXCL 1/214 1/32 DLCflexbar-PT-8a-LTLFireability-09 --

Time elapsed: 171 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 83 (type EXCL) for DLCflexbar-PT-8a-LTLFireability-09
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 DLCflexbar-PT-8a-LTLFireability-03
lola: time limit : 228 sec
lola: memory limit: 32 pages
lola: FINISHED task # 14 (type EXCL) for DLCflexbar-PT-8a-LTLFireability-03
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 DLCflexbar-PT-8a-LTLFireability-00
lola: time limit : 244 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for DLCflexbar-PT-8a-LTLFireability-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 176 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 181 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 186 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 191 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 196 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 60 (type EXCL) for 57 DLCflexbar-PT-8a-LTLFireability-11
lola: time limit : 261 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for DLCflexbar-PT-8a-LTLFireability-11
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 DLCflexbar-PT-8a-LTLFireability-10
lola: time limit : 283 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 0 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 2/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 2057 m, 411 m/sec, 25941 t fired, .

Time elapsed: 201 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 7/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 10359 m, 1660 m/sec, 143966 t fired, .

Time elapsed: 206 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 12/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 41536 m, 6235 m/sec, 656293 t fired, .

Time elapsed: 211 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 17/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 68309 m, 5354 m/sec, 1224848 t fired, .

Time elapsed: 216 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 22/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 86698 m, 3677 m/sec, 1797857 t fired, .

Time elapsed: 221 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 27/283 1/32 DLCflexbar-PT-8a-LTLFireability-10 97167 m, 2093 m/sec, 2430873 t fired, .

Time elapsed: 226 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 32/283 2/32 DLCflexbar-PT-8a-LTLFireability-10 120181 m, 4602 m/sec, 3073020 t fired, .

Time elapsed: 231 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 37/283 2/32 DLCflexbar-PT-8a-LTLFireability-10 147988 m, 5561 m/sec, 3561708 t fired, .

Time elapsed: 236 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 42/283 2/32 DLCflexbar-PT-8a-LTLFireability-10 171084 m, 4619 m/sec, 4093390 t fired, .

Time elapsed: 241 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 47/283 2/32 DLCflexbar-PT-8a-LTLFireability-10 187221 m, 3227 m/sec, 4644517 t fired, .

Time elapsed: 246 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 52/283 2/32 DLCflexbar-PT-8a-LTLFireability-10 196206 m, 1797 m/sec, 5354597 t fired, .

Time elapsed: 251 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 57/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 220446 m, 4848 m/sec, 5862185 t fired, .

Time elapsed: 256 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 62/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 244357 m, 4782 m/sec, 6308516 t fired, .

Time elapsed: 261 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 67/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 265923 m, 4313 m/sec, 6815224 t fired, .

Time elapsed: 266 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 72/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 282324 m, 3280 m/sec, 7349068 t fired, .

Time elapsed: 271 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 77/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 292803 m, 2095 m/sec, 7949304 t fired, .

Time elapsed: 276 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 82/283 3/32 DLCflexbar-PT-8a-LTLFireability-10 310153 m, 3470 m/sec, 8625612 t fired, .

Time elapsed: 281 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 87/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 337824 m, 5534 m/sec, 9088833 t fired, .

Time elapsed: 286 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 92/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 362355 m, 4906 m/sec, 9618423 t fired, .

Time elapsed: 291 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 97/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 377540 m, 3037 m/sec, 10067256 t fired, .

Time elapsed: 296 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 102/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 389120 m, 2316 m/sec, 10636209 t fired, .

Time elapsed: 301 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 107/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 404125 m, 3001 m/sec, 11294121 t fired, .

Time elapsed: 306 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 112/283 4/32 DLCflexbar-PT-8a-LTLFireability-10 414930 m, 2161 m/sec, 11464618 t fired, .

Time elapsed: 311 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 117/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 431224 m, 3258 m/sec, 11743577 t fired, .

Time elapsed: 316 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 122/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 446652 m, 3085 m/sec, 12045351 t fired, .

Time elapsed: 321 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 128/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 459191 m, 2507 m/sec, 12335201 t fired, .

Time elapsed: 327 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 133/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 472938 m, 2749 m/sec, 12736677 t fired, .

Time elapsed: 332 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 138/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 483088 m, 2030 m/sec, 13173842 t fired, .

Time elapsed: 337 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 143/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 490699 m, 1522 m/sec, 13862053 t fired, .

Time elapsed: 342 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 150/283 5/32 DLCflexbar-PT-8a-LTLFireability-10 513398 m, 4539 m/sec, 14209354 t fired, .

Time elapsed: 349 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 155/283 6/32 DLCflexbar-PT-8a-LTLFireability-10 528706 m, 3061 m/sec, 14475649 t fired, .

Time elapsed: 354 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-LTLFireability-00: LTL true LTL model checker
DLCflexbar-PT-8a-LTLFireability-01: CONJ false preprocessing
DLCflexbar-PT-8a-LTLFireability-03: LTL false LTL model checker
DLCflexbar-PT-8a-LTLFireability-04: CONJ false state space
DLCflexbar-PT-8a-LTLFireability-08: CONJ false skeleton: LTL model checker
DLCflexbar-PT-8a-LTLFireability-09: F false state space / EG

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-07: CONJ 0 3 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-11: CONJ 0 1 0 0 3 0 0 0
DLCflexbar-PT-8a-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 LTL EXCL 161/283 6/32 DLCflexbar-PT-8a-LTLFireability-10 545346 m, 3328 m/sec, 14808285 t fired, .

Time elapsed: 360 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ltlfireabilityconf --formula=$DIR/LTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-8a"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-8a, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100604"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-8a.tgz
mv DLCflexbar-PT-8a execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;