Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100602.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-8a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100602
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.2M
-rw-r--r-- 1 mcc users 7.8K Feb 26 07:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 26 07:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 25 18:01 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 25 18:01 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 18K Feb 27 06:24 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 203K Feb 27 06:24 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 26 21:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 21:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 8.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-8a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678305785074

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-8a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-8a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCflexbar-PT-8a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-8a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678306215880

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-01: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 152 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-CTLFireability-00: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-01: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-14: AG 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 157 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-01: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-04: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-8a-CTLFireability-14: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 162 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 52 (type SKEL/SRCH) for 34 DLCflexbar-PT-8a-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-8a-CTLFireability-10
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: LAUNCH task # 55 (type SKEL/SRCH) for 19 DLCflexbar-PT-8a-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type SKEL/SRCH) for DLCflexbar-PT-8a-CTLFireability-05
lola: result : false
lola: markings : 109
lola: fired transitions : 616
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-8a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-01: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-8a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-14: AG 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

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DLCflexbar-PT-8a-CTLFireability-05: SP ECTL 0 0 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-14: AG 0 0 0 0 1 0 0 0
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-8a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 40/254 2/32 DLCflexbar-PT-8a-CTLFireability-11 210174 m, 17084 m/sec, 3818064 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-8a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 1 0 0 1 0 0 0
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DLCflexbar-PT-8a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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38 CTL EXCL 48/254 2/32 DLCflexbar-PT-8a-CTLFireability-11 220142 m, 1993 m/sec, 3996633 t fired, .

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DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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38 CTL EXCL 53/254 2/32 DLCflexbar-PT-8a-CTLFireability-11 295679 m, 15107 m/sec, 5352629 t fired, .

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DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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38 CTL EXCL 58/254 2/32 DLCflexbar-PT-8a-CTLFireability-11 314986 m, 3861 m/sec, 5698098 t fired, .

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DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 63/254 3/32 DLCflexbar-PT-8a-CTLFireability-11 366495 m, 10301 m/sec, 6615440 t fired, .

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DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 68/254 3/32 DLCflexbar-PT-8a-CTLFireability-11 469942 m, 20689 m/sec, 8469694 t fired, .

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DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 1 0 0 1 0 0 0
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38 CTL EXCL 73/254 4/32 DLCflexbar-PT-8a-CTLFireability-11 537778 m, 13567 m/sec, 9689699 t fired, .

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DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 78/254 4/32 DLCflexbar-PT-8a-CTLFireability-11 576510 m, 7746 m/sec, 10382504 t fired, .

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DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 83/254 5/32 DLCflexbar-PT-8a-CTLFireability-11 656594 m, 16016 m/sec, 11815845 t fired, .

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DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 89/254 5/32 DLCflexbar-PT-8a-CTLFireability-11 742537 m, 17188 m/sec, 13352666 t fired, .

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38 CTL EXCL 94/254 6/32 DLCflexbar-PT-8a-CTLFireability-11 834881 m, 18468 m/sec, 15006974 t fired, .

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38 CTL EXCL 99/254 6/32 DLCflexbar-PT-8a-CTLFireability-11 933498 m, 19723 m/sec, 16778170 t fired, .

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DLCflexbar-PT-8a-CTLFireability-10: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-8a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 104/254 7/32 DLCflexbar-PT-8a-CTLFireability-11 1011227 m, 15545 m/sec, 18167191 t fired, .

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DLCflexbar-PT-8a-CTLFireability-01: CONJ false state space / EG
DLCflexbar-PT-8a-CTLFireability-05: SP ECTL true LTL model checker
DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 109/254 8/32 DLCflexbar-PT-8a-CTLFireability-11 1120040 m, 21762 m/sec, 20113607 t fired, .

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DLCflexbar-PT-8a-CTLFireability-14: AG false state space

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38 CTL EXCL 114/254 8/32 DLCflexbar-PT-8a-CTLFireability-11 1224468 m, 20885 m/sec, 21979854 t fired, .

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38 CTL EXCL 119/254 9/32 DLCflexbar-PT-8a-CTLFireability-11 1328250 m, 20756 m/sec, 23849523 t fired, .

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38 CTL EXCL 124/254 10/32 DLCflexbar-PT-8a-CTLFireability-11 1437445 m, 21839 m/sec, 25800148 t fired, .

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38 CTL EXCL 129/254 10/32 DLCflexbar-PT-8a-CTLFireability-11 1536809 m, 19872 m/sec, 27585067 t fired, .

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38 CTL EXCL 134/254 11/32 DLCflexbar-PT-8a-CTLFireability-11 1644894 m, 21617 m/sec, 29534275 t fired, .

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-8a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-8a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100602"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-8a.tgz
mv DLCflexbar-PT-8a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;