Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100586.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-7a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100586
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 6.7M
-rw-r--r-- 1 mcc users 7.8K Feb 25 20:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 20:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 18:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 18:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:52 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:52 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 03:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 175K Feb 26 03:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 00:35 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 00:35 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 6.2M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-7a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678303381928

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-7a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-7a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCflexbar-PT-7a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-7a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DLCflexbar-PT-7a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678303789694

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type SKEL/FNDP) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/SRCH) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type SKEL/SRCH) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 51 (type SKEL/SRCH) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for DLCflexbar-PT-7a-CTLFireability-08 (obsolete)
lola: CANCELED task # 50 (type EQUN) for DLCflexbar-PT-7a-CTLFireability-08 (obsolete)
lola: FINISHED task # 49 (type SKEL/FNDP) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-50.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 50 (type SKEL/EQUN) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-08: EF 0 0 0 0 4 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-08: EF 0 0 0 0 4 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type EXCL) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 220 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 53 (type FNDP) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SRCH) for 24 DLCflexbar-PT-7a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type EXCL) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for DLCflexbar-PT-7a-CTLFireability-08 (obsolete)
lola: CANCELED task # 54 (type EQUN) for DLCflexbar-PT-7a-CTLFireability-08 (obsolete)
lola: CANCELED task # 56 (type SRCH) for DLCflexbar-PT-7a-CTLFireability-08 (obsolete)
lola: FINISHED task # 56 (type SRCH) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 53 (type FNDP) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 54 (type EQUN) for DLCflexbar-PT-7a-CTLFireability-08
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 80 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 85 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-03: EGEF 1 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 DLCflexbar-PT-7a-CTLFireability-03
lola: time limit : 233 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: FINISHED task # 10 (type EXCL) for DLCflexbar-PT-7a-CTLFireability-03
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 DLCflexbar-PT-7a-CTLFireability-14
lola: time limit : 250 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 2/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 2769 m, 553 m/sec, 258056 t fired, .

Time elapsed: 95 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 7/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 8278 m, 1101 m/sec, 782565 t fired, .

Time elapsed: 100 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 1 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 12/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 22666 m, 2877 m/sec, 2224944 t fired, .

Time elapsed: 105 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 17/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 53774 m, 6221 m/sec, 5577556 t fired, .

Time elapsed: 110 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 22/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 88046 m, 6854 m/sec, 9277945 t fired, .

Time elapsed: 115 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 27/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 122203 m, 6831 m/sec, 12920945 t fired, .

Time elapsed: 120 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 32/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 156358 m, 6831 m/sec, 16576271 t fired, .

Time elapsed: 125 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 37/250 1/32 DLCflexbar-PT-7a-CTLFireability-14 190110 m, 6750 m/sec, 20203918 t fired, .

Time elapsed: 130 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 42/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 223788 m, 6735 m/sec, 23846316 t fired, .

Time elapsed: 135 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 47/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 257572 m, 6756 m/sec, 27476836 t fired, .

Time elapsed: 140 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 52/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 291238 m, 6733 m/sec, 31074637 t fired, .

Time elapsed: 145 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 57/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 324943 m, 6741 m/sec, 34672484 t fired, .

Time elapsed: 150 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 62/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 357956 m, 6602 m/sec, 38204265 t fired, .

Time elapsed: 155 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 67/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 390558 m, 6520 m/sec, 41713171 t fired, .

Time elapsed: 160 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 72/250 2/32 DLCflexbar-PT-7a-CTLFireability-14 422761 m, 6440 m/sec, 45197662 t fired, .

Time elapsed: 165 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 77/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 456023 m, 6652 m/sec, 48748427 t fired, .

Time elapsed: 170 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 82/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 488611 m, 6517 m/sec, 52248630 t fired, .

Time elapsed: 175 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 87/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 521303 m, 6538 m/sec, 55788008 t fired, .

Time elapsed: 180 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 92/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 553907 m, 6520 m/sec, 59319711 t fired, .

Time elapsed: 185 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 97/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 586161 m, 6450 m/sec, 62820159 t fired, .

Time elapsed: 190 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 102/250 3/32 DLCflexbar-PT-7a-CTLFireability-14 619094 m, 6586 m/sec, 66355670 t fired, .

Time elapsed: 195 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 107/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 652255 m, 6632 m/sec, 69908800 t fired, .

Time elapsed: 200 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 112/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 685489 m, 6646 m/sec, 73465483 t fired, .

Time elapsed: 205 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 117/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 718433 m, 6588 m/sec, 77039644 t fired, .

Time elapsed: 210 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 122/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 751868 m, 6687 m/sec, 80604113 t fired, .

Time elapsed: 215 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 127/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 785019 m, 6630 m/sec, 84160027 t fired, .

Time elapsed: 220 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 132/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 817444 m, 6485 m/sec, 87688744 t fired, .

Time elapsed: 225 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 137/250 4/32 DLCflexbar-PT-7a-CTLFireability-14 850679 m, 6647 m/sec, 91239270 t fired, .

Time elapsed: 230 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 142/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 885071 m, 6878 m/sec, 94909505 t fired, .

Time elapsed: 235 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 147/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 918676 m, 6721 m/sec, 98528410 t fired, .

Time elapsed: 240 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 152/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 951874 m, 6639 m/sec, 102095917 t fired, .

Time elapsed: 245 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 157/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 985473 m, 6719 m/sec, 105682210 t fired, .

Time elapsed: 250 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 162/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 1018795 m, 6664 m/sec, 109275210 t fired, .

Time elapsed: 255 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 167/250 5/32 DLCflexbar-PT-7a-CTLFireability-14 1051408 m, 6522 m/sec, 112805891 t fired, .

Time elapsed: 260 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 172/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1084132 m, 6544 m/sec, 116371060 t fired, .

Time elapsed: 265 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 177/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1117081 m, 6589 m/sec, 119951520 t fired, .

Time elapsed: 270 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 182/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1150751 m, 6734 m/sec, 123555850 t fired, .

Time elapsed: 275 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 187/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1184027 m, 6655 m/sec, 127130767 t fired, .

Time elapsed: 280 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 192/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1216753 m, 6545 m/sec, 130653877 t fired, .

Time elapsed: 285 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 197/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1249702 m, 6589 m/sec, 134166685 t fired, .

Time elapsed: 290 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 202/250 6/32 DLCflexbar-PT-7a-CTLFireability-14 1280628 m, 6185 m/sec, 137507755 t fired, .

Time elapsed: 295 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 207/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1310008 m, 5876 m/sec, 140654651 t fired, .

Time elapsed: 300 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 212/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1337219 m, 5442 m/sec, 143635762 t fired, .

Time elapsed: 305 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 217/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1366485 m, 5853 m/sec, 146821474 t fired, .

Time elapsed: 310 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 222/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1394239 m, 5550 m/sec, 149827048 t fired, .

Time elapsed: 315 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 227/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1419359 m, 5024 m/sec, 152504733 t fired, .

Time elapsed: 320 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 232/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1450438 m, 6215 m/sec, 155837301 t fired, .

Time elapsed: 325 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 237/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1478154 m, 5543 m/sec, 158817776 t fired, .

Time elapsed: 330 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 242/250 7/32 DLCflexbar-PT-7a-CTLFireability-14 1507976 m, 5964 m/sec, 161997377 t fired, .

Time elapsed: 335 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 247/250 8/32 DLCflexbar-PT-7a-CTLFireability-14 1538487 m, 6102 m/sec, 165285392 t fired, .

Time elapsed: 340 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for DLCflexbar-PT-7a-CTLFireability-14 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 0 0 1 1 0 0
DLCflexbar-PT-7a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 345 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 DLCflexbar-PT-7a-CTLFireability-15
lola: time limit : 250 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 43 (type EXCL) for 42 DLCflexbar-PT-7a-CTLFireability-14
lola: time limit : 3255 sec
lola: memory limit: 5 pages
lola: FINISHED task # 46 (type EXCL) for DLCflexbar-PT-7a-CTLFireability-15
lola: result : true
lola: markings : 1
lola: fired transitions : 2
lola: time used : 2.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 4/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 19049 m, -303887 m/sec, 1851631 t fired, .

Time elapsed: 350 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 9/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 50843 m, 6358 m/sec, 5259326 t fired, .

Time elapsed: 355 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 14/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 80017 m, 5834 m/sec, 8417646 t fired, .

Time elapsed: 360 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 19/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 111483 m, 6293 m/sec, 11783920 t fired, .

Time elapsed: 365 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 24/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 143203 m, 6344 m/sec, 15186961 t fired, .

Time elapsed: 370 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 29/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 169817 m, 5322 m/sec, 18028592 t fired, .

Time elapsed: 375 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 34/250 1/5 DLCflexbar-PT-7a-CTLFireability-14 201715 m, 6379 m/sec, 21457210 t fired, .

Time elapsed: 380 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 39/250 2/5 DLCflexbar-PT-7a-CTLFireability-14 231837 m, 6024 m/sec, 24718174 t fired, .

Time elapsed: 385 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 44/250 2/5 DLCflexbar-PT-7a-CTLFireability-14 261014 m, 5835 m/sec, 27850973 t fired, .

Time elapsed: 390 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 49/250 2/5 DLCflexbar-PT-7a-CTLFireability-14 291835 m, 6164 m/sec, 31137521 t fired, .

Time elapsed: 395 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 54/250 2/5 DLCflexbar-PT-7a-CTLFireability-14 320686 m, 5770 m/sec, 34225952 t fired, .

Time elapsed: 400 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-7a-CTLFireability-03: EGEF true CTL model checker
DLCflexbar-PT-7a-CTLFireability-08: EF true state space
DLCflexbar-PT-7a-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-7a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-7a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 59/250 2/5 DLCflexbar-PT-7a-CTLFireability-14 345648 m, 4992 m/sec, 36906033 t fired, .

Time elapsed: 405 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-7a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-7a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100586"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-7a.tgz
mv DLCflexbar-PT-7a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;