About the Execution of LoLA for DLCflexbar-PT-6a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16217.136 | 650047.00 | 773858.00 | 13976.60 | ??????????F??FFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477100570.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-6a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477100570
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.6M
-rw-r--r-- 1 mcc users 6.2K Feb 25 17:21 CTLCardinality.txt
-rw-r--r-- 1 mcc users 66K Feb 25 17:21 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 38K Feb 25 16:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Feb 25 20:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 88K Feb 25 20:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 25 18:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K Feb 25 18:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 4.2M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-6a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678301714146
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-6a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-6a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCflexbar-PT-6a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-6a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-6a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-6a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678302364193
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 60 (type SKEL/SRCH) for 31 DLCflexbar-PT-6a-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type SKEL/SRCH) for DLCflexbar-PT-6a-CTLFireability-09
lola: result : false
lola: markings : 106
lola: fired transitions : 548
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 16 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 21 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 58 (type EXCL) for 57 DLCflexbar-PT-6a-CTLFireability-15
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 58 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 7
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 18 DLCflexbar-PT-6a-CTLFireability-06
lola: time limit : 198 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 0 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 1 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 0/198 0/32 DLCflexbar-PT-6a-CTLFireability-06 --
Time elapsed: 27 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 5/198 1/32 DLCflexbar-PT-6a-CTLFireability-06 19097 m, 3819 m/sec, 1692067 t fired, .
Time elapsed: 32 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 10/198 1/32 DLCflexbar-PT-6a-CTLFireability-06 70415 m, 10263 m/sec, 6280933 t fired, .
Time elapsed: 37 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 15/198 1/32 DLCflexbar-PT-6a-CTLFireability-06 122929 m, 10502 m/sec, 10994150 t fired, .
Time elapsed: 42 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 20/198 1/32 DLCflexbar-PT-6a-CTLFireability-06 175500 m, 10514 m/sec, 15697146 t fired, .
Time elapsed: 47 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 25/198 2/32 DLCflexbar-PT-6a-CTLFireability-06 228074 m, 10514 m/sec, 20393225 t fired, .
Time elapsed: 52 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 30/198 2/32 DLCflexbar-PT-6a-CTLFireability-06 280311 m, 10447 m/sec, 25110448 t fired, .
Time elapsed: 57 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 35/198 2/32 DLCflexbar-PT-6a-CTLFireability-06 331918 m, 10321 m/sec, 29757996 t fired, .
Time elapsed: 62 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 40/198 2/32 DLCflexbar-PT-6a-CTLFireability-06 383834 m, 10383 m/sec, 34405874 t fired, .
Time elapsed: 67 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 45/198 3/32 DLCflexbar-PT-6a-CTLFireability-06 436126 m, 10458 m/sec, 39095805 t fired, .
Time elapsed: 72 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 50/198 3/32 DLCflexbar-PT-6a-CTLFireability-06 487864 m, 10347 m/sec, 43754948 t fired, .
Time elapsed: 77 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 55/198 3/32 DLCflexbar-PT-6a-CTLFireability-06 539658 m, 10358 m/sec, 48383185 t fired, .
Time elapsed: 82 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 60/198 3/32 DLCflexbar-PT-6a-CTLFireability-06 591175 m, 10303 m/sec, 52975013 t fired, .
Time elapsed: 87 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 65/198 4/32 DLCflexbar-PT-6a-CTLFireability-06 642867 m, 10338 m/sec, 57651594 t fired, .
Time elapsed: 92 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 70/198 4/32 DLCflexbar-PT-6a-CTLFireability-06 694391 m, 10304 m/sec, 62320361 t fired, .
Time elapsed: 97 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 75/198 4/32 DLCflexbar-PT-6a-CTLFireability-06 745743 m, 10270 m/sec, 66905834 t fired, .
Time elapsed: 102 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 80/198 4/32 DLCflexbar-PT-6a-CTLFireability-06 797257 m, 10302 m/sec, 71524241 t fired, .
Time elapsed: 107 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 85/198 4/32 DLCflexbar-PT-6a-CTLFireability-06 848500 m, 10248 m/sec, 76146327 t fired, .
Time elapsed: 112 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 90/198 5/32 DLCflexbar-PT-6a-CTLFireability-06 899511 m, 10202 m/sec, 80674401 t fired, .
Time elapsed: 117 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 95/198 5/32 DLCflexbar-PT-6a-CTLFireability-06 949692 m, 10036 m/sec, 85194578 t fired, .
Time elapsed: 122 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 100/198 5/32 DLCflexbar-PT-6a-CTLFireability-06 999414 m, 9944 m/sec, 89711162 t fired, .
Time elapsed: 127 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 105/198 5/32 DLCflexbar-PT-6a-CTLFireability-06 1049962 m, 10109 m/sec, 94291151 t fired, .
Time elapsed: 132 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 110/198 6/32 DLCflexbar-PT-6a-CTLFireability-06 1100569 m, 10121 m/sec, 98854878 t fired, .
Time elapsed: 137 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 115/198 6/32 DLCflexbar-PT-6a-CTLFireability-06 1151230 m, 10132 m/sec, 103424522 t fired, .
Time elapsed: 142 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 120/198 6/32 DLCflexbar-PT-6a-CTLFireability-06 1202283 m, 10210 m/sec, 108029851 t fired, .
Time elapsed: 147 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 125/198 6/32 DLCflexbar-PT-6a-CTLFireability-06 1253551 m, 10253 m/sec, 112604618 t fired, .
Time elapsed: 152 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 130/198 7/32 DLCflexbar-PT-6a-CTLFireability-06 1304138 m, 10117 m/sec, 117107850 t fired, .
Time elapsed: 157 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 135/198 7/32 DLCflexbar-PT-6a-CTLFireability-06 1354477 m, 10067 m/sec, 121642592 t fired, .
Time elapsed: 162 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 140/198 7/32 DLCflexbar-PT-6a-CTLFireability-06 1405163 m, 10137 m/sec, 126216484 t fired, .
Time elapsed: 167 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 145/198 7/32 DLCflexbar-PT-6a-CTLFireability-06 1455946 m, 10156 m/sec, 130833820 t fired, .
Time elapsed: 172 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 150/198 8/32 DLCflexbar-PT-6a-CTLFireability-06 1506502 m, 10111 m/sec, 135420793 t fired, .
Time elapsed: 177 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 155/198 8/32 DLCflexbar-PT-6a-CTLFireability-06 1557204 m, 10140 m/sec, 140037410 t fired, .
Time elapsed: 182 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 160/198 8/32 DLCflexbar-PT-6a-CTLFireability-06 1608147 m, 10188 m/sec, 144616702 t fired, .
Time elapsed: 187 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 165/198 8/32 DLCflexbar-PT-6a-CTLFireability-06 1658368 m, 10044 m/sec, 149106390 t fired, .
Time elapsed: 192 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 170/198 8/32 DLCflexbar-PT-6a-CTLFireability-06 1707927 m, 9911 m/sec, 153518293 t fired, .
Time elapsed: 197 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 175/198 9/32 DLCflexbar-PT-6a-CTLFireability-06 1757616 m, 9937 m/sec, 158007996 t fired, .
Time elapsed: 202 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 180/198 9/32 DLCflexbar-PT-6a-CTLFireability-06 1808239 m, 10124 m/sec, 162582922 t fired, .
Time elapsed: 207 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 185/198 9/32 DLCflexbar-PT-6a-CTLFireability-06 1858973 m, 10146 m/sec, 167058365 t fired, .
Time elapsed: 212 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 190/198 9/32 DLCflexbar-PT-6a-CTLFireability-06 1908898 m, 9985 m/sec, 171516985 t fired, .
Time elapsed: 217 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 195/198 10/32 DLCflexbar-PT-6a-CTLFireability-06 1958672 m, 9954 m/sec, 175966578 t fired, .
Time elapsed: 222 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 21 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-06 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 1 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 227 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 55 (type EXCL) for 54 DLCflexbar-PT-6a-CTLFireability-14
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 21 (type EXCL) for 18 DLCflexbar-PT-6a-CTLFireability-06
lola: time limit : 3373 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-14
lola: result : false
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 5/198 1/5 DLCflexbar-PT-6a-CTLFireability-06 53254 m, -381083 m/sec, 4753992 t fired, .
Time elapsed: 232 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 10/198 1/5 DLCflexbar-PT-6a-CTLFireability-06 105365 m, 10422 m/sec, 9441919 t fired, .
Time elapsed: 237 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 15/198 1/5 DLCflexbar-PT-6a-CTLFireability-06 158045 m, 10536 m/sec, 14130006 t fired, .
Time elapsed: 242 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 20/198 1/5 DLCflexbar-PT-6a-CTLFireability-06 210162 m, 10423 m/sec, 18801907 t fired, .
Time elapsed: 247 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 25/198 2/5 DLCflexbar-PT-6a-CTLFireability-06 262731 m, 10513 m/sec, 23530900 t fired, .
Time elapsed: 252 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 30/198 2/5 DLCflexbar-PT-6a-CTLFireability-06 314382 m, 10330 m/sec, 28179698 t fired, .
Time elapsed: 257 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 35/198 2/5 DLCflexbar-PT-6a-CTLFireability-06 366089 m, 10341 m/sec, 32810822 t fired, .
Time elapsed: 262 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 40/198 2/5 DLCflexbar-PT-6a-CTLFireability-06 418080 m, 10398 m/sec, 37463357 t fired, .
Time elapsed: 267 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 45/198 3/5 DLCflexbar-PT-6a-CTLFireability-06 470132 m, 10410 m/sec, 42147630 t fired, .
Time elapsed: 272 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 50/198 3/5 DLCflexbar-PT-6a-CTLFireability-06 521517 m, 10277 m/sec, 46768013 t fired, .
Time elapsed: 277 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 55/198 3/5 DLCflexbar-PT-6a-CTLFireability-06 573311 m, 10358 m/sec, 51379774 t fired, .
Time elapsed: 282 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 60/198 3/5 DLCflexbar-PT-6a-CTLFireability-06 624871 m, 10312 m/sec, 56021983 t fired, .
Time elapsed: 287 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 65/198 4/5 DLCflexbar-PT-6a-CTLFireability-06 676433 m, 10312 m/sec, 60699114 t fired, .
Time elapsed: 292 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 70/198 4/5 DLCflexbar-PT-6a-CTLFireability-06 727811 m, 10275 m/sec, 65284665 t fired, .
Time elapsed: 297 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 75/198 4/5 DLCflexbar-PT-6a-CTLFireability-06 779177 m, 10273 m/sec, 69905506 t fired, .
Time elapsed: 302 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 80/198 4/5 DLCflexbar-PT-6a-CTLFireability-06 830546 m, 10273 m/sec, 74525249 t fired, .
Time elapsed: 307 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 85/198 5/5 DLCflexbar-PT-6a-CTLFireability-06 882082 m, 10307 m/sec, 79122268 t fired, .
Time elapsed: 312 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 90/198 5/5 DLCflexbar-PT-6a-CTLFireability-06 932507 m, 10085 m/sec, 83637608 t fired, .
Time elapsed: 317 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 95/198 5/5 DLCflexbar-PT-6a-CTLFireability-06 982529 m, 10004 m/sec, 88185675 t fired, .
Time elapsed: 322 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 AGEF EXCL 100/198 5/5 DLCflexbar-PT-6a-CTLFireability-06 1033228 m, 10139 m/sec, 92780444 t fired, .
Time elapsed: 327 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 21 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 332 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 51 DLCflexbar-PT-6a-CTLFireability-13
lola: time limit : 204 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-13
lola: result : false
lola: markings : 2
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 DLCflexbar-PT-6a-CTLFireability-10
lola: time limit : 217 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-10
lola: result : false
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 31 DLCflexbar-PT-6a-CTLFireability-09
lola: time limit : 233 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 5/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 3169 m, 633 m/sec, 136087 t fired, .
Time elapsed: 337 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 10/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 8464 m, 1059 m/sec, 371923 t fired, .
Time elapsed: 342 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 15/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 13709 m, 1049 m/sec, 610147 t fired, .
Time elapsed: 347 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 20/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 19023 m, 1062 m/sec, 845133 t fired, .
Time elapsed: 352 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 25/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 24284 m, 1052 m/sec, 1085260 t fired, .
Time elapsed: 357 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 30/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 29580 m, 1059 m/sec, 1322073 t fired, .
Time elapsed: 362 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 35/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 34857 m, 1055 m/sec, 1561174 t fired, .
Time elapsed: 367 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 40/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 40128 m, 1054 m/sec, 1802176 t fired, .
Time elapsed: 372 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 45/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 45446 m, 1063 m/sec, 2037894 t fired, .
Time elapsed: 377 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 50/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 50735 m, 1057 m/sec, 2272338 t fired, .
Time elapsed: 382 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 55/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 56016 m, 1056 m/sec, 2507745 t fired, .
Time elapsed: 387 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 60/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 61333 m, 1063 m/sec, 2744182 t fired, .
Time elapsed: 392 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 65/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 66645 m, 1062 m/sec, 2981713 t fired, .
Time elapsed: 397 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 70/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 71941 m, 1059 m/sec, 3215879 t fired, .
Time elapsed: 402 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 75/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 77225 m, 1056 m/sec, 3453672 t fired, .
Time elapsed: 407 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 80/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 82533 m, 1061 m/sec, 3689831 t fired, .
Time elapsed: 412 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 85/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 87803 m, 1054 m/sec, 3928912 t fired, .
Time elapsed: 417 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 90/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 93117 m, 1062 m/sec, 4165102 t fired, .
Time elapsed: 422 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 95/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 98435 m, 1063 m/sec, 4403083 t fired, .
Time elapsed: 427 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 100/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 103750 m, 1063 m/sec, 4639573 t fired, .
Time elapsed: 432 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 105/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 109064 m, 1062 m/sec, 4878443 t fired, .
Time elapsed: 437 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 110/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 114369 m, 1061 m/sec, 5119762 t fired, .
Time elapsed: 442 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 115/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 119654 m, 1057 m/sec, 5360650 t fired, .
Time elapsed: 447 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 120/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 124876 m, 1044 m/sec, 5597991 t fired, .
Time elapsed: 452 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 125/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 129991 m, 1023 m/sec, 5832770 t fired, .
Time elapsed: 457 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 130/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 135161 m, 1034 m/sec, 6069997 t fired, .
Time elapsed: 462 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 135/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 140256 m, 1019 m/sec, 6305583 t fired, .
Time elapsed: 467 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 140/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 145381 m, 1025 m/sec, 6538581 t fired, .
Time elapsed: 472 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 145/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 150592 m, 1042 m/sec, 6771496 t fired, .
Time elapsed: 477 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 150/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 155860 m, 1053 m/sec, 7009754 t fired, .
Time elapsed: 482 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 155/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 161124 m, 1052 m/sec, 7245480 t fired, .
Time elapsed: 487 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 160/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 166320 m, 1039 m/sec, 7481854 t fired, .
Time elapsed: 492 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 165/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 171519 m, 1039 m/sec, 7710943 t fired, .
Time elapsed: 497 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 170/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 176820 m, 1060 m/sec, 7950436 t fired, .
Time elapsed: 502 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 175/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 182105 m, 1057 m/sec, 8186483 t fired, .
Time elapsed: 507 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 180/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 187244 m, 1027 m/sec, 8415588 t fired, .
Time elapsed: 512 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 185/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 192429 m, 1037 m/sec, 8649450 t fired, .
Time elapsed: 517 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 190/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 197629 m, 1040 m/sec, 8884038 t fired, .
Time elapsed: 522 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 195/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 202855 m, 1045 m/sec, 9116187 t fired, .
Time elapsed: 527 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 200/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 208016 m, 1032 m/sec, 9349376 t fired, .
Time elapsed: 532 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 205/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 213128 m, 1022 m/sec, 9585706 t fired, .
Time elapsed: 537 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 210/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 218309 m, 1036 m/sec, 9819991 t fired, .
Time elapsed: 542 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 215/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 223545 m, 1047 m/sec, 10053165 t fired, .
Time elapsed: 547 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 220/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 228810 m, 1053 m/sec, 10289164 t fired, .
Time elapsed: 552 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 225/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 234392 m, 1116 m/sec, 10547994 t fired, .
Time elapsed: 557 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 230/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 239605 m, 1042 m/sec, 10783172 t fired, .
Time elapsed: 562 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 36 (type EXCL) for DLCflexbar-PT-6a-CTLFireability-09 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 1 0 0 2 1 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 568 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 31 DLCflexbar-PT-6a-CTLFireability-09
lola: time limit : 233 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 36 (type EXCL) for 31 DLCflexbar-PT-6a-CTLFireability-09
lola: time limit : 3032 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 32497 m, 6499 m/sec, 1595677 t fired, .
36 CTL EXCL 5/3032 1/5 DLCflexbar-PT-6a-CTLFireability-09 1216 m, -47677 m/sec, 52100 t fired, .
Time elapsed: 573 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 78013 m, 9103 m/sec, 3961657 t fired, .
36 CTL EXCL 10/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 5911 m, 939 m/sec, 257633 t fired, .
Time elapsed: 578 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/233 1/32 DLCflexbar-PT-6a-CTLFireability-09 116930 m, 7783 m/sec, 5987060 t fired, .
36 CTL EXCL 15/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 10031 m, 824 m/sec, 443062 t fired, .
Time elapsed: 583 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 156931 m, 8000 m/sec, 8091583 t fired, .
36 CTL EXCL 20/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 14271 m, 848 m/sec, 634466 t fired, .
Time elapsed: 588 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 191966 m, 7007 m/sec, 9933845 t fired, .
36 CTL EXCL 25/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 18013 m, 748 m/sec, 800151 t fired, .
Time elapsed: 593 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/233 2/32 DLCflexbar-PT-6a-CTLFireability-09 222789 m, 6164 m/sec, 11544273 t fired, .
36 CTL EXCL 30/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 21320 m, 661 m/sec, 949823 t fired, .
Time elapsed: 598 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/233 3/32 DLCflexbar-PT-6a-CTLFireability-09 268643 m, 9170 m/sec, 13933855 t fired, .
36 CTL EXCL 35/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 26218 m, 979 m/sec, 1170828 t fired, .
Time elapsed: 603 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/233 3/32 DLCflexbar-PT-6a-CTLFireability-09 303084 m, 6888 m/sec, 15734047 t fired, .
36 CTL EXCL 40/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 29917 m, 739 m/sec, 1337330 t fired, .
Time elapsed: 608 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/233 3/32 DLCflexbar-PT-6a-CTLFireability-09 346024 m, 8588 m/sec, 17972728 t fired, .
36 CTL EXCL 45/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 34542 m, 925 m/sec, 1546830 t fired, .
Time elapsed: 613 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/233 3/32 DLCflexbar-PT-6a-CTLFireability-09 392038 m, 9202 m/sec, 20375056 t fired, .
36 CTL EXCL 50/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 39529 m, 997 m/sec, 1774281 t fired, .
Time elapsed: 618 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 55/233 4/32 DLCflexbar-PT-6a-CTLFireability-09 430508 m, 7694 m/sec, 22382492 t fired, .
36 CTL EXCL 55/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 43756 m, 845 m/sec, 1963310 t fired, .
Time elapsed: 623 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 60/233 4/32 DLCflexbar-PT-6a-CTLFireability-09 467841 m, 7466 m/sec, 24352271 t fired, .
36 CTL EXCL 60/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 47867 m, 822 m/sec, 2144621 t fired, .
Time elapsed: 628 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 65/233 4/32 DLCflexbar-PT-6a-CTLFireability-09 514654 m, 9362 m/sec, 26797998 t fired, .
36 CTL EXCL 65/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 52910 m, 1008 m/sec, 2370431 t fired, .
Time elapsed: 633 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 70/233 5/32 DLCflexbar-PT-6a-CTLFireability-09 552995 m, 7668 m/sec, 28801363 t fired, .
36 CTL EXCL 70/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 57093 m, 836 m/sec, 2556185 t fired, .
Time elapsed: 638 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 75/233 5/32 DLCflexbar-PT-6a-CTLFireability-09 592393 m, 7879 m/sec, 30856222 t fired, .
36 CTL EXCL 75/216 1/5 DLCflexbar-PT-6a-CTLFireability-09 61351 m, 851 m/sec, 2744994 t fired, .
Time elapsed: 643 secs. Pages in use: 10
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-6a-CTLFireability-10: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-13: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-6a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-6a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-05: F 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-06: CONJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-6a-CTLFireability-07: EFEG 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-09: CONJ 0 0 2 0 2 0 0 0
DLCflexbar-PT-6a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-6a-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 81/233 5/32 DLCflexbar-PT-6a-CTLFireability-09 614095 m, 4340 m/sec, 31985955 t fired, .
36 CTL EXCL 81//home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-6a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-6a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477100570"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-6a.tgz
mv DLCflexbar-PT-6a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;