fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r102-tall-167814477000554
Last Updated
May 14, 2023

About the Execution of LoLA for DLCflexbar-PT-5a

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16216.184 1291048.00 1403624.00 11376.20 ???????????????T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000554.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-5a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000554
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.2M
-rw-r--r-- 1 mcc users 8.2K Feb 25 16:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 25 16:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 16:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 25 18:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 110K Feb 25 18:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 17:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Feb 25 17:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 2.8M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-5a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678299116983

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-5a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-5a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCflexbar-PT-5a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678300408031

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 12 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 48 (type EXCL) for 6 DLCflexbar-PT-5a-CTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 4/224 1/32 DLCflexbar-PT-5a-CTLFireability-02 16637 m, 3327 m/sec, 2235062 t fired, .

Time elapsed: 18 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 9/224 1/32 DLCflexbar-PT-5a-CTLFireability-02 56800 m, 8032 m/sec, 7757379 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 14/224 1/32 DLCflexbar-PT-5a-CTLFireability-02 97372 m, 8114 m/sec, 13342066 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 19/224 1/32 DLCflexbar-PT-5a-CTLFireability-02 137377 m, 8001 m/sec, 18899546 t fired, .

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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 24/224 1/32 DLCflexbar-PT-5a-CTLFireability-02 176894 m, 7903 m/sec, 24413473 t fired, .

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DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 34/224 2/32 DLCflexbar-PT-5a-CTLFireability-02 255080 m, 7827 m/sec, 35400474 t fired, .

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DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 39/224 2/32 DLCflexbar-PT-5a-CTLFireability-02 293813 m, 7746 m/sec, 40844888 t fired, .

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DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 44/224 2/32 DLCflexbar-PT-5a-CTLFireability-02 332193 m, 7676 m/sec, 46291873 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 49/224 2/32 DLCflexbar-PT-5a-CTLFireability-02 370868 m, 7735 m/sec, 51770384 t fired, .

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DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 54/224 2/32 DLCflexbar-PT-5a-CTLFireability-02 409388 m, 7704 m/sec, 57205826 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 59/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 447702 m, 7662 m/sec, 62639233 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 64/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 485201 m, 7499 m/sec, 67975416 t fired, .

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DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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48 AGEF EXCL 69/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 522571 m, 7474 m/sec, 73334915 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 74/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 559709 m, 7427 m/sec, 78669659 t fired, .

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48 AGEF EXCL 79/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 596842 m, 7426 m/sec, 83988142 t fired, .

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48 AGEF EXCL 84/224 3/32 DLCflexbar-PT-5a-CTLFireability-02 634389 m, 7509 m/sec, 89373490 t fired, .

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48 AGEF EXCL 89/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 671564 m, 7435 m/sec, 94732845 t fired, .

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48 AGEF EXCL 94/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 709178 m, 7522 m/sec, 100090935 t fired, .

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48 AGEF EXCL 99/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 746849 m, 7534 m/sec, 105457042 t fired, .

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48 AGEF EXCL 104/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 785258 m, 7681 m/sec, 110905065 t fired, .

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48 AGEF EXCL 109/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 822351 m, 7418 m/sec, 116234939 t fired, .

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48 AGEF EXCL 114/224 4/32 DLCflexbar-PT-5a-CTLFireability-02 858509 m, 7231 m/sec, 121497797 t fired, .

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48 AGEF EXCL 119/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 894800 m, 7258 m/sec, 126751464 t fired, .

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48 AGEF EXCL 124/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 930958 m, 7231 m/sec, 132007197 t fired, .

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48 AGEF EXCL 129/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 967012 m, 7210 m/sec, 137237447 t fired, .

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48 AGEF EXCL 134/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 1004310 m, 7459 m/sec, 142625118 t fired, .

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48 AGEF EXCL 139/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 1041259 m, 7389 m/sec, 148005699 t fired, .

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48 AGEF EXCL 144/224 5/32 DLCflexbar-PT-5a-CTLFireability-02 1078442 m, 7436 m/sec, 153403027 t fired, .

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48 AGEF EXCL 149/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1116414 m, 7594 m/sec, 158847570 t fired, .

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48 AGEF EXCL 154/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1152834 m, 7284 m/sec, 164141906 t fired, .

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48 AGEF EXCL 159/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1189189 m, 7271 m/sec, 169418959 t fired, .

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48 AGEF EXCL 164/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1225753 m, 7312 m/sec, 174766090 t fired, .

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48 AGEF EXCL 169/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1262478 m, 7345 m/sec, 180123815 t fired, .

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48 AGEF EXCL 174/224 6/32 DLCflexbar-PT-5a-CTLFireability-02 1298857 m, 7275 m/sec, 185446728 t fired, .

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48 AGEF EXCL 179/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1335672 m, 7363 m/sec, 190768484 t fired, .

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48 AGEF EXCL 184/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1372809 m, 7427 m/sec, 196130851 t fired, .

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48 AGEF EXCL 189/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1409356 m, 7309 m/sec, 201425825 t fired, .

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48 AGEF EXCL 194/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1445203 m, 7169 m/sec, 206679124 t fired, .

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48 AGEF EXCL 199/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1480733 m, 7106 m/sec, 211880180 t fired, .

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48 AGEF EXCL 204/224 7/32 DLCflexbar-PT-5a-CTLFireability-02 1516244 m, 7102 m/sec, 217072281 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 209/224 8/32 DLCflexbar-PT-5a-CTLFireability-02 1551814 m, 7114 m/sec, 222301474 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 214/224 8/32 DLCflexbar-PT-5a-CTLFireability-02 1588101 m, 7257 m/sec, 227589894 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 219/224 8/32 DLCflexbar-PT-5a-CTLFireability-02 1624231 m, 7226 m/sec, 232893047 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 224/224 8/32 DLCflexbar-PT-5a-CTLFireability-02 1660275 m, 7208 m/sec, 238176029 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 0 0 1 1 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 5/223 1/5 DLCflexbar-PT-5a-CTLFireability-02 41096 m, -323835 m/sec, 5637705 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 10/223 1/5 DLCflexbar-PT-5a-CTLFireability-02 81825 m, 8145 m/sec, 11209178 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 15/223 1/5 DLCflexbar-PT-5a-CTLFireability-02 121892 m, 8013 m/sec, 16734821 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 20/223 1/5 DLCflexbar-PT-5a-CTLFireability-02 161209 m, 7863 m/sec, 22217479 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 25/223 1/5 DLCflexbar-PT-5a-CTLFireability-02 200065 m, 7771 m/sec, 27659852 t fired, .

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DLCflexbar-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 30/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 238390 m, 7665 m/sec, 33078934 t fired, .

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DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

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48 AGEF EXCL 35/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 277108 m, 7743 m/sec, 38508546 t fired, .

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DLCflexbar-PT-5a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 40/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 316130 m, 7804 m/sec, 44000916 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 1 0 1 0 0 0
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DLCflexbar-PT-5a-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 AGEF EXCL 45/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 354227 m, 7619 m/sec, 49416819 t fired, .

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48 AGEF EXCL 50/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 393000 m, 7754 m/sec, 54906015 t fired, .

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48 AGEF EXCL 55/223 2/5 DLCflexbar-PT-5a-CTLFireability-02 431641 m, 7728 m/sec, 60349665 t fired, .

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48 AGEF EXCL 60/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 469588 m, 7589 m/sec, 65751532 t fired, .

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48 AGEF EXCL 65/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 507254 m, 7533 m/sec, 71148851 t fired, .

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48 AGEF EXCL 70/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 545033 m, 7555 m/sec, 76558425 t fired, .

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48 AGEF EXCL 75/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 582162 m, 7425 m/sec, 81880898 t fired, .

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48 AGEF EXCL 80/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 618372 m, 7242 m/sec, 87079315 t fired, .

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48 AGEF EXCL 85/223 3/5 DLCflexbar-PT-5a-CTLFireability-02 654239 m, 7173 m/sec, 92235253 t fired, .

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48 AGEF EXCL 90/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 690007 m, 7153 m/sec, 97401317 t fired, .

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48 AGEF EXCL 95/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 726769 m, 7352 m/sec, 102581351 t fired, .

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48 AGEF EXCL 100/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 763446 m, 7335 m/sec, 107820091 t fired, .

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48 AGEF EXCL 105/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 799851 m, 7281 m/sec, 113010468 t fired, .

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48 AGEF EXCL 110/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 835710 m, 7171 m/sec, 118182603 t fired, .

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48 AGEF EXCL 115/223 4/5 DLCflexbar-PT-5a-CTLFireability-02 871018 m, 7061 m/sec, 123295469 t fired, .

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48 AGEF EXCL 120/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 906459 m, 7088 m/sec, 128419922 t fired, .

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48 AGEF EXCL 125/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 941570 m, 7022 m/sec, 133542420 t fired, .

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48 AGEF EXCL 130/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 977745 m, 7235 m/sec, 138775860 t fired, .

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48 AGEF EXCL 135/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 1014011 m, 7253 m/sec, 144021031 t fired, .

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48 AGEF EXCL 140/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 1049396 m, 7077 m/sec, 149199535 t fired, .

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48 AGEF EXCL 145/223 5/5 DLCflexbar-PT-5a-CTLFireability-02 1086357 m, 7392 m/sec, 154495687 t fired, .

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43 CTL EXCL 5/229 1/32 DLCflexbar-PT-5a-CTLFireability-14 101991 m, 20398 m/sec, 3602236 t fired, .

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43 CTL EXCL 10/229 2/32 DLCflexbar-PT-5a-CTLFireability-14 208107 m, 21223 m/sec, 7245004 t fired, .

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43 CTL EXCL 15/229 2/32 DLCflexbar-PT-5a-CTLFireability-14 324731 m, 23324 m/sec, 10860538 t fired, .

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43 CTL EXCL 20/229 3/32 DLCflexbar-PT-5a-CTLFireability-14 436790 m, 22411 m/sec, 14460883 t fired, .

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43 CTL EXCL 25/229 4/32 DLCflexbar-PT-5a-CTLFireability-14 544606 m, 21563 m/sec, 18050210 t fired, .

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43 CTL EXCL 30/229 4/32 DLCflexbar-PT-5a-CTLFireability-14 647549 m, 20588 m/sec, 21626515 t fired, .

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43 CTL EXCL 35/229 5/32 DLCflexbar-PT-5a-CTLFireability-14 753490 m, 21188 m/sec, 25203912 t fired, .

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43 CTL EXCL 40/229 6/32 DLCflexbar-PT-5a-CTLFireability-14 872440 m, 23790 m/sec, 28748755 t fired, .

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43 CTL EXCL 45/229 7/32 DLCflexbar-PT-5a-CTLFireability-14 984513 m, 22414 m/sec, 32258494 t fired, .

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43 CTL EXCL 50/229 7/32 DLCflexbar-PT-5a-CTLFireability-14 1092774 m, 21652 m/sec, 35787858 t fired, .

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43 CTL EXCL 55/229 8/32 DLCflexbar-PT-5a-CTLFireability-14 1208659 m, 23177 m/sec, 39316263 t fired, .

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43 CTL EXCL 60/229 9/32 DLCflexbar-PT-5a-CTLFireability-14 1325909 m, 23450 m/sec, 42834602 t fired, .

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43 CTL EXCL 65/229 9/32 DLCflexbar-PT-5a-CTLFireability-14 1438963 m, 22610 m/sec, 46301157 t fired, .

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43 CTL EXCL 70/229 10/32 DLCflexbar-PT-5a-CTLFireability-14 1551993 m, 22606 m/sec, 49776346 t fired, .

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43 CTL EXCL 75/229 11/32 DLCflexbar-PT-5a-CTLFireability-14 1661213 m, 21844 m/sec, 53249823 t fired, .

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43 CTL EXCL 80/229 11/32 DLCflexbar-PT-5a-CTLFireability-14 1774268 m, 22611 m/sec, 56697214 t fired, .

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43 CTL EXCL 85/229 12/32 DLCflexbar-PT-5a-CTLFireability-14 1885134 m, 22173 m/sec, 60163372 t fired, .

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43 CTL EXCL 90/229 13/32 DLCflexbar-PT-5a-CTLFireability-14 2004232 m, 23819 m/sec, 63612016 t fired, .

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43 CTL EXCL 95/229 13/32 DLCflexbar-PT-5a-CTLFireability-14 2114470 m, 22047 m/sec, 67052895 t fired, .

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43 CTL EXCL 100/229 14/32 DLCflexbar-PT-5a-CTLFireability-14 2227979 m, 22701 m/sec, 70482891 t fired, .

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43 CTL EXCL 105/229 15/32 DLCflexbar-PT-5a-CTLFireability-14 2343524 m, 23109 m/sec, 73955218 t fired, .

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43 CTL EXCL 110/229 16/32 DLCflexbar-PT-5a-CTLFireability-14 2454928 m, 22280 m/sec, 77420932 t fired, .

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43 CTL EXCL 115/229 16/32 DLCflexbar-PT-5a-CTLFireability-14 2568480 m, 22710 m/sec, 80858339 t fired, .

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43 CTL EXCL 120/229 17/32 DLCflexbar-PT-5a-CTLFireability-14 2668360 m, 19976 m/sec, 84308209 t fired, .

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43 CTL EXCL 125/229 17/32 DLCflexbar-PT-5a-CTLFireability-14 2776242 m, 21576 m/sec, 87725685 t fired, .

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43 CTL EXCL 130/229 18/32 DLCflexbar-PT-5a-CTLFireability-14 2885476 m, 21846 m/sec, 91145531 t fired, .

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43 CTL EXCL 135/229 19/32 DLCflexbar-PT-5a-CTLFireability-14 2989522 m, 20809 m/sec, 94567456 t fired, .

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43 CTL EXCL 140/229 19/32 DLCflexbar-PT-5a-CTLFireability-14 3101257 m, 22347 m/sec, 97993099 t fired, .

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43 CTL EXCL 145/229 20/32 DLCflexbar-PT-5a-CTLFireability-14 3206618 m, 21072 m/sec, 101445796 t fired, .

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43 CTL EXCL 150/229 21/32 DLCflexbar-PT-5a-CTLFireability-14 3313633 m, 21403 m/sec, 104886330 t fired, .

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43 CTL EXCL 155/229 21/32 DLCflexbar-PT-5a-CTLFireability-14 3419142 m, 21101 m/sec, 108316319 t fired, .

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43 CTL EXCL 160/229 22/32 DLCflexbar-PT-5a-CTLFireability-14 3523377 m, 20847 m/sec, 111766663 t fired, .

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43 CTL EXCL 165/229 23/32 DLCflexbar-PT-5a-CTLFireability-14 3626878 m, 20700 m/sec, 115201808 t fired, .

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43 CTL EXCL 170/229 23/32 DLCflexbar-PT-5a-CTLFireability-14 3732376 m, 21099 m/sec, 118629731 t fired, .

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43 CTL EXCL 175/229 24/32 DLCflexbar-PT-5a-CTLFireability-14 3833322 m, 20189 m/sec, 122102634 t fired, .

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43 CTL EXCL 180/229 25/32 DLCflexbar-PT-5a-CTLFireability-14 3937806 m, 20896 m/sec, 125503502 t fired, .

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43 CTL EXCL 185/229 25/32 DLCflexbar-PT-5a-CTLFireability-14 4039800 m, 20398 m/sec, 128969604 t fired, .

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43 CTL EXCL 190/229 26/32 DLCflexbar-PT-5a-CTLFireability-14 4141661 m, 20372 m/sec, 132440018 t fired, .

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43 CTL EXCL 195/229 27/32 DLCflexbar-PT-5a-CTLFireability-14 4263089 m, 24285 m/sec, 135898661 t fired, .

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43 CTL EXCL 200/229 27/32 DLCflexbar-PT-5a-CTLFireability-14 4365548 m, 20491 m/sec, 139318957 t fired, .

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43 CTL EXCL 205/229 28/32 DLCflexbar-PT-5a-CTLFireability-14 4465875 m, 20065 m/sec, 142735824 t fired, .

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43 CTL EXCL 210/229 28/32 DLCflexbar-PT-5a-CTLFireability-14 4576452 m, 22115 m/sec, 146171195 t fired, .

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43 CTL EXCL 225/229 31/32 DLCflexbar-PT-5a-CTLFireability-14 4954974 m, 22106 m/sec, 156552573 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 0 0 1 0 1 0
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DLCflexbar-PT-5a-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-5a-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/229 1/32 DLCflexbar-PT-5a-CTLFireability-13 98969 m, 19793 m/sec, 3496785 t fired, .
43 CTL EXCL 4/2977 1/5 DLCflexbar-PT-5a-CTLFireability-14 99244 m, -971146 m/sec, 3513732 t fired, .

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DLCflexbar-PT-5a-CTLFireability-02: EFAG 0 0 0 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/229 2/32 DLCflexbar-PT-5a-CTLFireability-13 203712 m, 20948 m/sec, 7087061 t fired, .
43 CTL EXCL 9/212 2/5 DLCflexbar-PT-5a-CTLFireability-14 203030 m, 20757 m/sec, 7071250 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/229 2/32 DLCflexbar-PT-5a-CTLFireability-13 317540 m, 22765 m/sec, 10648448 t fired, .
43 CTL EXCL 14/212 2/5 DLCflexbar-PT-5a-CTLFireability-14 314909 m, 22375 m/sec, 10591230 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/229 3/32 DLCflexbar-PT-5a-CTLFireability-13 428132 m, 22118 m/sec, 14182414 t fired, .
43 CTL EXCL 19/212 3/5 DLCflexbar-PT-5a-CTLFireability-14 425795 m, 22177 m/sec, 14093609 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/229 4/32 DLCflexbar-PT-5a-CTLFireability-13 535754 m, 21524 m/sec, 17711458 t fired, .
43 CTL EXCL 24/212 4/5 DLCflexbar-PT-5a-CTLFireability-14 531508 m, 21142 m/sec, 17583141 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 30/229 4/32 DLCflexbar-PT-5a-CTLFireability-13 636369 m, 20123 m/sec, 21236516 t fired, .
43 CTL EXCL 29/212 4/5 DLCflexbar-PT-5a-CTLFireability-14 631689 m, 20036 m/sec, 21065454 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 35/229 5/32 DLCflexbar-PT-5a-CTLFireability-13 740535 m, 20833 m/sec, 24764751 t fired, .
43 CTL EXCL 34/212 5/5 DLCflexbar-PT-5a-CTLFireability-14 733919 m, 20446 m/sec, 24548469 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 40/229 6/32 DLCflexbar-PT-5a-CTLFireability-13 856101 m, 23113 m/sec, 28272921 t fired, .

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40 CTL EXCL 45/229 6/32 DLCflexbar-PT-5a-CTLFireability-13 971846 m, 23149 m/sec, 31766042 t fired, .

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40 CTL EXCL 50/229 7/32 DLCflexbar-PT-5a-CTLFireability-13 1078695 m, 21369 m/sec, 35275657 t fired, .

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40 CTL EXCL 55/229 8/32 DLCflexbar-PT-5a-CTLFireability-13 1190993 m, 22459 m/sec, 38775498 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 60/229 8/32 DLCflexbar-PT-5a-CTLFireability-13 1307570 m, 23315 m/sec, 42265076 t fired, .

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40 CTL EXCL 70/229 10/32 DLCflexbar-PT-5a-CTLFireability-13 1535841 m, 22812 m/sec, 49233011 t fired, .

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40 CTL EXCL 75/229 11/32 DLCflexbar-PT-5a-CTLFireability-13 1644249 m, 21681 m/sec, 52724316 t fired, .

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40 CTL EXCL 80/229 11/32 DLCflexbar-PT-5a-CTLFireability-13 1759866 m, 23123 m/sec, 56198061 t fired, .

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40 CTL EXCL 85/229 12/32 DLCflexbar-PT-5a-CTLFireability-13 1868889 m, 21804 m/sec, 59686899 t fired, .

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40 CTL EXCL 90/229 13/32 DLCflexbar-PT-5a-CTLFireability-13 1987699 m, 23762 m/sec, 63148478 t fired, .

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40 CTL EXCL 96/229 13/32 DLCflexbar-PT-5a-CTLFireability-13 2101116 m, 22683 m/sec, 66599133 t fired, .

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40 CTL EXCL 101/229 14/32 DLCflexbar-PT-5a-CTLFireability-13 2212877 m, 22352 m/sec, 70045941 t fired, .

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40 CTL EXCL 106/229 15/32 DLCflexbar-PT-5a-CTLFireability-13 2327750 m, 22974 m/sec, 73501266 t fired, .

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40 CTL EXCL 111/229 15/32 DLCflexbar-PT-5a-CTLFireability-13 2440245 m, 22499 m/sec, 76970753 t fired, .

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40 CTL EXCL 116/229 16/32 DLCflexbar-PT-5a-CTLFireability-13 2555005 m, 22952 m/sec, 80431086 t fired, .

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40 CTL EXCL 121/229 17/32 DLCflexbar-PT-5a-CTLFireability-13 2656210 m, 20241 m/sec, 83907508 t fired, .

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40 CTL EXCL 126/229 17/32 DLCflexbar-PT-5a-CTLFireability-13 2765083 m, 21774 m/sec, 87367889 t fired, .

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40 CTL EXCL 131/229 18/32 DLCflexbar-PT-5a-CTLFireability-13 2874877 m, 21958 m/sec, 90814208 t fired, .

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40 CTL EXCL 136/229 19/32 DLCflexbar-PT-5a-CTLFireability-13 2979726 m, 20969 m/sec, 94262417 t fired, .

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40 CTL EXCL 141/229 19/32 DLCflexbar-PT-5a-CTLFireability-13 3092230 m, 22500 m/sec, 97722270 t fired, .

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40 CTL EXCL 146/229 20/32 DLCflexbar-PT-5a-CTLFireability-13 3198029 m, 21159 m/sec, 101189457 t fired, .

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40 CTL EXCL 151/229 21/32 DLCflexbar-PT-5a-CTLFireability-13 3306842 m, 21762 m/sec, 104652452 t fired, .

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40 CTL EXCL 156/229 21/32 DLCflexbar-PT-5a-CTLFireability-13 3410820 m, 20795 m/sec, 108112566 t fired, .

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40 CTL EXCL 161/229 22/32 DLCflexbar-PT-5a-CTLFireability-13 3517344 m, 21304 m/sec, 111565290 t fired, .

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40 CTL EXCL 166/229 23/32 DLCflexbar-PT-5a-CTLFireability-13 3621102 m, 20751 m/sec, 115013095 t fired, .

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40 CTL EXCL 171/229 23/32 DLCflexbar-PT-5a-CTLFireability-13 3727455 m, 21270 m/sec, 118460781 t fired, .

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40 CTL EXCL 176/229 24/32 DLCflexbar-PT-5a-CTLFireability-13 3827782 m, 20065 m/sec, 121925902 t fired, .

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40 CTL EXCL 181/229 25/32 DLCflexbar-PT-5a-CTLFireability-13 3934507 m, 21345 m/sec, 125370536 t fired, .

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40 CTL EXCL 186/229 25/32 DLCflexbar-PT-5a-CTLFireability-13 4035766 m, 20251 m/sec, 128826360 t fired, .

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40 CTL EXCL 191/229 26/32 DLCflexbar-PT-5a-CTLFireability-13 4135729 m, 19992 m/sec, 132280568 t fired, .

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40 CTL EXCL 196/229 27/32 DLCflexbar-PT-5a-CTLFireability-13 4259589 m, 24772 m/sec, 135776412 t fired, .

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40 CTL EXCL 201/229 27/32 DLCflexbar-PT-5a-CTLFireability-13 4362857 m, 20653 m/sec, 139220870 t fired, .

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40 CTL EXCL 206/229 28/32 DLCflexbar-PT-5a-CTLFireability-13 4463303 m, 20089 m/sec, 142652037 t fired, .

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40 CTL EXCL 211/229 28/32 DLCflexbar-PT-5a-CTLFireability-13 4573851 m, 22109 m/sec, 146108298 t fired, .

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40 CTL EXCL 216/229 29/32 DLCflexbar-PT-5a-CTLFireability-13 4710142 m, 27258 m/sec, 149623456 t fired, .

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40 CTL EXCL 221/229 30/32 DLCflexbar-PT-5a-CTLFireability-13 4844404 m, 26852 m/sec, 153106156 t fired, .

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40 CTL EXCL 226/229 31/32 DLCflexbar-PT-5a-CTLFireability-13 4955725 m, 22264 m/sec, 156574304 t fired, .

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37 CTL EXCL 5/228 1/32 DLCflexbar-PT-5a-CTLFireability-12 117486 m, 23497 m/sec, 3414113 t fired, .
40 CTL EXCL 5/2746 1/5 DLCflexbar-PT-5a-CTLFireability-13 101444 m, -970856 m/sec, 3583246 t fired, .

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37 CTL EXCL 10/228 2/32 DLCflexbar-PT-5a-CTLFireability-12 234138 m, 23330 m/sec, 6814611 t fired, .
40 CTL EXCL 10/211 2/5 DLCflexbar-PT-5a-CTLFireability-13 205818 m, 20874 m/sec, 7151116 t fired, .

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37 CTL EXCL 15/228 3/32 DLCflexbar-PT-5a-CTLFireability-12 356354 m, 24443 m/sec, 10189786 t fired, .
40 CTL EXCL 15/211 2/5 DLCflexbar-PT-5a-CTLFireability-13 318998 m, 22636 m/sec, 10690623 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/228 3/32 DLCflexbar-PT-5a-CTLFireability-12 483274 m, 25384 m/sec, 13554962 t fired, .
40 CTL EXCL 20/211 3/5 DLCflexbar-PT-5a-CTLFireability-13 429173 m, 22035 m/sec, 14212177 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/228 4/32 DLCflexbar-PT-5a-CTLFireability-12 603048 m, 23954 m/sec, 16902763 t fired, .
40 CTL EXCL 25/211 4/5 DLCflexbar-PT-5a-CTLFireability-13 535886 m, 21342 m/sec, 17719366 t fired, .

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37 CTL EXCL 30/228 5/32 DLCflexbar-PT-5a-CTLFireability-12 719664 m, 23323 m/sec, 20237121 t fired, .
40 CTL EXCL 30/211 4/5 DLCflexbar-PT-5a-CTLFireability-13 636010 m, 20024 m/sec, 21222872 t fired, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/228 5/32 DLCflexbar-PT-5a-CTLFireability-12 835818 m, 23230 m/sec, 23589880 t fired, .
40 CTL EXCL 35/211 5/5 DLCflexbar-PT-5a-CTLFireability-13 739718 m, 20741 m/sec, 24732891 t fired, .

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37 CTL EXCL 40/228 6/32 DLCflexbar-PT-5a-CTLFireability-12 951848 m, 23206 m/sec, 26937399 t fired, .

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37 CTL EXCL 45/228 7/32 DLCflexbar-PT-5a-CTLFireability-12 1080626 m, 25755 m/sec, 30221844 t fired, .

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37 CTL EXCL 50/228 8/32 DLCflexbar-PT-5a-CTLFireability-12 1205251 m, 24925 m/sec, 33542355 t fired, .

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37 CTL EXCL 55/228 8/32 DLCflexbar-PT-5a-CTLFireability-12 1326560 m, 24261 m/sec, 36889957 t fired, .

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37 CTL EXCL 60/228 9/32 DLCflexbar-PT-5a-CTLFireability-12 1450042 m, 24696 m/sec, 40202807 t fired, .

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37 CTL EXCL 65/228 10/32 DLCflexbar-PT-5a-CTLFireability-12 1576238 m, 25239 m/sec, 43516620 t fired, .

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37 CTL EXCL 70/228 11/32 DLCflexbar-PT-5a-CTLFireability-12 1701062 m, 24964 m/sec, 46822363 t fired, .

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37 CTL EXCL 75/228 11/32 DLCflexbar-PT-5a-CTLFireability-12 1824578 m, 24703 m/sec, 50133804 t fired, .

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37 CTL EXCL 80/228 12/32 DLCflexbar-PT-5a-CTLFireability-12 1947452 m, 24574 m/sec, 53442110 t fired, .

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37 CTL EXCL 85/228 13/32 DLCflexbar-PT-5a-CTLFireability-12 2072828 m, 25075 m/sec, 56723777 t fired, .

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37 CTL EXCL 90/228 13/32 DLCflexbar-PT-5a-CTLFireability-12 2190810 m, 23596 m/sec, 59998993 t fired, .

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37 CTL EXCL 95/228 14/32 DLCflexbar-PT-5a-CTLFireability-12 2315108 m, 24859 m/sec, 63325396 t fired, .

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37 CTL EXCL 100/228 15/32 DLCflexbar-PT-5a-CTLFireability-12 2445526 m, 26083 m/sec, 66587418 t fired, .

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37 CTL EXCL 105/228 16/32 DLCflexbar-PT-5a-CTLFireability-12 2568238 m, 24542 m/sec, 69898556 t fired, .

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37 CTL EXCL 110/228 16/32 DLCflexbar-PT-5a-CTLFireability-12 2691752 m, 24702 m/sec, 73170298 t fired, .

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37 CTL EXCL 115/228 17/32 DLCflexbar-PT-5a-CTLFireability-12 2820208 m, 25691 m/sec, 76531443 t fired, .

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37 CTL EXCL 120/228 18/32 DLCflexbar-PT-5a-CTLFireability-12 2942768 m, 24512 m/sec, 79819842 t fired, .

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37 CTL EXCL 125/228 19/32 DLCflexbar-PT-5a-CTLFireability-12 3069553 m, 25357 m/sec, 83113554 t fired, .

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37 CTL EXCL 130/228 19/32 DLCflexbar-PT-5a-CTLFireability-12 3185552 m, 23199 m/sec, 86394320 t fired, .

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37 CTL EXCL 135/228 20/32 DLCflexbar-PT-5a-CTLFireability-12 3302076 m, 23304 m/sec, 89678466 t fired, .

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37 CTL EXCL 140/228 21/32 DLCflexbar-PT-5a-CTLFireability-12 3423732 m, 24331 m/sec, 92963178 t fired, .

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37 CTL EXCL 145/228 21/32 DLCflexbar-PT-5a-CTLFireability-12 3543418 m, 23937 m/sec, 96246556 t fired, .

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37 CTL EXCL 150/228 22/32 DLCflexbar-PT-5a-CTLFireability-12 3659310 m, 23178 m/sec, 99511022 t fired, .

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37 CTL EXCL 155/228 23/32 DLCflexbar-PT-5a-CTLFireability-12 3782760 m, 24690 m/sec, 102793509 t fired, .

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37 CTL EXCL 160/228 24/32 DLCflexbar-PT-5a-CTLFireability-12 3899629 m, 23373 m/sec, 106079097 t fired, .

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37 CTL EXCL 165/228 24/32 DLCflexbar-PT-5a-CTLFireability-12 4018350 m, 23744 m/sec, 109363548 t fired, .

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37 CTL EXCL 180/228 26/32 DLCflexbar-PT-5a-CTLFireability-12 4368319 m, 23041 m/sec, 119206556 t fired, .

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37 CTL EXCL 190/228 28/32 DLCflexbar-PT-5a-CTLFireability-12 4598174 m, 22363 m/sec, 125789262 t fired, .

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34 CTL EXCL 10/228 2/32 DLCflexbar-PT-5a-CTLFireability-11 197848 m, 19952 m/sec, 7116889 t fired, .

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34 CTL EXCL 15/228 2/32 DLCflexbar-PT-5a-CTLFireability-11 304529 m, 21336 m/sec, 10630208 t fired, .

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34 CTL EXCL 20/228 3/32 DLCflexbar-PT-5a-CTLFireability-11 413523 m, 21798 m/sec, 14112583 t fired, .

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34 CTL EXCL 25/228 4/32 DLCflexbar-PT-5a-CTLFireability-11 516031 m, 20501 m/sec, 17596713 t fired, .

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34 CTL EXCL 30/228 4/32 DLCflexbar-PT-5a-CTLFireability-11 613586 m, 19511 m/sec, 21071292 t fired, .

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34 CTL EXCL 35/228 5/32 DLCflexbar-PT-5a-CTLFireability-11 711005 m, 19483 m/sec, 24527294 t fired, .

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34 CTL EXCL 40/228 5/32 DLCflexbar-PT-5a-CTLFireability-11 814947 m, 20788 m/sec, 27995084 t fired, .

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34 CTL EXCL 45/228 6/32 DLCflexbar-PT-5a-CTLFireability-11 931869 m, 23384 m/sec, 31415913 t fired, .

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34 CTL EXCL 50/228 7/32 DLCflexbar-PT-5a-CTLFireability-11 1030527 m, 19731 m/sec, 34852429 t fired, .

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34 CTL EXCL 55/228 7/32 DLCflexbar-PT-5a-CTLFireability-11 1140591 m, 22012 m/sec, 38290604 t fired, .

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34 CTL EXCL 60/228 8/32 DLCflexbar-PT-5a-CTLFireability-11 1250869 m, 22055 m/sec, 41706123 t fired, .

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34 CTL EXCL 65/228 9/32 DLCflexbar-PT-5a-CTLFireability-11 1356438 m, 21113 m/sec, 45137227 t fired, .

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34 CTL EXCL 70/228 9/32 DLCflexbar-PT-5a-CTLFireability-11 1464953 m, 21703 m/sec, 48549817 t fired, .

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34 CTL EXCL 75/228 10/32 DLCflexbar-PT-5a-CTLFireability-11 1572799 m, 21569 m/sec, 51961881 t fired, .

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34 CTL EXCL 80/228 11/32 DLCflexbar-PT-5a-CTLFireability-11 1676472 m, 20734 m/sec, 55387673 t fired, .

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34 CTL EXCL 85/228 11/32 DLCflexbar-PT-5a-CTLFireability-11 1782784 m, 21262 m/sec, 58791768 t fired, .

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34 CTL EXCL 90/228 12/32 DLCflexbar-PT-5a-CTLFireability-11 1889705 m, 21384 m/sec, 62209949 t fired, .

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34 CTL EXCL 95/228 13/32 DLCflexbar-PT-5a-CTLFireability-11 2003955 m, 22850 m/sec, 65610963 t fired, .

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34 CTL EXCL 100/228 13/32 DLCflexbar-PT-5a-CTLFireability-11 2109096 m, 21028 m/sec, 69002893 t fired, .

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34 CTL EXCL 105/228 14/32 DLCflexbar-PT-5a-CTLFireability-11 2216891 m, 21559 m/sec, 72399069 t fired, .

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34 CTL EXCL 110/228 15/32 DLCflexbar-PT-5a-CTLFireability-11 2326243 m, 21870 m/sec, 75784223 t fired, .

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34 CTL EXCL 115/228 15/32 DLCflexbar-PT-5a-CTLFireability-11 2433112 m, 21373 m/sec, 79192337 t fired, .

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34 CTL EXCL 120/228 16/32 DLCflexbar-PT-5a-CTLFireability-11 2543249 m, 22027 m/sec, 82585751 t fired, .

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34 CTL EXCL 125/228 17/32 DLCflexbar-PT-5a-CTLFireability-11 2638545 m, 19059 m/sec, 85969381 t fired, .

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34 CTL EXCL 130/228 17/32 DLCflexbar-PT-5a-CTLFireability-11 2741077 m, 20506 m/sec, 89363846 t fired, .

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34 CTL EXCL 135/228 18/32 DLCflexbar-PT-5a-CTLFireability-11 2844622 m, 20709 m/sec, 92689524 t fired, .

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34 CTL EXCL 140/228 19/32 DLCflexbar-PT-5a-CTLFireability-11 2944988 m, 20073 m/sec, 96003506 t fired, .

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34 CTL EXCL 160/228 21/32 DLCflexbar-PT-5a-CTLFireability-11 3347005 m, 20023 m/sec, 109424131 t fired, .

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34 CTL EXCL 165/228 22/32 DLCflexbar-PT-5a-CTLFireability-11 3450168 m, 20632 m/sec, 112832711 t fired, .

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34 CTL EXCL 170/228 22/32 DLCflexbar-PT-5a-CTLFireability-11 3551486 m, 20263 m/sec, 116221097 t fired, .

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34 CTL EXCL 175/228 23/32 DLCflexbar-PT-5a-CTLFireability-11 3651500 m, 20002 m/sec, 119622769 t fired, .

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34 CTL EXCL 180/228 23/32 DLCflexbar-PT-5a-CTLFireability-11 3749190 m, 19538 m/sec, 123013022 t fired, .

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-5a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-5a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000554"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-5a.tgz
mv DLCflexbar-PT-5a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;