About the Execution of LoLA for DLCflexbar-PT-4b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16227.252 | 352823.00 | 612549.00 | 22830.00 | ?T??T?T????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000546.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-4b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000546
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.6M
-rw-r--r-- 1 mcc users 8.6K Feb 25 14:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 25 14:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 14:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Feb 25 14:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 25 14:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 14:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 14:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 4.1M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-4b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678298263874
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-4b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-4b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCflexbar-PT-4b-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4b-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-4b-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678298616697
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 62 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 67 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 72 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 77 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 82 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 87 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 92 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 97 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 11.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 107 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 112 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 117 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 122 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 127 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 132 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-01: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-04: EG 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-06: DISJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 137 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 9.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 61 (type EXCL) for 3 DLCflexbar-PT-4b-CTLFireability-01
lola: time limit : 192 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 59 (type FNDP) for 3 DLCflexbar-PT-4b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 3 DLCflexbar-PT-4b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 3 DLCflexbar-PT-4b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 61 (type EXCL) for DLCflexbar-PT-4b-CTLFireability-01
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 59 (type FNDP) for DLCflexbar-PT-4b-CTLFireability-01 (obsolete)
lola: CANCELED task # 60 (type EQUN) for DLCflexbar-PT-4b-CTLFireability-01 (obsolete)
lola: CANCELED task # 62 (type SRCH) for DLCflexbar-PT-4b-CTLFireability-01 (obsolete)
lola: LAUNCH task # 58 (type EXCL) for 18 DLCflexbar-PT-4b-CTLFireability-06
lola: time limit : 203 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 56 (type FNDP) for 18 DLCflexbar-PT-4b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 18 DLCflexbar-PT-4b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SRCH) for 18 DLCflexbar-PT-4b-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type FNDP) for DLCflexbar-PT-4b-CTLFireability-01
lola: result : unknown
lola: fired transitions : 1
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 62 (type SRCH) for DLCflexbar-PT-4b-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 58 (type EXCL) for DLCflexbar-PT-4b-CTLFireability-06
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 56 (type FNDP) for DLCflexbar-PT-4b-CTLFireability-06 (obsolete)
lola: CANCELED task # 57 (type EQUN) for DLCflexbar-PT-4b-CTLFireability-06 (obsolete)
lola: CANCELED task # 63 (type SRCH) for DLCflexbar-PT-4b-CTLFireability-06 (obsolete)
lola: LAUNCH task # 13 (type EXCL) for 12 DLCflexbar-PT-4b-CTLFireability-04
lola: time limit : 230 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-60.sara.
lola: FINISHED task # 60 (type EQUN) for DLCflexbar-PT-4b-CTLFireability-01
lola: result : true
lola: FINISHED task # 56 (type FNDP) for DLCflexbar-PT-4b-CTLFireability-06
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-57.sara.
lola: FINISHED task # 57 (type EQUN) for DLCflexbar-PT-4b-CTLFireability-06
lola: result : true
lola: FINISHED task # 13 (type EXCL) for DLCflexbar-PT-4b-CTLFireability-04
lola: result : true
lola: markings : 561
lola: fired transitions : 561
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 DLCflexbar-PT-4b-CTLFireability-11
lola: time limit : 247 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 3/247 1/32 DLCflexbar-PT-4b-CTLFireability-11 15023 m, 3004 m/sec, 117798 t fired, .
Time elapsed: 142 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 8/247 1/32 DLCflexbar-PT-4b-CTLFireability-11 49257 m, 6846 m/sec, 366575 t fired, .
Time elapsed: 147 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 13/247 1/32 DLCflexbar-PT-4b-CTLFireability-11 81344 m, 6417 m/sec, 603935 t fired, .
Time elapsed: 152 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: planning for (null) stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 18/247 1/32 DLCflexbar-PT-4b-CTLFireability-11 110741 m, 5879 m/sec, 828254 t fired, .
Time elapsed: 157 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 23/247 2/32 DLCflexbar-PT-4b-CTLFireability-11 133686 m, 4589 m/sec, 1004726 t fired, .
Time elapsed: 162 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 28/247 2/32 DLCflexbar-PT-4b-CTLFireability-11 167605 m, 6783 m/sec, 1269704 t fired, .
Time elapsed: 167 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 33/247 2/32 DLCflexbar-PT-4b-CTLFireability-11 203341 m, 7147 m/sec, 1547908 t fired, .
Time elapsed: 172 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 38/247 2/32 DLCflexbar-PT-4b-CTLFireability-11 238563 m, 7044 m/sec, 1816591 t fired, .
Time elapsed: 177 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 43/247 3/32 DLCflexbar-PT-4b-CTLFireability-11 269431 m, 6173 m/sec, 2059245 t fired, .
Time elapsed: 182 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 48/247 3/32 DLCflexbar-PT-4b-CTLFireability-11 302093 m, 6532 m/sec, 2308178 t fired, .
Time elapsed: 187 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 53/247 3/32 DLCflexbar-PT-4b-CTLFireability-11 334478 m, 6477 m/sec, 2566346 t fired, .
Time elapsed: 192 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 0 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 58/247 3/32 DLCflexbar-PT-4b-CTLFireability-11 366890 m, 6482 m/sec, 2828197 t fired, .
Time elapsed: 197 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 1 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 63/247 4/32 DLCflexbar-PT-4b-CTLFireability-11 403731 m, 7368 m/sec, 3113087 t fired, .
Time elapsed: 202 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 70/247 4/32 DLCflexbar-PT-4b-CTLFireability-11 447186 m, 8691 m/sec, 3454927 t fired, .
Time elapsed: 209 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 77/247 4/32 DLCflexbar-PT-4b-CTLFireability-11 508168 m, 12196 m/sec, 3922460 t fired, .
Time elapsed: 216 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 82/247 5/32 DLCflexbar-PT-4b-CTLFireability-11 597675 m, 17901 m/sec, 4605468 t fired, .
Time elapsed: 221 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 87/247 6/32 DLCflexbar-PT-4b-CTLFireability-11 657927 m, 12050 m/sec, 5073871 t fired, .
Time elapsed: 226 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 92/247 6/32 DLCflexbar-PT-4b-CTLFireability-11 753310 m, 19076 m/sec, 5830607 t fired, .
Time elapsed: 231 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 97/247 7/32 DLCflexbar-PT-4b-CTLFireability-11 851818 m, 19701 m/sec, 6615203 t fired, .
Time elapsed: 236 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 102/247 8/32 DLCflexbar-PT-4b-CTLFireability-11 916369 m, 12910 m/sec, 7124338 t fired, .
Time elapsed: 241 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 107/247 8/32 DLCflexbar-PT-4b-CTLFireability-11 967117 m, 10149 m/sec, 7528340 t fired, .
Time elapsed: 246 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 112/247 8/32 DLCflexbar-PT-4b-CTLFireability-11 1034128 m, 13402 m/sec, 8070177 t fired, .
Time elapsed: 251 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 117/247 9/32 DLCflexbar-PT-4b-CTLFireability-11 1087194 m, 10613 m/sec, 8494175 t fired, .
Time elapsed: 256 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 122/247 9/32 DLCflexbar-PT-4b-CTLFireability-11 1160285 m, 14618 m/sec, 9073051 t fired, .
Time elapsed: 261 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 127/247 10/32 DLCflexbar-PT-4b-CTLFireability-11 1199952 m, 7933 m/sec, 9386914 t fired, .
Time elapsed: 266 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 132/247 11/32 DLCflexbar-PT-4b-CTLFireability-11 1299010 m, 19811 m/sec, 10136428 t fired, .
Time elapsed: 271 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 137/247 11/32 DLCflexbar-PT-4b-CTLFireability-11 1319508 m, 4099 m/sec, 10298673 t fired, .
Time elapsed: 276 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 142/247 12/32 DLCflexbar-PT-4b-CTLFireability-11 1428369 m, 21772 m/sec, 11149542 t fired, .
Time elapsed: 281 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 147/247 12/32 DLCflexbar-PT-4b-CTLFireability-11 1527267 m, 19779 m/sec, 11928537 t fired, .
Time elapsed: 286 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 152/247 13/32 DLCflexbar-PT-4b-CTLFireability-11 1623817 m, 19310 m/sec, 12693984 t fired, .
Time elapsed: 291 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 157/247 14/32 DLCflexbar-PT-4b-CTLFireability-11 1707981 m, 16832 m/sec, 13356785 t fired, .
Time elapsed: 296 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 162/247 15/32 DLCflexbar-PT-4b-CTLFireability-11 1823464 m, 23096 m/sec, 14272181 t fired, .
Time elapsed: 301 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 167/247 15/32 DLCflexbar-PT-4b-CTLFireability-11 1914164 m, 18140 m/sec, 14999987 t fired, .
Time elapsed: 306 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 172/247 16/32 DLCflexbar-PT-4b-CTLFireability-11 2015070 m, 20181 m/sec, 15812001 t fired, .
Time elapsed: 311 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 177/247 17/32 DLCflexbar-PT-4b-CTLFireability-11 2118257 m, 20637 m/sec, 16665816 t fired, .
Time elapsed: 316 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 182/247 17/32 DLCflexbar-PT-4b-CTLFireability-11 2197452 m, 15839 m/sec, 17302836 t fired, .
Time elapsed: 321 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 188/247 18/32 DLCflexbar-PT-4b-CTLFireability-11 2230950 m, 6699 m/sec, 17564017 t fired, .
Time elapsed: 327 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4b-CTLFireability-01: EF true state space
DLCflexbar-PT-4b-CTLFireability-04: EG true state space / EG
DLCflexbar-PT-4b-CTLFireability-06: DISJ true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4b-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 207/247 18/32 DLCflexbar-PT-4b-CTLFireability-11 2237141 m, 1238 m/sec, 17614092 t fired, .
Time elapsed: 347 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 375 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000546"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4b.tgz
mv DLCflexbar-PT-4b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;